================ @@ -3657,14 +3611,18 @@ mlir::LogicalResult CIRToLLVMVecCmpOpLowering::matchAndRewrite( } // LLVM IR vector comparison returns a vector of i1. This one-bit vector - // must be sign-extended to the correct result type, unless a vector of i1 is - // the type we need. - if (cast<cir::IntType>(cast<cir::VectorType>(op.getType()).getElementType()) - .getWidth() > 1) - rewriter.replaceOpWithNewOp<mlir::LLVM::SExtOp>( - op, typeConverter->convertType(op.getType()), bitResult); - else - rewriter.replaceOp(op, bitResult); + // must be sign-extended to the correct result type. + auto vecElementType = elementTypeIfVector(op.getType()); ---------------- Lancern wrote:
```suggestion mlir::Type vecElementType = elementTypeIfVector(op.getType()); ``` https://github.com/llvm/llvm-project/pull/174318 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
