Author: Rana Pratap Reddy Date: 2026-01-10T20:37:16+05:30 New Revision: 7c6162fc5994f0389f2c079772497facbfe39a38
URL: https://github.com/llvm/llvm-project/commit/7c6162fc5994f0389f2c079772497facbfe39a38 DIFF: https://github.com/llvm/llvm-project/commit/7c6162fc5994f0389f2c079772497facbfe39a38.diff LOG: [AMDGPU] Modifies mfma builtin def to take _Float16 for HIP/C++ (#175197) For mfma builtins, using 'x' to take _Float16 for HIP/C++ and half for OpenCL. Added: clang/test/CodeGenHIP/builtins-amdgcn-mfma-gfx908.hip clang/test/CodeGenHIP/builtins-amdgcn-mfma-gfx942.hip clang/test/CodeGenHIP/builtins-amdgcn-mfma-gfx950.hip Modified: clang/include/clang/Basic/BuiltinsAMDGPU.def Removed: ################################################################################ diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def b/clang/include/clang/Basic/BuiltinsAMDGPU.def index f189e34aac707..56d00161cc52f 100644 --- a/clang/include/clang/Basic/BuiltinsAMDGPU.def +++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def @@ -433,11 +433,11 @@ TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_16x16x1f32, "V16fffV16fIiIiIi", "nc", " TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_4x4x1f32, "V4fffV4fIiIiIi", "nc", "mai-insts") TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_32x32x2f32, "V16fffV16fIiIiIi", "nc", "mai-insts") TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_16x16x4f32, "V4fffV4fIiIiIi", "nc", "mai-insts") -TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_32x32x4f16, "V32fV4hV4hV32fIiIiIi", "nc", "mai-insts") -TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_16x16x4f16, "V16fV4hV4hV16fIiIiIi", "nc", "mai-insts") -TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_4x4x4f16, "V4fV4hV4hV4fIiIiIi", "nc", "mai-insts") -TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_32x32x8f16, "V16fV4hV4hV16fIiIiIi", "nc", "mai-insts") -TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_16x16x16f16, "V4fV4hV4hV4fIiIiIi", "nc", "mai-insts") +TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_32x32x4f16, "V32fV4xV4xV32fIiIiIi", "nc", "mai-insts") +TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_16x16x4f16, "V16fV4xV4xV16fIiIiIi", "nc", "mai-insts") +TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_4x4x4f16, "V4fV4xV4xV4fIiIiIi", "nc", "mai-insts") +TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_32x32x8f16, "V16fV4xV4xV16fIiIiIi", "nc", "mai-insts") +TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_16x16x16f16, "V4fV4xV4xV4fIiIiIi", "nc", "mai-insts") TARGET_BUILTIN(__builtin_amdgcn_mfma_i32_32x32x4i8, "V32iiiV32iIiIiIi", "nc", "mai-insts") TARGET_BUILTIN(__builtin_amdgcn_mfma_i32_16x16x4i8, "V16iiiV16iIiIiIi", "nc", "mai-insts") TARGET_BUILTIN(__builtin_amdgcn_mfma_i32_4x4x4i8, "V4iiiV4iIiIiIi", "nc", "mai-insts") @@ -469,8 +469,8 @@ TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_32x32x16_bf8_bf8, "V16fWiWiV16fIiIiIi", TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_32x32x16_bf8_fp8, "V16fWiWiV16fIiIiIi", "nc", "fp8-insts") TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_32x32x16_fp8_bf8, "V16fWiWiV16fIiIiIi", "nc", "fp8-insts") TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_32x32x16_fp8_fp8, "V16fWiWiV16fIiIiIi", "nc", "fp8-insts") -TARGET_BUILTIN(__builtin_amdgcn_smfmac_f32_16x16x32_f16, "V4fV4hV8hV4fiIiIi", "nc", "mai-insts") -TARGET_BUILTIN(__builtin_amdgcn_smfmac_f32_32x32x16_f16, "V16fV4hV8hV16fiIiIi", "nc", "mai-insts") +TARGET_BUILTIN(__builtin_amdgcn_smfmac_f32_16x16x32_f16, "V4fV4xV8xV4fiIiIi", "nc", "mai-insts") +TARGET_BUILTIN(__builtin_amdgcn_smfmac_f32_32x32x16_f16, "V16fV4xV8xV16fiIiIi", "nc", "mai-insts") TARGET_BUILTIN(__builtin_amdgcn_smfmac_f32_16x16x32_bf16, "V4fV4sV8sV4fiIiIi", "nc", "mai-insts") TARGET_BUILTIN(__builtin_amdgcn_smfmac_f32_32x32x16_bf16, "V16fV4sV8sV16fiIiIi", "nc", "mai-insts") TARGET_BUILTIN(__builtin_amdgcn_smfmac_i32_16x16x64_i8, "V4iV2iV4iV4iiIiIi", "nc", "mai-insts") @@ -500,15 +500,15 @@ TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_fp8_f32, "ifiiIi", "nc", "fp8-conversion- TARGET_BUILTIN(__builtin_amdgcn_mfma_scale_f32_16x16x128_f8f6f4, "V4fV8ZiV8ZiV4fIiIiIiiIii", "nc", "gfx950-insts") TARGET_BUILTIN(__builtin_amdgcn_mfma_scale_f32_32x32x64_f8f6f4, "V16fV8ZiV8ZiV16fIiIiIiiIii", "nc", "gfx950-insts") -TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_16x16x32_f16, "V4fV8hV8hV4fIiIiIi", "nc", "gfx950-insts") +TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_16x16x32_f16, "V4fV8xV8xV4fIiIiIi", "nc", "gfx950-insts") TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_16x16x32_bf16, "V4fV8yV8yV4fIiIiIi", "nc", "gfx950-insts") -TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_32x32x16_f16, "V16fV8hV8hV16fIiIiIi", "nc", "gfx950-insts") +TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_32x32x16_f16, "V16fV8xV8xV16fIiIiIi", "nc", "gfx950-insts") TARGET_BUILTIN(__builtin_amdgcn_mfma_f32_32x32x16_bf16, "V16fV8yV8yV16fIiIiIi", "nc", "gfx950-insts") TARGET_BUILTIN(__builtin_amdgcn_mfma_i32_16x16x64_i8, "V4iV4iV4iV4iIiIiIi", "nc", "gfx950-insts") TARGET_BUILTIN(__builtin_amdgcn_mfma_i32_32x32x32_i8, "V16iV4iV4iV16iIiIiIi", "nc", "gfx950-insts") -TARGET_BUILTIN(__builtin_amdgcn_smfmac_f32_16x16x64_f16, "V4fV8hV16hV4fiIiIi", "nc", "gfx950-insts") -TARGET_BUILTIN(__builtin_amdgcn_smfmac_f32_32x32x32_f16, "V16fV8hV16hV16fiIiIi", "nc", "gfx950-insts") +TARGET_BUILTIN(__builtin_amdgcn_smfmac_f32_16x16x64_f16, "V4fV8xV16xV4fiIiIi", "nc", "gfx950-insts") +TARGET_BUILTIN(__builtin_amdgcn_smfmac_f32_32x32x32_f16, "V16fV8xV16xV16fiIiIi", "nc", "gfx950-insts") TARGET_BUILTIN(__builtin_amdgcn_smfmac_f32_16x16x64_bf16, "V4fV8yV16yV4fiIiIi", "nc", "gfx950-insts") TARGET_BUILTIN(__builtin_amdgcn_smfmac_f32_32x32x32_bf16, "V16fV8yV16yV16fiIiIi", "nc", "gfx950-insts") TARGET_BUILTIN(__builtin_amdgcn_smfmac_i32_16x16x128_i8, "V4iV4iV8iV4iiIiIi", "nc", "gfx950-insts") diff --git a/clang/test/CodeGenHIP/builtins-amdgcn-mfma-gfx908.hip b/clang/test/CodeGenHIP/builtins-amdgcn-mfma-gfx908.hip new file mode 100644 index 0000000000000..0a10fc1865748 --- /dev/null +++ b/clang/test/CodeGenHIP/builtins-amdgcn-mfma-gfx908.hip @@ -0,0 +1,147 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 +// REQUIRES: amdgpu-registered-target +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx908 -emit-llvm -fcuda-is-device -o - %s | FileCheck %s --check-prefix=CHECK-GFX908 + +#define __device__ __attribute__((device)) + +typedef float v4f __attribute__((ext_vector_type(4))); +typedef float v16f __attribute__((ext_vector_type(16))); +typedef float v32f __attribute__((ext_vector_type(32))); +typedef _Float16 v4h __attribute__((ext_vector_type(4))); +typedef _Float16 v8h __attribute__((ext_vector_type(8))); +typedef _Float16 v16h __attribute__((ext_vector_type(16))); + +// CHECK-GFX908-LABEL: define dso_local void @_Z28test_mfma_f32_32x32x4f16_hipPDv32_fDv4_DF16_S1_S_( +// CHECK-GFX908-SAME: ptr noundef [[OUT:%.*]], <4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], <32 x float> noundef [[C:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-GFX908-NEXT: [[ENTRY:.*:]] +// CHECK-GFX908-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-GFX908-NEXT: [[A_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) +// CHECK-GFX908-NEXT: [[B_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) +// CHECK-GFX908-NEXT: [[C_ADDR:%.*]] = alloca <32 x float>, align 128, addrspace(5) +// CHECK-GFX908-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr +// CHECK-GFX908-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-GFX908-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-GFX908-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr +// CHECK-GFX908-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <4 x half> [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <4 x half> [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <32 x float> [[C]], ptr [[C_ADDR_ASCAST]], align 128 +// CHECK-GFX908-NEXT: [[TMP0:%.*]] = load <4 x half>, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: [[TMP1:%.*]] = load <4 x half>, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: [[TMP2:%.*]] = load <32 x float>, ptr [[C_ADDR_ASCAST]], align 128 +// CHECK-GFX908-NEXT: [[TMP3:%.*]] = call contract <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> [[TMP0]], <4 x half> [[TMP1]], <32 x float> [[TMP2]], i32 0, i32 0, i32 0) +// CHECK-GFX908-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <32 x float> [[TMP3]], ptr [[TMP4]], align 128 +// CHECK-GFX908-NEXT: ret void +// +__device__ void test_mfma_f32_32x32x4f16_hip(v32f* out, v4h a, v4h b, v32f c) { + *out = __builtin_amdgcn_mfma_f32_32x32x4f16(a, b, c, 0, 0, 0); +} + +// CHECK-GFX908-LABEL: define dso_local void @_Z28test_mfma_f32_16x16x4f16_hipPDv16_fDv4_DF16_S1_S_( +// CHECK-GFX908-SAME: ptr noundef [[OUT:%.*]], <4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], <16 x float> noundef [[C:%.*]]) #[[ATTR0]] { +// CHECK-GFX908-NEXT: [[ENTRY:.*:]] +// CHECK-GFX908-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-GFX908-NEXT: [[A_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) +// CHECK-GFX908-NEXT: [[B_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) +// CHECK-GFX908-NEXT: [[C_ADDR:%.*]] = alloca <16 x float>, align 64, addrspace(5) +// CHECK-GFX908-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr +// CHECK-GFX908-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-GFX908-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-GFX908-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr +// CHECK-GFX908-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <4 x half> [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <4 x half> [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <16 x float> [[C]], ptr [[C_ADDR_ASCAST]], align 64 +// CHECK-GFX908-NEXT: [[TMP0:%.*]] = load <4 x half>, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: [[TMP1:%.*]] = load <4 x half>, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: [[TMP2:%.*]] = load <16 x float>, ptr [[C_ADDR_ASCAST]], align 64 +// CHECK-GFX908-NEXT: [[TMP3:%.*]] = call contract <16 x float> @llvm.amdgcn.mfma.f32.16x16x4f16(<4 x half> [[TMP0]], <4 x half> [[TMP1]], <16 x float> [[TMP2]], i32 0, i32 0, i32 0) +// CHECK-GFX908-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <16 x float> [[TMP3]], ptr [[TMP4]], align 64 +// CHECK-GFX908-NEXT: ret void +// +__device__ void test_mfma_f32_16x16x4f16_hip(v16f* out, v4h a, v4h b, v16f c) { + *out = __builtin_amdgcn_mfma_f32_16x16x4f16(a, b, c, 0, 0, 0); +} + +// CHECK-GFX908-LABEL: define dso_local void @_Z26test_mfma_f32_4x4x4f16_hipPDv4_fDv4_DF16_S1_S_( +// CHECK-GFX908-SAME: ptr noundef [[OUT:%.*]], <4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], <4 x float> noundef [[C:%.*]]) #[[ATTR0]] { +// CHECK-GFX908-NEXT: [[ENTRY:.*:]] +// CHECK-GFX908-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-GFX908-NEXT: [[A_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) +// CHECK-GFX908-NEXT: [[B_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) +// CHECK-GFX908-NEXT: [[C_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) +// CHECK-GFX908-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr +// CHECK-GFX908-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-GFX908-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-GFX908-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr +// CHECK-GFX908-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <4 x half> [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <4 x half> [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <4 x float> [[C]], ptr [[C_ADDR_ASCAST]], align 16 +// CHECK-GFX908-NEXT: [[TMP0:%.*]] = load <4 x half>, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: [[TMP1:%.*]] = load <4 x half>, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[C_ADDR_ASCAST]], align 16 +// CHECK-GFX908-NEXT: [[TMP3:%.*]] = call contract <4 x float> @llvm.amdgcn.mfma.f32.4x4x4f16(<4 x half> [[TMP0]], <4 x half> [[TMP1]], <4 x float> [[TMP2]], i32 0, i32 0, i32 0) +// CHECK-GFX908-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <4 x float> [[TMP3]], ptr [[TMP4]], align 16 +// CHECK-GFX908-NEXT: ret void +// +__device__ void test_mfma_f32_4x4x4f16_hip(v4f* out, v4h a, v4h b, v4f c) { + *out = __builtin_amdgcn_mfma_f32_4x4x4f16(a, b, c, 0, 0, 0); +} + +// CHECK-GFX908-LABEL: define dso_local void @_Z28test_mfma_f32_32x32x8f16_hipPDv16_fDv4_DF16_S1_S_( +// CHECK-GFX908-SAME: ptr noundef [[OUT:%.*]], <4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], <16 x float> noundef [[C:%.*]]) #[[ATTR0]] { +// CHECK-GFX908-NEXT: [[ENTRY:.*:]] +// CHECK-GFX908-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-GFX908-NEXT: [[A_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) +// CHECK-GFX908-NEXT: [[B_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) +// CHECK-GFX908-NEXT: [[C_ADDR:%.*]] = alloca <16 x float>, align 64, addrspace(5) +// CHECK-GFX908-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr +// CHECK-GFX908-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-GFX908-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-GFX908-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr +// CHECK-GFX908-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <4 x half> [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <4 x half> [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <16 x float> [[C]], ptr [[C_ADDR_ASCAST]], align 64 +// CHECK-GFX908-NEXT: [[TMP0:%.*]] = load <4 x half>, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: [[TMP1:%.*]] = load <4 x half>, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: [[TMP2:%.*]] = load <16 x float>, ptr [[C_ADDR_ASCAST]], align 64 +// CHECK-GFX908-NEXT: [[TMP3:%.*]] = call contract <16 x float> @llvm.amdgcn.mfma.f32.32x32x8f16(<4 x half> [[TMP0]], <4 x half> [[TMP1]], <16 x float> [[TMP2]], i32 0, i32 0, i32 0) +// CHECK-GFX908-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <16 x float> [[TMP3]], ptr [[TMP4]], align 64 +// CHECK-GFX908-NEXT: ret void +// +__device__ void test_mfma_f32_32x32x8f16_hip(v16f* out, v4h a, v4h b, v16f c) { + *out = __builtin_amdgcn_mfma_f32_32x32x8f16(a, b, c, 0, 0, 0); +} + +// CHECK-GFX908-LABEL: define dso_local void @_Z29test_mfma_f32_16x16x16f16_hipPDv4_fDv4_DF16_S1_S_( +// CHECK-GFX908-SAME: ptr noundef [[OUT:%.*]], <4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], <4 x float> noundef [[C:%.*]]) #[[ATTR0]] { +// CHECK-GFX908-NEXT: [[ENTRY:.*:]] +// CHECK-GFX908-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-GFX908-NEXT: [[A_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) +// CHECK-GFX908-NEXT: [[B_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) +// CHECK-GFX908-NEXT: [[C_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) +// CHECK-GFX908-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr +// CHECK-GFX908-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-GFX908-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-GFX908-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr +// CHECK-GFX908-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <4 x half> [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <4 x half> [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <4 x float> [[C]], ptr [[C_ADDR_ASCAST]], align 16 +// CHECK-GFX908-NEXT: [[TMP0:%.*]] = load <4 x half>, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: [[TMP1:%.*]] = load <4 x half>, ptr [[B_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[C_ADDR_ASCAST]], align 16 +// CHECK-GFX908-NEXT: [[TMP3:%.*]] = call contract <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> [[TMP0]], <4 x half> [[TMP1]], <4 x float> [[TMP2]], i32 0, i32 0, i32 0) +// CHECK-GFX908-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX908-NEXT: store <4 x float> [[TMP3]], ptr [[TMP4]], align 16 +// CHECK-GFX908-NEXT: ret void +// +__device__ void test_mfma_f32_16x16x16f16_hip(v4f* out, v4h a, v4h b, v4f c) { + *out = __builtin_amdgcn_mfma_f32_16x16x16f16(a, b, c, 0, 0, 0); +} diff --git a/clang/test/CodeGenHIP/builtins-amdgcn-mfma-gfx942.hip b/clang/test/CodeGenHIP/builtins-amdgcn-mfma-gfx942.hip new file mode 100644 index 0000000000000..5227e32ebbb8e --- /dev/null +++ b/clang/test/CodeGenHIP/builtins-amdgcn-mfma-gfx942.hip @@ -0,0 +1,74 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 +// REQUIRES: amdgpu-registered-target +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx942 -emit-llvm -fcuda-is-device -o - %s | FileCheck %s --check-prefix=CHECK-GFX942 + +#define __device__ __attribute__((device)) + +typedef float v4f __attribute__((ext_vector_type(4))); +typedef float v16f __attribute__((ext_vector_type(16))); +typedef float v32f __attribute__((ext_vector_type(32))); +typedef _Float16 v4h __attribute__((ext_vector_type(4))); +typedef _Float16 v8h __attribute__((ext_vector_type(8))); +typedef _Float16 v16h __attribute__((ext_vector_type(16))); + +// CHECK-GFX942-LABEL: define dso_local void @_Z32test_smfmac_f32_16x16x32_f16_hipPDv4_fDv4_DF16_Dv8_DF16_S_i( +// CHECK-GFX942-SAME: ptr noundef [[OUT:%.*]], <4 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]], <4 x float> noundef [[C:%.*]], i32 noundef [[IDX:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-GFX942-NEXT: [[ENTRY:.*:]] +// CHECK-GFX942-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-GFX942-NEXT: [[A_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) +// CHECK-GFX942-NEXT: [[B_ADDR:%.*]] = alloca <8 x half>, align 16, addrspace(5) +// CHECK-GFX942-NEXT: [[C_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) +// CHECK-GFX942-NEXT: [[IDX_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-GFX942-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr +// CHECK-GFX942-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-GFX942-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-GFX942-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr +// CHECK-GFX942-NEXT: [[IDX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[IDX_ADDR]] to ptr +// CHECK-GFX942-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX942-NEXT: store <4 x half> [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-GFX942-NEXT: store <8 x half> [[B]], ptr [[B_ADDR_ASCAST]], align 16 +// CHECK-GFX942-NEXT: store <4 x float> [[C]], ptr [[C_ADDR_ASCAST]], align 16 +// CHECK-GFX942-NEXT: store i32 [[IDX]], ptr [[IDX_ADDR_ASCAST]], align 4 +// CHECK-GFX942-NEXT: [[TMP0:%.*]] = load <4 x half>, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-GFX942-NEXT: [[TMP1:%.*]] = load <8 x half>, ptr [[B_ADDR_ASCAST]], align 16 +// CHECK-GFX942-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[C_ADDR_ASCAST]], align 16 +// CHECK-GFX942-NEXT: [[TMP3:%.*]] = load i32, ptr [[IDX_ADDR_ASCAST]], align 4 +// CHECK-GFX942-NEXT: [[TMP4:%.*]] = call contract <4 x float> @llvm.amdgcn.smfmac.f32.16x16x32.f16(<4 x half> [[TMP0]], <8 x half> [[TMP1]], <4 x float> [[TMP2]], i32 [[TMP3]], i32 0, i32 0) +// CHECK-GFX942-NEXT: [[TMP5:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX942-NEXT: store <4 x float> [[TMP4]], ptr [[TMP5]], align 16 +// CHECK-GFX942-NEXT: ret void +// +__device__ void test_smfmac_f32_16x16x32_f16_hip(v4f* out, v4h a, v8h b, v4f c, int idx) { + *out = __builtin_amdgcn_smfmac_f32_16x16x32_f16(a, b, c, idx, 0, 0); +} + +// CHECK-GFX942-LABEL: define dso_local void @_Z32test_smfmac_f32_32x32x16_f16_hipPDv16_fDv4_DF16_Dv8_DF16_S_i( +// CHECK-GFX942-SAME: ptr noundef [[OUT:%.*]], <4 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]], <16 x float> noundef [[C:%.*]], i32 noundef [[IDX:%.*]]) #[[ATTR0]] { +// CHECK-GFX942-NEXT: [[ENTRY:.*:]] +// CHECK-GFX942-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-GFX942-NEXT: [[A_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) +// CHECK-GFX942-NEXT: [[B_ADDR:%.*]] = alloca <8 x half>, align 16, addrspace(5) +// CHECK-GFX942-NEXT: [[C_ADDR:%.*]] = alloca <16 x float>, align 64, addrspace(5) +// CHECK-GFX942-NEXT: [[IDX_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-GFX942-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr +// CHECK-GFX942-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-GFX942-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-GFX942-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr +// CHECK-GFX942-NEXT: [[IDX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[IDX_ADDR]] to ptr +// CHECK-GFX942-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX942-NEXT: store <4 x half> [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-GFX942-NEXT: store <8 x half> [[B]], ptr [[B_ADDR_ASCAST]], align 16 +// CHECK-GFX942-NEXT: store <16 x float> [[C]], ptr [[C_ADDR_ASCAST]], align 64 +// CHECK-GFX942-NEXT: store i32 [[IDX]], ptr [[IDX_ADDR_ASCAST]], align 4 +// CHECK-GFX942-NEXT: [[TMP0:%.*]] = load <4 x half>, ptr [[A_ADDR_ASCAST]], align 8 +// CHECK-GFX942-NEXT: [[TMP1:%.*]] = load <8 x half>, ptr [[B_ADDR_ASCAST]], align 16 +// CHECK-GFX942-NEXT: [[TMP2:%.*]] = load <16 x float>, ptr [[C_ADDR_ASCAST]], align 64 +// CHECK-GFX942-NEXT: [[TMP3:%.*]] = load i32, ptr [[IDX_ADDR_ASCAST]], align 4 +// CHECK-GFX942-NEXT: [[TMP4:%.*]] = call contract <16 x float> @llvm.amdgcn.smfmac.f32.32x32x16.f16(<4 x half> [[TMP0]], <8 x half> [[TMP1]], <16 x float> [[TMP2]], i32 [[TMP3]], i32 0, i32 0) +// CHECK-GFX942-NEXT: [[TMP5:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX942-NEXT: store <16 x float> [[TMP4]], ptr [[TMP5]], align 64 +// CHECK-GFX942-NEXT: ret void +// +__device__ void test_smfmac_f32_32x32x16_f16_hip(v16f* out, v4h a, v8h b, v16f c, int idx) { + *out = __builtin_amdgcn_smfmac_f32_32x32x16_f16(a, b, c, idx, 0, 0); +} diff --git a/clang/test/CodeGenHIP/builtins-amdgcn-mfma-gfx950.hip b/clang/test/CodeGenHIP/builtins-amdgcn-mfma-gfx950.hip new file mode 100644 index 0000000000000..11ce4ad1fa9ee --- /dev/null +++ b/clang/test/CodeGenHIP/builtins-amdgcn-mfma-gfx950.hip @@ -0,0 +1,128 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 +// REQUIRES: amdgpu-registered-target +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx950 -emit-llvm -fcuda-is-device -o - %s | FileCheck %s --check-prefix=CHECK-GFX950 + +#define __device__ __attribute__((device)) + +typedef float v4f __attribute__((ext_vector_type(4))); +typedef float v16f __attribute__((ext_vector_type(16))); +typedef float v32f __attribute__((ext_vector_type(32))); +typedef _Float16 v4h __attribute__((ext_vector_type(4))); +typedef _Float16 v8h __attribute__((ext_vector_type(8))); +typedef _Float16 v16h __attribute__((ext_vector_type(16))); + +// CHECK-GFX950-LABEL: define dso_local void @_Z30test_mfma_f32_16x16x32_f16_hipPDv4_fDv8_DF16_S1_S_( +// CHECK-GFX950-SAME: ptr noundef [[OUT:%.*]], <8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]], <4 x float> noundef [[C:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-GFX950-NEXT: [[ENTRY:.*:]] +// CHECK-GFX950-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-GFX950-NEXT: [[A_ADDR:%.*]] = alloca <8 x half>, align 16, addrspace(5) +// CHECK-GFX950-NEXT: [[B_ADDR:%.*]] = alloca <8 x half>, align 16, addrspace(5) +// CHECK-GFX950-NEXT: [[C_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) +// CHECK-GFX950-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr +// CHECK-GFX950-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-GFX950-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-GFX950-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr +// CHECK-GFX950-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX950-NEXT: store <8 x half> [[A]], ptr [[A_ADDR_ASCAST]], align 16 +// CHECK-GFX950-NEXT: store <8 x half> [[B]], ptr [[B_ADDR_ASCAST]], align 16 +// CHECK-GFX950-NEXT: store <4 x float> [[C]], ptr [[C_ADDR_ASCAST]], align 16 +// CHECK-GFX950-NEXT: [[TMP0:%.*]] = load <8 x half>, ptr [[A_ADDR_ASCAST]], align 16 +// CHECK-GFX950-NEXT: [[TMP1:%.*]] = load <8 x half>, ptr [[B_ADDR_ASCAST]], align 16 +// CHECK-GFX950-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[C_ADDR_ASCAST]], align 16 +// CHECK-GFX950-NEXT: [[TMP3:%.*]] = call contract <4 x float> @llvm.amdgcn.mfma.f32.16x16x32.f16(<8 x half> [[TMP0]], <8 x half> [[TMP1]], <4 x float> [[TMP2]], i32 0, i32 0, i32 0) +// CHECK-GFX950-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX950-NEXT: store <4 x float> [[TMP3]], ptr [[TMP4]], align 16 +// CHECK-GFX950-NEXT: ret void +// +__device__ void test_mfma_f32_16x16x32_f16_hip(v4f* out, v8h a, v8h b, v4f c) { + *out = __builtin_amdgcn_mfma_f32_16x16x32_f16(a, b, c, 0, 0, 0); +} + +// CHECK-GFX950-LABEL: define dso_local void @_Z30test_mfma_f32_32x32x16_f16_hipPDv16_fDv8_DF16_S1_S_( +// CHECK-GFX950-SAME: ptr noundef [[OUT:%.*]], <8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]], <16 x float> noundef [[C:%.*]]) #[[ATTR0]] { +// CHECK-GFX950-NEXT: [[ENTRY:.*:]] +// CHECK-GFX950-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-GFX950-NEXT: [[A_ADDR:%.*]] = alloca <8 x half>, align 16, addrspace(5) +// CHECK-GFX950-NEXT: [[B_ADDR:%.*]] = alloca <8 x half>, align 16, addrspace(5) +// CHECK-GFX950-NEXT: [[C_ADDR:%.*]] = alloca <16 x float>, align 64, addrspace(5) +// CHECK-GFX950-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr +// CHECK-GFX950-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-GFX950-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-GFX950-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr +// CHECK-GFX950-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX950-NEXT: store <8 x half> [[A]], ptr [[A_ADDR_ASCAST]], align 16 +// CHECK-GFX950-NEXT: store <8 x half> [[B]], ptr [[B_ADDR_ASCAST]], align 16 +// CHECK-GFX950-NEXT: store <16 x float> [[C]], ptr [[C_ADDR_ASCAST]], align 64 +// CHECK-GFX950-NEXT: [[TMP0:%.*]] = load <8 x half>, ptr [[A_ADDR_ASCAST]], align 16 +// CHECK-GFX950-NEXT: [[TMP1:%.*]] = load <8 x half>, ptr [[B_ADDR_ASCAST]], align 16 +// CHECK-GFX950-NEXT: [[TMP2:%.*]] = load <16 x float>, ptr [[C_ADDR_ASCAST]], align 64 +// CHECK-GFX950-NEXT: [[TMP3:%.*]] = call contract <16 x float> @llvm.amdgcn.mfma.f32.32x32x16.f16(<8 x half> [[TMP0]], <8 x half> [[TMP1]], <16 x float> [[TMP2]], i32 0, i32 0, i32 0) +// CHECK-GFX950-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX950-NEXT: store <16 x float> [[TMP3]], ptr [[TMP4]], align 64 +// CHECK-GFX950-NEXT: ret void +// +__device__ void test_mfma_f32_32x32x16_f16_hip(v16f* out, v8h a, v8h b, v16f c) { + *out = __builtin_amdgcn_mfma_f32_32x32x16_f16(a, b, c, 0, 0, 0); +} + +// CHECK-GFX950-LABEL: define dso_local void @_Z36test_smfmac_f32_16x16x64_f16_950_hipPDv4_fDv8_DF16_Dv16_DF16_S_i( +// CHECK-GFX950-SAME: ptr noundef [[OUT:%.*]], <8 x half> noundef [[A:%.*]], <16 x half> noundef [[B:%.*]], <4 x float> noundef [[C:%.*]], i32 noundef [[IDX:%.*]]) #[[ATTR0]] { +// CHECK-GFX950-NEXT: [[ENTRY:.*:]] +// CHECK-GFX950-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-GFX950-NEXT: [[A_ADDR:%.*]] = alloca <8 x half>, align 16, addrspace(5) +// CHECK-GFX950-NEXT: [[B_ADDR:%.*]] = alloca <16 x half>, align 32, addrspace(5) +// CHECK-GFX950-NEXT: [[C_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) +// CHECK-GFX950-NEXT: [[IDX_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-GFX950-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr +// CHECK-GFX950-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-GFX950-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-GFX950-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr +// CHECK-GFX950-NEXT: [[IDX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[IDX_ADDR]] to ptr +// CHECK-GFX950-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX950-NEXT: store <8 x half> [[A]], ptr [[A_ADDR_ASCAST]], align 16 +// CHECK-GFX950-NEXT: store <16 x half> [[B]], ptr [[B_ADDR_ASCAST]], align 32 +// CHECK-GFX950-NEXT: store <4 x float> [[C]], ptr [[C_ADDR_ASCAST]], align 16 +// CHECK-GFX950-NEXT: store i32 [[IDX]], ptr [[IDX_ADDR_ASCAST]], align 4 +// CHECK-GFX950-NEXT: [[TMP0:%.*]] = load <8 x half>, ptr [[A_ADDR_ASCAST]], align 16 +// CHECK-GFX950-NEXT: [[TMP1:%.*]] = load <16 x half>, ptr [[B_ADDR_ASCAST]], align 32 +// CHECK-GFX950-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[C_ADDR_ASCAST]], align 16 +// CHECK-GFX950-NEXT: [[TMP3:%.*]] = load i32, ptr [[IDX_ADDR_ASCAST]], align 4 +// CHECK-GFX950-NEXT: [[TMP4:%.*]] = call contract <4 x float> @llvm.amdgcn.smfmac.f32.16x16x64.f16(<8 x half> [[TMP0]], <16 x half> [[TMP1]], <4 x float> [[TMP2]], i32 [[TMP3]], i32 0, i32 0) +// CHECK-GFX950-NEXT: [[TMP5:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX950-NEXT: store <4 x float> [[TMP4]], ptr [[TMP5]], align 16 +// CHECK-GFX950-NEXT: ret void +// +__device__ void test_smfmac_f32_16x16x64_f16_950_hip(v4f* out, v8h a, v16h b, v4f c, int idx) { + *out = __builtin_amdgcn_smfmac_f32_16x16x64_f16(a, b, c, idx, 0, 0); +} + +// CHECK-GFX950-LABEL: define dso_local void @_Z36test_smfmac_f32_32x32x32_f16_950_hipPDv16_fDv8_DF16_Dv16_DF16_S_i( +// CHECK-GFX950-SAME: ptr noundef [[OUT:%.*]], <8 x half> noundef [[A:%.*]], <16 x half> noundef [[B:%.*]], <16 x float> noundef [[C:%.*]], i32 noundef [[IDX:%.*]]) #[[ATTR0]] { +// CHECK-GFX950-NEXT: [[ENTRY:.*:]] +// CHECK-GFX950-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-GFX950-NEXT: [[A_ADDR:%.*]] = alloca <8 x half>, align 16, addrspace(5) +// CHECK-GFX950-NEXT: [[B_ADDR:%.*]] = alloca <16 x half>, align 32, addrspace(5) +// CHECK-GFX950-NEXT: [[C_ADDR:%.*]] = alloca <16 x float>, align 64, addrspace(5) +// CHECK-GFX950-NEXT: [[IDX_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-GFX950-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr +// CHECK-GFX950-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// CHECK-GFX950-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// CHECK-GFX950-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr +// CHECK-GFX950-NEXT: [[IDX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[IDX_ADDR]] to ptr +// CHECK-GFX950-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX950-NEXT: store <8 x half> [[A]], ptr [[A_ADDR_ASCAST]], align 16 +// CHECK-GFX950-NEXT: store <16 x half> [[B]], ptr [[B_ADDR_ASCAST]], align 32 +// CHECK-GFX950-NEXT: store <16 x float> [[C]], ptr [[C_ADDR_ASCAST]], align 64 +// CHECK-GFX950-NEXT: store i32 [[IDX]], ptr [[IDX_ADDR_ASCAST]], align 4 +// CHECK-GFX950-NEXT: [[TMP0:%.*]] = load <8 x half>, ptr [[A_ADDR_ASCAST]], align 16 +// CHECK-GFX950-NEXT: [[TMP1:%.*]] = load <16 x half>, ptr [[B_ADDR_ASCAST]], align 32 +// CHECK-GFX950-NEXT: [[TMP2:%.*]] = load <16 x float>, ptr [[C_ADDR_ASCAST]], align 64 +// CHECK-GFX950-NEXT: [[TMP3:%.*]] = load i32, ptr [[IDX_ADDR_ASCAST]], align 4 +// CHECK-GFX950-NEXT: [[TMP4:%.*]] = call contract <16 x float> @llvm.amdgcn.smfmac.f32.32x32x32.f16(<8 x half> [[TMP0]], <16 x half> [[TMP1]], <16 x float> [[TMP2]], i32 [[TMP3]], i32 0, i32 0) +// CHECK-GFX950-NEXT: [[TMP5:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-GFX950-NEXT: store <16 x float> [[TMP4]], ptr [[TMP5]], align 64 +// CHECK-GFX950-NEXT: ret void +// +__device__ void test_smfmac_f32_32x32x32_f16_950_hip(v16f* out, v8h a, v16h b, v16f c, int idx) { + *out = __builtin_amdgcn_smfmac_f32_32x32x32_f16(a, b, c, idx, 0, 0); +} _______________________________________________ cfe-commits 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