llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Piyou Chen (BeMg) <details> <summary>Changes</summary> fa57074d146925a303263905af415cc78f58f353 constraint the RISCV BitInt with 128 bits. It is due to fp <-> int convension will crash in backend. (https://godbolt.org/z/9o1qr4rje) This patch enable larger than 128 bits BitInt type by `setMaxLargeFPConvertBitWidthSupported(128)`. --- Patch is 103.97 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/175515.diff 5 Files Affected: - (modified) clang/lib/Basic/Targets/RISCV.h (+4) - (modified) clang/test/CodeGen/RISCV/bitint.c (+218-36) - (modified) clang/test/CodeGen/ext-int-cc.c (-2) - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+2) - (added) llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll (+2175) ``````````diff diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h index 685735b54a45b..619d491d379d3 100644 --- a/clang/lib/Basic/Targets/RISCV.h +++ b/clang/lib/Basic/Targets/RISCV.h @@ -109,6 +109,10 @@ class RISCVTargetInfo : public TargetInfo { bool hasBitIntType() const override { return true; } + size_t getMaxBitIntWidth() const override { + return llvm::IntegerType::MAX_INT_BITS; + } + bool hasBFloat16Type() const override { return true; } CallingConvCheckResult checkCallingConvention(CallingConv CC) const override; diff --git a/clang/test/CodeGen/RISCV/bitint.c b/clang/test/CodeGen/RISCV/bitint.c index 1ad43affac9e6..26ac3dbf7d1f9 100644 --- a/clang/test/CodeGen/RISCV/bitint.c +++ b/clang/test/CodeGen/RISCV/bitint.c @@ -145,25 +145,25 @@ _BitInt(32) test_bitint_32_add_default(_BitInt(32) a, _BitInt(32) b) { // RISCV32-LABEL: define {{[^@]+}}@test_bitint_65_add_unsigned // RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] { // RISCV32-NEXT: entry: -// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA6:![0-9]+]] +// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10:![0-9]+]] // RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i65 -// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA6]] +// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]] // RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i65 // RISCV32-NEXT: [[ADD:%.*]] = add i65 [[B]], [[A]] // RISCV32-NEXT: [[STOREDV4:%.*]] = zext i65 [[ADD]] to i128 -// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA6]] +// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]] // RISCV32-NEXT: ret void // // RISCV32_INT128-LABEL: define {{[^@]+}}@test_bitint_65_add_unsigned // RISCV32_INT128-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] { // RISCV32_INT128-NEXT: entry: -// RISCV32_INT128-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA6:![0-9]+]] +// RISCV32_INT128-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10:![0-9]+]] // RISCV32_INT128-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i65 -// RISCV32_INT128-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA6]] +// RISCV32_INT128-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]] // RISCV32_INT128-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i65 // RISCV32_INT128-NEXT: [[ADD:%.*]] = add i65 [[B]], [[A]] // RISCV32_INT128-NEXT: [[STOREDV4:%.*]] = zext i65 [[ADD]] to i128 -// RISCV32_INT128-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA6]] +// RISCV32_INT128-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]] // RISCV32_INT128-NEXT: ret void // unsigned _BitInt(65) test_bitint_65_add_unsigned(unsigned _BitInt(65) a, unsigned _BitInt(65) b) { @@ -179,25 +179,25 @@ unsigned _BitInt(65) test_bitint_65_add_unsigned(unsigned _BitInt(65) a, unsigne // RISCV32-LABEL: define {{[^@]+}}@test_bitint_65_add_signed // RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] { // RISCV32-NEXT: entry: -// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA6]] +// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10]] // RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i65 -// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA6]] +// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]] // RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i65 // RISCV32-NEXT: [[ADD:%.*]] = add nsw i65 [[B]], [[A]] // RISCV32-NEXT: [[STOREDV4:%.*]] = sext i65 [[ADD]] to i128 -// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA6]] +// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]] // RISCV32-NEXT: ret void // // RISCV32_INT128-LABEL: define {{[^@]+}}@test_bitint_65_add_signed // RISCV32_INT128-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] { // RISCV32_INT128-NEXT: entry: -// RISCV32_INT128-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA6]] +// RISCV32_INT128-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10]] // RISCV32_INT128-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i65 -// RISCV32_INT128-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA6]] +// RISCV32_INT128-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]] // RISCV32_INT128-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i65 // RISCV32_INT128-NEXT: [[ADD:%.*]] = add nsw i65 [[B]], [[A]] // RISCV32_INT128-NEXT: [[STOREDV4:%.*]] = sext i65 [[ADD]] to i128 -// RISCV32_INT128-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA6]] +// RISCV32_INT128-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]] // RISCV32_INT128-NEXT: ret void // signed _BitInt(65) test_bitint_65_add_signed(signed _BitInt(65) a, signed _BitInt(65) b) { @@ -213,25 +213,25 @@ signed _BitInt(65) test_bitint_65_add_signed(signed _BitInt(65) a, signed _BitIn // RISCV32-LABEL: define {{[^@]+}}@test_bitint_65_add_default // RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] { // RISCV32-NEXT: entry: -// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA6]] +// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10]] // RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i65 -// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA6]] +// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]] // RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i65 // RISCV32-NEXT: [[ADD:%.*]] = add nsw i65 [[B]], [[A]] // RISCV32-NEXT: [[STOREDV4:%.*]] = sext i65 [[ADD]] to i128 -// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA6]] +// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]] // RISCV32-NEXT: ret void // // RISCV32_INT128-LABEL: define {{[^@]+}}@test_bitint_65_add_default // RISCV32_INT128-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] { // RISCV32_INT128-NEXT: entry: -// RISCV32_INT128-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA6]] +// RISCV32_INT128-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10]] // RISCV32_INT128-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i65 -// RISCV32_INT128-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA6]] +// RISCV32_INT128-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]] // RISCV32_INT128-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i65 // RISCV32_INT128-NEXT: [[ADD:%.*]] = add nsw i65 [[B]], [[A]] // RISCV32_INT128-NEXT: [[STOREDV4:%.*]] = sext i65 [[ADD]] to i128 -// RISCV32_INT128-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA6]] +// RISCV32_INT128-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]] // RISCV32_INT128-NEXT: ret void // _BitInt(65) test_bitint_65_add_default(_BitInt(65) a, _BitInt(65) b) { @@ -248,25 +248,25 @@ _BitInt(65) test_bitint_65_add_default(_BitInt(65) a, _BitInt(65) b) { // RISCV32-LABEL: define {{[^@]+}}@test_bitint_77_add_unsigned // RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] { // RISCV32-NEXT: entry: -// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10:![0-9]+]] +// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA12:![0-9]+]] // RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i77 -// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]] +// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA12]] // RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i77 // RISCV32-NEXT: [[ADD:%.*]] = add i77 [[B]], [[A]] // RISCV32-NEXT: [[STOREDV4:%.*]] = zext i77 [[ADD]] to i128 -// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]] +// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA12]] // RISCV32-NEXT: ret void // // RISCV32_INT128-LABEL: define {{[^@]+}}@test_bitint_77_add_unsigned // RISCV32_INT128-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] { // RISCV32_INT128-NEXT: entry: -// RISCV32_INT128-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10:![0-9]+]] +// RISCV32_INT128-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA12:![0-9]+]] // RISCV32_INT128-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i77 -// RISCV32_INT128-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]] +// RISCV32_INT128-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA12]] // RISCV32_INT128-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i77 // RISCV32_INT128-NEXT: [[ADD:%.*]] = add i77 [[B]], [[A]] // RISCV32_INT128-NEXT: [[STOREDV4:%.*]] = zext i77 [[ADD]] to i128 -// RISCV32_INT128-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]] +// RISCV32_INT128-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA12]] // RISCV32_INT128-NEXT: ret void // unsigned _BitInt(77) test_bitint_77_add_unsigned(unsigned _BitInt(77) a, unsigned _BitInt(77) b) { @@ -282,25 +282,25 @@ unsigned _BitInt(77) test_bitint_77_add_unsigned(unsigned _BitInt(77) a, unsigne // RISCV32-LABEL: define {{[^@]+}}@test_bitint_77_add_signed // RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] { // RISCV32-NEXT: entry: -// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10]] +// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA12]] // RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i77 -// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]] +// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA12]] // RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i77 // RISCV32-NEXT: [[ADD:%.*]] = add nsw i77 [[B]], [[A]] // RISCV32-NEXT: [[STOREDV4:%.*]] = sext i77 [[ADD]] to i128 -// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]] +// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA12]] // RISCV32-NEXT: ret void // // RISCV32_INT128-LABEL: define {{[^@]+}}@test_bitint_77_add_signed // RISCV32_INT128-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] { // RISCV32_INT128-NEXT: entry: -// RISCV32_INT128-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10]] +// RISCV32_INT128-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA12]] // RISCV32_INT128-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i77 -// RISCV32_INT128-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]] +// RISCV32_INT128-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA12]] // RISCV32_INT128-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i77 // RISCV32_INT128-NEXT: [[ADD:%.*]] = add nsw i77 [[B]], [[A]] // RISCV32_INT128-NEXT: [[STOREDV4:%.*]] = sext i77 [[ADD]] to i128 -// RISCV32_INT128-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]] +// RISCV32_INT128-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA12]] // RISCV32_INT128-NEXT: ret void // signed _BitInt(77) test_bitint_77_add_signed(signed _BitInt(77) a, signed _BitInt(77) b) { @@ -316,27 +316,209 @@ signed _BitInt(77) test_bitint_77_add_signed(signed _BitInt(77) a, signed _BitIn // RISCV32-LABEL: define {{[^@]+}}@test_bitint_77_add_default // RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] { // RISCV32-NEXT: entry: -// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10]] +// RISCV32-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA12]] // RISCV32-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i77 -// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]] +// RISCV32-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA12]] // RISCV32-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i77 // RISCV32-NEXT: [[ADD:%.*]] = add nsw i77 [[B]], [[A]] // RISCV32-NEXT: [[STOREDV4:%.*]] = sext i77 [[ADD]] to i128 -// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]] +// RISCV32-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA12]] // RISCV32-NEXT: ret void // // RISCV32_INT128-LABEL: define {{[^@]+}}@test_bitint_77_add_default // RISCV32_INT128-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i128) align 8 captures(none) initializes((0, 16)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] { // RISCV32_INT128-NEXT: entry: -// RISCV32_INT128-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA10]] +// RISCV32_INT128-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8, !tbaa [[TBAA12]] // RISCV32_INT128-NEXT: [[A:%.*]] = trunc i128 [[TMP2]] to i77 -// RISCV32_INT128-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA10]] +// RISCV32_INT128-NEXT: [[TMP3:%.*]] = load i128, ptr [[TMP1]], align 8, !tbaa [[TBAA12]] // RISCV32_INT128-NEXT: [[B:%.*]] = trunc i128 [[TMP3]] to i77 // RISCV32_INT128-NEXT: [[ADD:%.*]] = add nsw i77 [[B]], [[A]] // RISCV32_INT128-NEXT: [[STOREDV4:%.*]] = sext i77 [[ADD]] to i128 -// RISCV32_INT128-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]] +// RISCV32_INT128-NEXT: store i128 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA12]] // RISCV32_INT128-NEXT: ret void // _BitInt(77) test_bitint_77_add_default(_BitInt(77) a, _BitInt(77) b) { return a + b; } + +// BitInt(200) tests - requires BitInt larger than 128 bits support + +// RISCV64-LABEL: define {{[^@]+}}@test_bitint_200_add_unsigned +// RISCV64-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i256) align 8 captures(none) initializes((0, 32)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] { +// RISCV64-NEXT: entry: +// RISCV64-NEXT: [[TMP2:%.*]] = load i256, ptr [[TMP0]], align 8, !tbaa [[TBAA10:![0-9]+]] +// RISCV64-NEXT: [[A:%.*]] = trunc i256 [[TMP2]] to i200 +// RISCV64-NEXT: [[TMP3:%.*]] = load i256, ptr [[TMP1]], align 8, !tbaa [[TBAA10]] +// RISCV64-NEXT: [[B:%.*]] = trunc i256 [[TMP3]] to i200 +// RISCV64-NEXT: [[ADD:%.*]] = add i200 [[B]], [[A]] +// RISCV64-NEXT: [[STOREDV4:%.*]] = zext i200 [[ADD]] to i256 +// RISCV64-NEXT: store i256 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA10]] +// RISCV64-NEXT: ret void +// +// RISCV32-LABEL: define {{[^@]+}}@test_bitint_200_add_unsigned +// RISCV32-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i256) align 8 captures(none) initializes((0, 32)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] { +// RISCV32-NEXT: entry: +// RISCV32-NEXT: [[TMP2:%.*]] = load i256, ptr [[TMP0]], align 8, !tbaa [[TBAA14:![0-9]+]] +// RISCV32-NEXT: [[A:%.*]] = trunc i256 [[TMP2]] to i200 +// RISCV32-NEXT: [[TMP3:%.*]] = load i256, ptr [[TMP1]], align 8, !tbaa [[TBAA14]] +// RISCV32-NEXT: [[B:%.*]] = trunc i256 [[TMP3]] to i200 +// RISCV32-NEXT: [[ADD:%.*]] = add i200 [[B]], [[A]] +// RISCV32-NEXT: [[STOREDV4:%.*]] = zext i200 [[ADD]] to i256 +// RISCV32-NEXT: store i256 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA14]] +// RISCV32-NEXT: ret void +// +// RISCV32_INT128-LABEL: define {{[^@]+}}@test_bitint_200_add_unsigned +// RISCV32_INT128-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i256) align 8 captures(none) initializes((0, 32)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] { +// RISCV32_INT128-NEXT: entry: +// RISCV32_INT128-NEXT: [[TMP2:%.*]] = load i256, ptr [[TMP0]], align 8, !tbaa [[TBAA14:![0-9]+]] +// RISCV32_INT128-NEXT: [[A:%.*]] = trunc i256 [[TMP2]] to i200 +// RISCV32_INT128-NEXT: [[TMP3:%.*]] = load i256, ptr [[TMP1]], align 8, !tbaa [[TBAA14]] +// RISCV32_INT128-NEXT: [[B:%.*]] = trunc i256 [[TMP3]] to i200 +// RISCV32_INT128-NEXT: [[ADD:%.*]] = add i200 [[B]], [[A]] +// RISCV32_INT128-NEXT: [[STOREDV4:%.*]] = zext i200 [[ADD]] to i256 +// RISCV32_INT128-NEXT: store i256 [[STOREDV4]], ptr [[AGG_RESULT]], align 8, !tbaa [[TBAA14]] +// RISCV32_INT128-NEXT: ret void +// +unsigned _BitInt(200) test_bitint_200_add_unsigned(unsigned _BitInt(200) a, unsigned _BitInt(200) b) { + return a + b; +} + +// RISCV64-LABEL: define {{[^@]+}}@test_bitint_200_add_signed +// RISCV64-SAME: (ptr dead_on_unwind noalias writable writeonly sret(i256) align 8 captures(none) initializes((0, 32)) [[AGG_RESULT:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP0:%.*]], ptr dead_on_return noundef readonly captures(none) [[TMP1:%.*]]) local_unnamed_addr #[[ATTR1]] { +// RISCV64-NEXT: e... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/175515 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
