================
@@ -1,22 +1,28 @@
-; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-compute %s |
FileCheck %s
+; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-compute %s |
FileCheck --check-prefix LOWER %s
+; RUN: opt -S -scalarizer -mtriple=dxil-pc-shadermodel6.3-library < %s |
FileCheck --check-prefix SCALAR %s
%dx.types.fouri32 = type { i32, i32, i32, i32 }
-define <4 x i32> @wave_ballot_simple(i1 noundef %p1) {
+define %dx.types.fouri32 @wave_ballot_simple(i1 noundef %p1) {
entry:
-; CHECK: call %dx.types.fouri32 @dx.op.waveActiveBallot(i32 116, i1 %p1)
+; LOWER: call %dx.types.fouri32 @dx.op.waveActiveBallot(i32 116, i1 %p1)
+; SCALAR: call { i32, i32, i32, i32 } @llvm.dx.wave.ballot.i32(i1 %p1)
+
+ %s = call %dx.types.fouri32 @llvm.dx.wave.ballot(i1 %p1)
+
+; Scalarization may occur
+; CHECK: extractvalue
+; CHECK: insertvalue
+; CHECK: extractvalue
+; CHECK: insertvalue
+; CHECK: extractvalue
+; CHECK: insertvalue
----------------
farzonl wrote:
It looks weird to just check instruction order and not registers
https://github.com/llvm/llvm-project/pull/175105
_______________________________________________
cfe-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
