https://github.com/Priyanshu3820 updated https://github.com/llvm/llvm-project/pull/176653
>From a30b79b98a26bd6feab0c4d08f67258723398a0b Mon Sep 17 00:00:00 2001 From: Priyanshu Kumar <[email protected]> Date: Thu, 8 Jan 2026 18:43:51 +0000 Subject: [PATCH 1/7] Implement handling for msvc specific shift builtins in CIR --- clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp | 22 +- .../CodeGenBuiltins/X86/ms-x86-intrinsics.c | 203 +++++------------- 2 files changed, 75 insertions(+), 150 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp index 6c01cbd7f699f..2e318ef278b88 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp @@ -2268,10 +2268,24 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) { } case X86::BI__shiftleft128: case X86::BI__shiftright128: { - cgm.errorNYI(expr->getSourceRange(), - std::string("unimplemented X86 builtin call: ") + - getContext().BuiltinInfo.getName(builtinID)); - return mlir::Value{}; + // Determine if left or right shift + bool isRight = (builtinID == X86::BI__shiftright128); + + // Flip low/high ops and zero-extend amount to matching type. + // shiftleft128(Low, High, Amt) -> fshl(High, Low, Amt) + // shiftright128(Low, High, Amt) -> fshr(High, Low, Amt) + std::swap(ops[0], ops[1]); + + // Zero-extend shift amount to i64 if needed + auto amtTy = mlir::dyn_cast<cir::IntType>(ops[2].getType()); + auto i64Ty = builder.getUInt64Ty(); + + if (amtTy != i64Ty) { + ops[2] = builder.createIntCast(ops[2], i64Ty); + } + + return emitX86FunnelShift(builder, getLoc(expr->getExprLoc()), ops[0], + ops[1], ops[2], isRight); } case X86::BI_ReadWriteBarrier: case X86::BI_ReadBarrier: diff --git a/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c index 1f80a683aa3cd..28fad3a68e968 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c @@ -1,149 +1,60 @@ -// RUN: %clang_cc1 -ffreestanding -triple x86_64-unknown-linux -fms-extensions -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir -Wall -Werror %s -// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s - -// RUN: %clang_cc1 -ffreestanding -triple x86_64-unknown-linux -fms-extensions -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t-cir.ll -Wall -Werror %s -// RUN: FileCheck --check-prefix=LLVM --input-file=%t-cir.ll %s - -// RUN: %clang_cc1 -ffreestanding -triple x86_64-unknown-linux -fms-extensions -Wno-implicit-function-declaration -emit-llvm -o %t.ll -Wall -Werror %s -// RUN: FileCheck --check-prefix=OGCG --input-file=%t.ll %s - -#pragma intrinsic(__cpuid) -#pragma intrinsic(__cpuidex) - -void test__cpuid_with_cpu_info_as_pointer(int cpuInfo[4], int functionId) { - __cpuid(cpuInfo, functionId); - - // CIR-LABEL: __cpuid_with_cpu_info_as_pointer - // CIR: [[CPU_INFO_PTR:%.*]] = cir.load align(8) - // CIR: [[FUNCTION_ID:%.*]] = cir.load align(4) - // CIR: [[SUB_FUNCTION_ID:%.*]] = cir.const #cir.int<0> : !s32i - // CIR: cir.cpuid [[CPU_INFO_PTR]], [[FUNCTION_ID]], [[SUB_FUNCTION_ID]] : !cir.ptr<!s32i>, !s32i, !s32i - - // LLVM-LABEL: __cpuid_with_cpu_info_as_pointer - // LLVM: [[CPU_INFO_PTR:%.*]] = load ptr - // LLVM: [[FUNCTION_ID:%.*]] = load i32 - // LLVM: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID]], i32 0) - // LLVM: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 - // LLVM: [[ADDR_PTR_0:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 0 - // LLVM: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 - // LLVM: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 - // LLVM: [[ADDR_PTR_1:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 1 - // LLVM: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 - // LLVM: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 - // LLVM: [[ADDR_PTR_2:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 2 - // LLVM: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 - // LLVM: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 - // LLVM: [[ADDR_PTR_3:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 3 - // LLVM: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 - - // OGCG-LABEL: __cpuid_with_cpu_info_as_pointer - // OGCG: [[FUNCTION_ID:%.*]] = load i32 - // OGCG: [[FUNCTION_ID_ARG:%.*]] = load i32 - // OGCG: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID_ARG]], i32 0) - // OGCG: [[CPU_INFO_PTR:%.*]] = load ptr - // OGCG: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 - // OGCG: [[ADDR_PTR_0:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 0 - // OGCG: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 - // OGCG: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 - // OGCG: [[ADDR_PTR_1:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 1 - // OGCG: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 - // OGCG: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 - // OGCG: [[ADDR_PTR_2:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 2 - // OGCG: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 - // OGCG: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 - // OGCG: [[ADDR_PTR_3:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 3 - // OGCG: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 +// RUN: %clang_cc1 -ffreestanding -fms-extensions -triple x86_64-unknown-linux-gnu \ +// RUN: -Oz -fclangir -emit-cir %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR + +// RUN: %clang_cc1 -ffreestanding -fms-extensions -triple x86_64-unknown-linux-gnu \ +// RUN: -Oz -fclangir -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM + +// RUN: %clang_cc1 -ffreestanding -fms-extensions -triple x86_64-unknown-linux-gnu \ +// RUN: -Oz -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=OGCG + +unsigned __int64 __shiftleft128(unsigned __int64 low, unsigned __int64 high, + unsigned char shift); +unsigned __int64 __shiftright128(unsigned __int64 low, unsigned __int64 high, + unsigned char shift); + +unsigned __int64 test_shiftleft128(unsigned __int64 l, unsigned __int64 h, + unsigned char d) { + // CIR-LABEL: cir.func{{.*}}@test_shiftleft128 + // CIR: (%[[L:[^,]+]]: !u64i{{.*}}, %[[H:[^,]+]]: !u64i{{.*}}, %[[D:[^,]+]]: !u8i{{.*}}) + // CIR: %[[D_LOAD:[^ ]+]] = cir.load {{.*}} %{{[^ ]+}} : !cir.ptr<!u8i>, !u8i + // CIR: %[[D_CAST:[^ ]+]] = cir.cast integral %[[D_LOAD]] : !u8i -> !u64i + // CIR: %{{[^ ]+}} = cir.call_llvm_intrinsic "fshl" {{.*}} : (!u64i, !u64i, !u64i) -> !u64i +// CIR: cir.return + +// LLVM-LABEL: define dso_local i64 @test_shiftleft128(i64 %0, i64 %1, i8 %2) +// LLVM-NEXT: [[TMP1:%.*]] = zext i8 %2 to i64 +// LLVM-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.fshl.i64(i64 %1, i64 %0, i64 [[TMP1]]) +// LLVM-NEXT: ret i64 [[TMP2]] + +// OGCG-LABEL: define dso_local noundef i64 @test_shiftleft128(i64 noundef %l, i64 noundef %h, i8 noundef zeroext %d) +// OGCG-NEXT: entry: +// OGCG-NEXT: [[TMP0:%.*]] = zext i8 %d to i64 +// OGCG-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.fshl.i64(i64 %h, i64 %l, i64 [[TMP0]]) +// OGCG-NEXT: ret i64 [[TMP1]] +return __shiftleft128(l, h, d); } -void test__cpuid_with_cpu_info_as_array(int functionId) { - int cpuInfo[4]; - __cpuid(cpuInfo, functionId); - - // CIR-LABEL: _cpuid_with_cpu_info_as_array - // CIR: [[CPU_INFO:%.*]] = cir.cast array_to_ptrdecay - // CIR: [[FUNCTION_ID:%.*]] = cir.load align(4) - // CIR: [[SUB_FUNCTION_ID:%.*]] = cir.const #cir.int<0> : !s32i - // CIR: cir.cpuid [[CPU_INFO_PTR]], [[FUNCTION_ID]], [[SUB_FUNCTION_ID]] : !cir.ptr<!s32i>, !s32i, !s32i - - // LLVM-LABEL: _cpuid_with_cpu_info_as_array - // LLVM: [[CPU_INFO_PTR:%.*]] = getelementptr i32, ptr - // LLVM: [[FUNCTION_ID:%.*]] = load i32 - // LLVM: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID]], i32 0) - // LLVM: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 - // LLVM: [[ADDR_PTR_0:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 0 - // LLVM: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 - // LLVM: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 - // LLVM: [[ADDR_PTR_1:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 1 - // LLVM: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 - // LLVM: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 - // LLVM: [[ADDR_PTR_2:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 2 - // LLVM: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 - // LLVM: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 - // LLVM: [[ADDR_PTR_3:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 3 - // LLVM: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 - - // OGCG-LABEL: _cpuid_with_cpu_info_as_array - // OGCG: [[FUNCTION_ID:%.*]] = load i32 - // OGCG: [[FUNCTION_ID_ARG:%.*]] = load i32 - // OGCG: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID_ARG]], i32 0) - // OGCG: [[CPU_INFO_PTR:%.*]] = getelementptr inbounds [4 x i32], ptr - // OGCG: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 - // OGCG: [[ADDR_PTR_0:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 0 - // OGCG: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 - // OGCG: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 - // OGCG: [[ADDR_PTR_1:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 1 - // OGCG: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 - // OGCG: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 - // OGCG: [[ADDR_PTR_2:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 2 - // OGCG: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 - // OGCG: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 - // OGCG: [[ADDR_PTR_3:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 3 - // OGCG: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 -} -void test__cpuidex(int cpuInfo[4], int functionId, int subFunctionId) { - __cpuidex(cpuInfo, functionId, subFunctionId); - - // CIR-LABEL: __cpuidex - // CIR: [[CPU_INFO_PTR:%.*]] = cir.load align(8) - // CIR: [[FUNCTION_ID:%.*]] = cir.load align(4) - // CIR: [[SUB_FUNCTION_ID:%.*]] = cir.load align(4) - // CIR: cir.cpuid [[CPU_INFO_PTR]], [[FUNCTION_ID]], [[SUB_FUNCTION_ID]] : !cir.ptr<!s32i>, !s32i, !s32i - - // LLVM-LABEL: __cpuidex - // LLVM: [[CPU_INFO_PTR:%.*]] = load ptr - // LLVM: [[FUNCTION_ID:%.*]] = load i32 - // LLVM: [[SUB_FUNCTION_ID:%.*]] = load i32 - // LLVM: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID]], i32 [[SUB_FUNCTION_ID]]) - // LLVM: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 - // LLVM: [[ADDR_PTR_0:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 0 - // LLVM: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 - // LLVM: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 - // LLVM: [[ADDR_PTR_1:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 1 - // LLVM: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 - // LLVM: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 - // LLVM: [[ADDR_PTR_2:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 2 - // LLVM: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 - // LLVM: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 - // LLVM: [[ADDR_PTR_3:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 3 - // LLVM: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 - - // OGCG-LABEL: __cpuidex - // OGCG: [[FUNCTION_ID:%.*]] = load i32 - // OGCG: [[SUB_FUNCTION_ID:%.*]] = load i32 - // OGCG: [[FUNCTION_ID_ARG:%.*]] = load i32 - // OGCG: [[SUB_FUNCTION_ID_ARG:%.*]] = load i32 - // OGCG: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID_ARG]], i32 [[SUB_FUNCTION_ID_ARG]]) - // OGCG: [[CPU_INFO_PTR:%.*]] = load ptr - // OGCG: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 - // OGCG: [[ADDR_PTR_0:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 0 - // OGCG: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 - // OGCG: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 - // OGCG: [[ADDR_PTR_1:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 1 - // OGCG: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 - // OGCG: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 - // OGCG: [[ADDR_PTR_2:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 2 - // OGCG: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 - // OGCG: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 - // OGCG: [[ADDR_PTR_3:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 3 - // OGCG: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 +unsigned __int64 test_shiftright128(unsigned __int64 l, unsigned __int64 h, + unsigned char d) { + // CIR-LABEL: cir.func{{.*}}@test_shiftright128 + // CIR: (%[[L:[^,]+]]: !u64i{{.*}}, %[[H:[^,]+]]: !u64i{{.*}}, %[[D:[^,]+]]: !u8i{{.*}}) +// CIR: %[[D_LOAD:[^ ]+]] = cir.load {{.*}} %{{[^ ]+}} : !cir.ptr<!u8i>, !u8i +// CIR: %[[D_CAST:[^ ]+]] = cir.cast integral %[[D_LOAD]] : !u8i -> !u64i +// CIR: %{{[^ ]+}} = cir.call_llvm_intrinsic "fshr" {{.*}} : (!u64i, !u64i, !u64i) -> !u64i +// CIR: cir.return + +// LLVM-LABEL: define dso_local i64 @test_shiftright128(i64 %0, i64 %1, i8 %2) +// LLVM-NEXT: [[TMP1:%.*]] = zext i8 %2 to i64 +// LLVM-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.fshr.i64(i64 %1, i64 %0, i64 [[TMP1]]) +// LLVM-NEXT: ret i64 [[TMP2]] + +// OGCG-LABEL: define dso_local noundef i64 @test_shiftright128(i64 noundef %l, i64 noundef %h, i8 noundef zeroext %d) +// OGCG-NEXT: entry: +// OGCG-NEXT: [[TMP0:%.*]] = zext i8 %d to i64 +// OGCG-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.fshr.i64(i64 %h, i64 %l, i64 [[TMP0]]) +// OGCG-NEXT: ret i64 [[TMP1]] +return __shiftright128(l, h, d); } >From eeb9b2e754aae82b3b1bf54d689efa19e5e675b6 Mon Sep 17 00:00:00 2001 From: Priyanshu Kumar <[email protected]> Date: Thu, 8 Jan 2026 19:02:15 +0000 Subject: [PATCH 2/7] Fix formatting and match existing function pattern --- clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp | 2 +- .../CodeGenBuiltins/X86/ms-x86-intrinsics.c | 26 +++++++++---------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp index 2e318ef278b88..473cf4538fbd3 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp @@ -2277,7 +2277,7 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) { std::swap(ops[0], ops[1]); // Zero-extend shift amount to i64 if needed - auto amtTy = mlir::dyn_cast<cir::IntType>(ops[2].getType()); + auto amtTy = mlir::cast<cir::IntType>(ops[2].getType()); auto i64Ty = builder.getUInt64Ty(); if (amtTy != i64Ty) { diff --git a/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c index 28fad3a68e968..5265537e5be7c 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c @@ -15,13 +15,11 @@ unsigned __int64 __shiftleft128(unsigned __int64 low, unsigned __int64 high, unsigned __int64 __shiftright128(unsigned __int64 low, unsigned __int64 high, unsigned char shift); -unsigned __int64 test_shiftleft128(unsigned __int64 l, unsigned __int64 h, - unsigned char d) { - // CIR-LABEL: cir.func{{.*}}@test_shiftleft128 - // CIR: (%[[L:[^,]+]]: !u64i{{.*}}, %[[H:[^,]+]]: !u64i{{.*}}, %[[D:[^,]+]]: !u8i{{.*}}) - // CIR: %[[D_LOAD:[^ ]+]] = cir.load {{.*}} %{{[^ ]+}} : !cir.ptr<!u8i>, !u8i - // CIR: %[[D_CAST:[^ ]+]] = cir.cast integral %[[D_LOAD]] : !u8i -> !u64i - // CIR: %{{[^ ]+}} = cir.call_llvm_intrinsic "fshl" {{.*}} : (!u64i, !u64i, !u64i) -> !u64i +// CIR-LABEL: cir.func{{.*}}@test_shiftleft128 +// CIR: (%[[L:[^,]+]]: !u64i{{.*}}, %[[H:[^,]+]]: !u64i{{.*}}, %[[D:[^,]+]]: !u8i{{.*}}) +// CIR: %[[D_LOAD:[^ ]+]] = cir.load {{.*}} %{{[^ ]+}} : !cir.ptr<!u8i>, !u8i +// CIR: %[[D_CAST:[^ ]+]] = cir.cast integral %[[D_LOAD]] : !u8i -> !u64i +// CIR: %{{[^ ]+}} = cir.call_llvm_intrinsic "fshl" {{.*}} : (!u64i, !u64i, !u64i) -> !u64i // CIR: cir.return // LLVM-LABEL: define dso_local i64 @test_shiftleft128(i64 %0, i64 %1, i8 %2) @@ -34,13 +32,13 @@ unsigned __int64 test_shiftleft128(unsigned __int64 l, unsigned __int64 h, // OGCG-NEXT: [[TMP0:%.*]] = zext i8 %d to i64 // OGCG-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.fshl.i64(i64 %h, i64 %l, i64 [[TMP0]]) // OGCG-NEXT: ret i64 [[TMP1]] -return __shiftleft128(l, h, d); +unsigned __int64 test_shiftleft128(unsigned __int64 l, unsigned __int64 h, + unsigned char d) { + return __shiftleft128(l, h, d); } -unsigned __int64 test_shiftright128(unsigned __int64 l, unsigned __int64 h, - unsigned char d) { - // CIR-LABEL: cir.func{{.*}}@test_shiftright128 - // CIR: (%[[L:[^,]+]]: !u64i{{.*}}, %[[H:[^,]+]]: !u64i{{.*}}, %[[D:[^,]+]]: !u8i{{.*}}) +// CIR-LABEL: cir.func{{.*}}@test_shiftright128 +// CIR: (%[[L:[^,]+]]: !u64i{{.*}}, %[[H:[^,]+]]: !u64i{{.*}}, %[[D:[^,]+]]: !u8i{{.*}}) // CIR: %[[D_LOAD:[^ ]+]] = cir.load {{.*}} %{{[^ ]+}} : !cir.ptr<!u8i>, !u8i // CIR: %[[D_CAST:[^ ]+]] = cir.cast integral %[[D_LOAD]] : !u8i -> !u64i // CIR: %{{[^ ]+}} = cir.call_llvm_intrinsic "fshr" {{.*}} : (!u64i, !u64i, !u64i) -> !u64i @@ -56,5 +54,7 @@ unsigned __int64 test_shiftright128(unsigned __int64 l, unsigned __int64 h, // OGCG-NEXT: [[TMP0:%.*]] = zext i8 %d to i64 // OGCG-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.fshr.i64(i64 %h, i64 %l, i64 [[TMP0]]) // OGCG-NEXT: ret i64 [[TMP1]] -return __shiftright128(l, h, d); +unsigned __int64 test_shiftright128(unsigned __int64 l, unsigned __int64 h, + unsigned char d) { + return __shiftright128(l, h, d); } >From 7e5cce03bcc1ac936fe6dab1234b693a4dc242da Mon Sep 17 00:00:00 2001 From: Priyanshu Kumar <[email protected]> Date: Fri, 9 Jan 2026 06:15:43 +0000 Subject: [PATCH 3/7] Update CIRGenBuiltinX86.cpp and test --- clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp | 15 +++++------ .../CodeGenBuiltins/X86/ms-x86-intrinsics.c | 26 +++++++++---------- 2 files changed, 19 insertions(+), 22 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp index 473cf4538fbd3..a4af08a222566 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp @@ -2268,9 +2268,6 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) { } case X86::BI__shiftleft128: case X86::BI__shiftright128: { - // Determine if left or right shift - bool isRight = (builtinID == X86::BI__shiftright128); - // Flip low/high ops and zero-extend amount to matching type. // shiftleft128(Low, High, Amt) -> fshl(High, Low, Amt) // shiftright128(Low, High, Amt) -> fshr(High, Low, Amt) @@ -2278,14 +2275,16 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) { // Zero-extend shift amount to i64 if needed auto amtTy = mlir::cast<cir::IntType>(ops[2].getType()); - auto i64Ty = builder.getUInt64Ty(); + cir::IntType i64Ty = builder.getUInt64Ty(); - if (amtTy != i64Ty) { + if (amtTy != i64Ty) ops[2] = builder.createIntCast(ops[2], i64Ty); - } - return emitX86FunnelShift(builder, getLoc(expr->getExprLoc()), ops[0], - ops[1], ops[2], isRight); + const StringRef intrinsicName = + (builtinID == X86::BI__shiftleft128) ? "fshl" : "fshr"; + return emitIntrinsicCallOp(builder, getLoc(expr->getExprLoc()), + intrinsicName, i64Ty, + mlir::ValueRange{ops[0], ops[1], ops[2]}); } case X86::BI_ReadWriteBarrier: case X86::BI_ReadBarrier: diff --git a/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c index 5265537e5be7c..67d7159c4dfe1 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c @@ -16,18 +16,17 @@ unsigned __int64 __shiftright128(unsigned __int64 low, unsigned __int64 high, unsigned char shift); // CIR-LABEL: cir.func{{.*}}@test_shiftleft128 -// CIR: (%[[L:[^,]+]]: !u64i{{.*}}, %[[H:[^,]+]]: !u64i{{.*}}, %[[D:[^,]+]]: !u8i{{.*}}) -// CIR: %[[D_LOAD:[^ ]+]] = cir.load {{.*}} %{{[^ ]+}} : !cir.ptr<!u8i>, !u8i +// CIR: %[[D_LOAD:[^ ]+]] = cir.load {{.*}} : !cir.ptr<!u8i>, !u8i // CIR: %[[D_CAST:[^ ]+]] = cir.cast integral %[[D_LOAD]] : !u8i -> !u64i // CIR: %{{[^ ]+}} = cir.call_llvm_intrinsic "fshl" {{.*}} : (!u64i, !u64i, !u64i) -> !u64i // CIR: cir.return -// LLVM-LABEL: define dso_local i64 @test_shiftleft128(i64 %0, i64 %1, i8 %2) -// LLVM-NEXT: [[TMP1:%.*]] = zext i8 %2 to i64 -// LLVM-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.fshl.i64(i64 %1, i64 %0, i64 [[TMP1]]) -// LLVM-NEXT: ret i64 [[TMP2]] +// LLVM-LABEL: define {{.*}} i64 @test_shiftleft128 +// LLVM-SAME: (i64 %[[ARG0:.*]], i64 %[[ARG1:.*]], i8 %[[ARG2:.*]]) +// LLVM-NEXT: [[TMP1:%.*]] = zext i8 %[[ARG2]] to i64 +// LLVM-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.fshl.i64(i64 %[[ARG1]], i64 %[[ARG0]], i64 [[TMP1]]) -// OGCG-LABEL: define dso_local noundef i64 @test_shiftleft128(i64 noundef %l, i64 noundef %h, i8 noundef zeroext %d) +// OGCG-LABEL: define {{.*}} i64 @test_shiftleft128(i64 noundef %l, i64 noundef %h, i8 noundef zeroext %d) // OGCG-NEXT: entry: // OGCG-NEXT: [[TMP0:%.*]] = zext i8 %d to i64 // OGCG-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.fshl.i64(i64 %h, i64 %l, i64 [[TMP0]]) @@ -38,18 +37,17 @@ unsigned __int64 test_shiftleft128(unsigned __int64 l, unsigned __int64 h, } // CIR-LABEL: cir.func{{.*}}@test_shiftright128 -// CIR: (%[[L:[^,]+]]: !u64i{{.*}}, %[[H:[^,]+]]: !u64i{{.*}}, %[[D:[^,]+]]: !u8i{{.*}}) -// CIR: %[[D_LOAD:[^ ]+]] = cir.load {{.*}} %{{[^ ]+}} : !cir.ptr<!u8i>, !u8i +// CIR: %[[D_LOAD:[^ ]+]] = cir.load {{.*}} : !cir.ptr<!u8i>, !u8i // CIR: %[[D_CAST:[^ ]+]] = cir.cast integral %[[D_LOAD]] : !u8i -> !u64i // CIR: %{{[^ ]+}} = cir.call_llvm_intrinsic "fshr" {{.*}} : (!u64i, !u64i, !u64i) -> !u64i // CIR: cir.return -// LLVM-LABEL: define dso_local i64 @test_shiftright128(i64 %0, i64 %1, i8 %2) -// LLVM-NEXT: [[TMP1:%.*]] = zext i8 %2 to i64 -// LLVM-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.fshr.i64(i64 %1, i64 %0, i64 [[TMP1]]) -// LLVM-NEXT: ret i64 [[TMP2]] +// LLVM-LABEL: define {{.*}} i64 @test_shiftright128 +// LLVM-SAME: (i64 %[[ARG0:.*]], i64 %[[ARG1:.*]], i8 %[[ARG2:.*]]) +// LLVM-NEXT: [[TMP1:%.*]] = zext i8 %[[ARG2]] to i64 +// LLVM-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.fshr.i64(i64 %[[ARG1]], i64 %[[ARG0]], i64 [[TMP1]]) -// OGCG-LABEL: define dso_local noundef i64 @test_shiftright128(i64 noundef %l, i64 noundef %h, i8 noundef zeroext %d) +// OGCG-LABEL: define {{.*}} i64 @test_shiftright128(i64 noundef %l, i64 noundef %h, i8 noundef zeroext %d) // OGCG-NEXT: entry: // OGCG-NEXT: [[TMP0:%.*]] = zext i8 %d to i64 // OGCG-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.fshr.i64(i64 %h, i64 %l, i64 [[TMP0]]) >From 29c42055e22276f1415ba31d6c57369c7e639ac7 Mon Sep 17 00:00:00 2001 From: Priyanshu Kumar <[email protected]> Date: Fri, 9 Jan 2026 12:42:13 +0000 Subject: [PATCH 4/7] Update test --- .../CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c index 67d7159c4dfe1..3d8da41ad07dc 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c @@ -26,10 +26,11 @@ unsigned __int64 __shiftright128(unsigned __int64 low, unsigned __int64 high, // LLVM-NEXT: [[TMP1:%.*]] = zext i8 %[[ARG2]] to i64 // LLVM-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.fshl.i64(i64 %[[ARG1]], i64 %[[ARG0]], i64 [[TMP1]]) -// OGCG-LABEL: define {{.*}} i64 @test_shiftleft128(i64 noundef %l, i64 noundef %h, i8 noundef zeroext %d) +// OGCG-LABEL: define {{.*}} i64 @test_shiftleft128 +// OGCG-SAME: (i64 {{.*}} %[[ARG0:.*]], i64 {{.*}} %[[ARG1:.*]], i8 {{.*}} %[[ARG2:.*]]) // OGCG-NEXT: entry: -// OGCG-NEXT: [[TMP0:%.*]] = zext i8 %d to i64 -// OGCG-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.fshl.i64(i64 %h, i64 %l, i64 [[TMP0]]) +// OGCG-NEXT: [[TMP0:%.*]] = zext i8 %[[ARG2]] to i64 +// OGCG-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.fshl.i64(i64 %[[ARG1]], i64 %[[ARG0]], i64 [[TMP0]]) // OGCG-NEXT: ret i64 [[TMP1]] unsigned __int64 test_shiftleft128(unsigned __int64 l, unsigned __int64 h, unsigned char d) { @@ -47,10 +48,11 @@ unsigned __int64 test_shiftleft128(unsigned __int64 l, unsigned __int64 h, // LLVM-NEXT: [[TMP1:%.*]] = zext i8 %[[ARG2]] to i64 // LLVM-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.fshr.i64(i64 %[[ARG1]], i64 %[[ARG0]], i64 [[TMP1]]) -// OGCG-LABEL: define {{.*}} i64 @test_shiftright128(i64 noundef %l, i64 noundef %h, i8 noundef zeroext %d) +// OGCG-LABEL: define {{.*}} i64 @test_shiftright128 +// OGCG-SAME: (i64 {{.*}} %[[ARG0:.*]], i64 {{.*}} %[[ARG1:.*]], i8 {{.*}} %[[ARG2:.*]]) // OGCG-NEXT: entry: -// OGCG-NEXT: [[TMP0:%.*]] = zext i8 %d to i64 -// OGCG-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.fshr.i64(i64 %h, i64 %l, i64 [[TMP0]]) +// OGCG-NEXT: [[TMP0:%.*]] = zext i8 %[[ARG2]] to i64 +// OGCG-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.fshr.i64(i64 %[[ARG1]], i64 %[[ARG0]], i64 [[TMP0]]) // OGCG-NEXT: ret i64 [[TMP1]] unsigned __int64 test_shiftright128(unsigned __int64 l, unsigned __int64 h, unsigned char d) { >From fb39eb2c2c43e9cb75a53ec3017e9a8a41613bbe Mon Sep 17 00:00:00 2001 From: Roberto Turrado Camblor <[email protected]> Date: Sat, 10 Jan 2026 00:37:44 +0100 Subject: [PATCH 5/7] [CIR][X86] Add support for `cpuid`/`cpuidex` (#173197) Adds support for the `__builtin_ia32_cpuid` and `__builtin_ia32_cpuidex` X86 builtins. Part of [167765](https://github.com/llvm/llvm-project/issues/167765). --- .../CodeGenBuiltins/X86/ms-x86-intrinsics.c | 142 ++++++++++++++++++ 1 file changed, 142 insertions(+) diff --git a/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c index 3d8da41ad07dc..cdecb24cc7b6f 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c @@ -58,3 +58,145 @@ unsigned __int64 test_shiftright128(unsigned __int64 l, unsigned __int64 h, unsigned char d) { return __shiftright128(l, h, d); } + +#pragma intrinsic(__cpuid) +#pragma intrinsic(__cpuidex) + +void test__cpuid_with_cpu_info_as_pointer(int cpuInfo[4], int functionId) { + __cpuid(cpuInfo, functionId); + + // CIR-LABEL: __cpuid_with_cpu_info_as_pointer + // CIR: [[CPU_INFO_PTR:%.*]] = cir.load align(8) + // CIR: [[FUNCTION_ID:%.*]] = cir.load align(4) + // CIR: [[SUB_FUNCTION_ID:%.*]] = cir.const #cir.int<0> : !s32i + // CIR: cir.cpuid [[CPU_INFO_PTR]], [[FUNCTION_ID]], [[SUB_FUNCTION_ID]] : !cir.ptr<!s32i>, !s32i, !s32i + + // LLVM-LABEL: __cpuid_with_cpu_info_as_pointer + // LLVM: [[CPU_INFO_PTR:%.*]] = load ptr + // LLVM: [[FUNCTION_ID:%.*]] = load i32 + // LLVM: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID]], i32 0) + // LLVM: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 + // LLVM: [[ADDR_PTR_0:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 0 + // LLVM: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 + // LLVM: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 + // LLVM: [[ADDR_PTR_1:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 1 + // LLVM: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 + // LLVM: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 + // LLVM: [[ADDR_PTR_2:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 2 + // LLVM: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 + // LLVM: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 + // LLVM: [[ADDR_PTR_3:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 3 + // LLVM: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 + + // OGCG-LABEL: __cpuid_with_cpu_info_as_pointer + // OGCG: [[FUNCTION_ID:%.*]] = load i32 + // OGCG: [[FUNCTION_ID_ARG:%.*]] = load i32 + // OGCG: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID_ARG]], i32 0) + // OGCG: [[CPU_INFO_PTR:%.*]] = load ptr + // OGCG: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 + // OGCG: [[ADDR_PTR_0:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 0 + // OGCG: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 + // OGCG: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 + // OGCG: [[ADDR_PTR_1:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 1 + // OGCG: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 + // OGCG: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 + // OGCG: [[ADDR_PTR_2:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 2 + // OGCG: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 + // OGCG: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 + // OGCG: [[ADDR_PTR_3:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 3 + // OGCG: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 +} + +void test__cpuid_with_cpu_info_as_array(int functionId) { + int cpuInfo[4]; + __cpuid(cpuInfo, functionId); + + // CIR-LABEL: _cpuid_with_cpu_info_as_array + // CIR: [[CPU_INFO:%.*]] = cir.cast array_to_ptrdecay + // CIR: [[FUNCTION_ID:%.*]] = cir.load align(4) + // CIR: [[SUB_FUNCTION_ID:%.*]] = cir.const #cir.int<0> : !s32i + // CIR: cir.cpuid [[CPU_INFO_PTR]], [[FUNCTION_ID]], [[SUB_FUNCTION_ID]] : !cir.ptr<!s32i>, !s32i, !s32i + + // LLVM-LABEL: _cpuid_with_cpu_info_as_array + // LLVM: [[CPU_INFO_PTR:%.*]] = getelementptr i32, ptr + // LLVM: [[FUNCTION_ID:%.*]] = load i32 + // LLVM: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID]], i32 0) + // LLVM: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 + // LLVM: [[ADDR_PTR_0:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 0 + // LLVM: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 + // LLVM: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 + // LLVM: [[ADDR_PTR_1:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 1 + // LLVM: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 + // LLVM: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 + // LLVM: [[ADDR_PTR_2:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 2 + // LLVM: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 + // LLVM: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 + // LLVM: [[ADDR_PTR_3:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 3 + // LLVM: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 + + // OGCG-LABEL: _cpuid_with_cpu_info_as_array + // OGCG: [[FUNCTION_ID:%.*]] = load i32 + // OGCG: [[FUNCTION_ID_ARG:%.*]] = load i32 + // OGCG: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID_ARG]], i32 0) + // OGCG: [[CPU_INFO_PTR:%.*]] = getelementptr inbounds [4 x i32], ptr + // OGCG: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 + // OGCG: [[ADDR_PTR_0:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 0 + // OGCG: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 + // OGCG: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 + // OGCG: [[ADDR_PTR_1:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 1 + // OGCG: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 + // OGCG: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 + // OGCG: [[ADDR_PTR_2:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 2 + // OGCG: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 + // OGCG: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 + // OGCG: [[ADDR_PTR_3:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 3 + // OGCG: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 +} +void test__cpuidex(int cpuInfo[4], int functionId, int subFunctionId) { + __cpuidex(cpuInfo, functionId, subFunctionId); + + // CIR-LABEL: __cpuidex + // CIR: [[CPU_INFO_PTR:%.*]] = cir.load align(8) + // CIR: [[FUNCTION_ID:%.*]] = cir.load align(4) + // CIR: [[SUB_FUNCTION_ID:%.*]] = cir.load align(4) + // CIR: cir.cpuid [[CPU_INFO_PTR]], [[FUNCTION_ID]], [[SUB_FUNCTION_ID]] : !cir.ptr<!s32i>, !s32i, !s32i + + // LLVM-LABEL: __cpuidex + // LLVM: [[CPU_INFO_PTR:%.*]] = load ptr + // LLVM: [[FUNCTION_ID:%.*]] = load i32 + // LLVM: [[SUB_FUNCTION_ID:%.*]] = load i32 + // LLVM: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID]], i32 [[SUB_FUNCTION_ID]]) + // LLVM: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 + // LLVM: [[ADDR_PTR_0:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 0 + // LLVM: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 + // LLVM: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 + // LLVM: [[ADDR_PTR_1:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 1 + // LLVM: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 + // LLVM: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 + // LLVM: [[ADDR_PTR_2:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 2 + // LLVM: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 + // LLVM: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 + // LLVM: [[ADDR_PTR_3:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 3 + // LLVM: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 + + // OGCG-LABEL: __cpuidex + // OGCG: [[FUNCTION_ID:%.*]] = load i32 + // OGCG: [[SUB_FUNCTION_ID:%.*]] = load i32 + // OGCG: [[FUNCTION_ID_ARG:%.*]] = load i32 + // OGCG: [[SUB_FUNCTION_ID_ARG:%.*]] = load i32 + // OGCG: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID_ARG]], i32 [[SUB_FUNCTION_ID_ARG]]) + // OGCG: [[CPU_INFO_PTR:%.*]] = load ptr + // OGCG: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 + // OGCG: [[ADDR_PTR_0:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 0 + // OGCG: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 + // OGCG: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 + // OGCG: [[ADDR_PTR_1:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 1 + // OGCG: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 + // OGCG: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 + // OGCG: [[ADDR_PTR_2:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 2 + // OGCG: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 + // OGCG: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 + // OGCG: [[ADDR_PTR_3:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 3 + // OGCG: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 +>>>>>>> 8b09e47e6fc8 ([CIR][X86] Add support for `cpuid`/`cpuidex` (#173197)) +} >From 4accbe59db8afa5cca9336616eb35d1f6aa1b108 Mon Sep 17 00:00:00 2001 From: Priyanshu Kumar <[email protected]> Date: Sun, 18 Jan 2026 15:31:38 +0000 Subject: [PATCH 6/7] Implement __shiftleft128 and __shiftright128 MSVC builtins in CIR --- .../CodeGenBuiltins/X86/ms-x86-intrinsics.c | 170 ++++++++++++++++-- 1 file changed, 154 insertions(+), 16 deletions(-) diff --git a/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c index cdecb24cc7b6f..099df36df2570 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c @@ -1,14 +1,11 @@ -// RUN: %clang_cc1 -ffreestanding -fms-extensions -triple x86_64-unknown-linux-gnu \ -// RUN: -Oz -fclangir -emit-cir %s -o %t.cir -// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR +// RUN: %clang_cc1 -ffreestanding -triple x86_64-unknown-linux -fms-extensions -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir -Wall -Werror %s +// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s -// RUN: %clang_cc1 -ffreestanding -fms-extensions -triple x86_64-unknown-linux-gnu \ -// RUN: -Oz -fclangir -emit-llvm %s -o %t.ll -// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM +// RUN: %clang_cc1 -ffreestanding -triple x86_64-unknown-linux -fms-extensions -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t-cir.ll -Wall -Werror %s +// RUN: FileCheck --check-prefix=LLVM --input-file=%t-cir.ll %s -// RUN: %clang_cc1 -ffreestanding -fms-extensions -triple x86_64-unknown-linux-gnu \ -// RUN: -Oz -emit-llvm %s -o %t.ll -// RUN: FileCheck --input-file=%t.ll %s -check-prefix=OGCG +// RUN: %clang_cc1 -ffreestanding -triple x86_64-unknown-linux -fms-extensions -Wno-implicit-function-declaration -emit-llvm -o %t.ll -Wall -Werror %s +// RUN: FileCheck --check-prefix=OGCG --input-file=%t.ll %s unsigned __int64 __shiftleft128(unsigned __int64 low, unsigned __int64 high, unsigned char shift); @@ -22,9 +19,10 @@ unsigned __int64 __shiftright128(unsigned __int64 low, unsigned __int64 high, // CIR: cir.return // LLVM-LABEL: define {{.*}} i64 @test_shiftleft128 -// LLVM-SAME: (i64 %[[ARG0:.*]], i64 %[[ARG1:.*]], i8 %[[ARG2:.*]]) -// LLVM-NEXT: [[TMP1:%.*]] = zext i8 %[[ARG2]] to i64 -// LLVM-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.fshl.i64(i64 %[[ARG1]], i64 %[[ARG0]], i64 [[TMP1]]) +// LLVM-SAME: (i64 %{{.*}}, i64 %{{.*}}, i8 %{{.*}}) +// LLVM: [[TMP1:%.*]] = zext i8 %{{.*}} to i64 +// LLVM-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.fshl.i64(i64 %{{.*}}, i64 %{{.*}}, i64 [[TMP1]]) +// LLVM: ret i64 [[TMP2]] // OGCG-LABEL: define {{.*}} i64 @test_shiftleft128 // OGCG-SAME: (i64 {{.*}} %[[ARG0:.*]], i64 {{.*}} %[[ARG1:.*]], i8 {{.*}} %[[ARG2:.*]]) @@ -44,9 +42,10 @@ unsigned __int64 test_shiftleft128(unsigned __int64 l, unsigned __int64 h, // CIR: cir.return // LLVM-LABEL: define {{.*}} i64 @test_shiftright128 -// LLVM-SAME: (i64 %[[ARG0:.*]], i64 %[[ARG1:.*]], i8 %[[ARG2:.*]]) -// LLVM-NEXT: [[TMP1:%.*]] = zext i8 %[[ARG2]] to i64 -// LLVM-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.fshr.i64(i64 %[[ARG1]], i64 %[[ARG0]], i64 [[TMP1]]) +// LLVM-SAME: (i64 %{{.*}}, i64 %{{.*}}, i8 %{{.*}}) +// LLVM: [[TMP1:%.*]] = zext i8 %{{.*}} to i64 +// LLVM-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.fshr.i64(i64 %{{.*}}, i64 %{{.*}}, i64 [[TMP1]]) +// LLVM: ret i64 [[TMP2]] // OGCG-LABEL: define {{.*}} i64 @test_shiftright128 // OGCG-SAME: (i64 {{.*}} %[[ARG0:.*]], i64 {{.*}} %[[ARG1:.*]], i8 {{.*}} %[[ARG2:.*]]) @@ -198,5 +197,144 @@ void test__cpuidex(int cpuInfo[4], int functionId, int subFunctionId) { // OGCG: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 // OGCG: [[ADDR_PTR_3:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 3 // OGCG: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 ->>>>>>> 8b09e47e6fc8 ([CIR][X86] Add support for `cpuid`/`cpuidex` (#173197)) +} +#pragma intrinsic(__cpuid) +#pragma intrinsic(__cpuidex) + +void test__cpuid_with_cpu_info_as_pointer(int cpuInfo[4], int functionId) { + __cpuid(cpuInfo, functionId); + + // CIR-LABEL: __cpuid_with_cpu_info_as_pointer + // CIR: [[CPU_INFO_PTR:%.*]] = cir.load align(8) + // CIR: [[FUNCTION_ID:%.*]] = cir.load align(4) + // CIR: [[SUB_FUNCTION_ID:%.*]] = cir.const #cir.int<0> : !s32i + // CIR: cir.cpuid [[CPU_INFO_PTR]], [[FUNCTION_ID]], [[SUB_FUNCTION_ID]] : !cir.ptr<!s32i>, !s32i, !s32i + + // LLVM-LABEL: __cpuid_with_cpu_info_as_pointer + // LLVM: [[CPU_INFO_PTR:%.*]] = load ptr + // LLVM: [[FUNCTION_ID:%.*]] = load i32 + // LLVM: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID]], i32 0) + // LLVM: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 + // LLVM: [[ADDR_PTR_0:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 0 + // LLVM: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 + // LLVM: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 + // LLVM: [[ADDR_PTR_1:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 1 + // LLVM: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 + // LLVM: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 + // LLVM: [[ADDR_PTR_2:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 2 + // LLVM: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 + // LLVM: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 + // LLVM: [[ADDR_PTR_3:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 3 + // LLVM: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 + + // OGCG-LABEL: __cpuid_with_cpu_info_as_pointer + // OGCG: [[FUNCTION_ID:%.*]] = load i32 + // OGCG: [[FUNCTION_ID_ARG:%.*]] = load i32 + // OGCG: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID_ARG]], i32 0) + // OGCG: [[CPU_INFO_PTR:%.*]] = load ptr + // OGCG: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 + // OGCG: [[ADDR_PTR_0:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 0 + // OGCG: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 + // OGCG: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 + // OGCG: [[ADDR_PTR_1:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 1 + // OGCG: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 + // OGCG: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 + // OGCG: [[ADDR_PTR_2:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 2 + // OGCG: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 + // OGCG: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 + // OGCG: [[ADDR_PTR_3:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 3 + // OGCG: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 +} + +void test__cpuid_with_cpu_info_as_array(int functionId) { + int cpuInfo[4]; + __cpuid(cpuInfo, functionId); + + // CIR-LABEL: _cpuid_with_cpu_info_as_array + // CIR: [[CPU_INFO:%.*]] = cir.cast array_to_ptrdecay + // CIR: [[FUNCTION_ID:%.*]] = cir.load align(4) + // CIR: [[SUB_FUNCTION_ID:%.*]] = cir.const #cir.int<0> : !s32i + // CIR: cir.cpuid [[CPU_INFO_PTR]], [[FUNCTION_ID]], [[SUB_FUNCTION_ID]] : !cir.ptr<!s32i>, !s32i, !s32i + + // LLVM-LABEL: _cpuid_with_cpu_info_as_array + // LLVM: [[CPU_INFO_PTR:%.*]] = getelementptr i32, ptr + // LLVM: [[FUNCTION_ID:%.*]] = load i32 + // LLVM: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID]], i32 0) + // LLVM: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 + // LLVM: [[ADDR_PTR_0:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 0 + // LLVM: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 + // LLVM: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 + // LLVM: [[ADDR_PTR_1:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 1 + // LLVM: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 + // LLVM: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 + // LLVM: [[ADDR_PTR_2:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 2 + // LLVM: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 + // LLVM: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 + // LLVM: [[ADDR_PTR_3:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 3 + // LLVM: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 + + // OGCG-LABEL: _cpuid_with_cpu_info_as_array + // OGCG: [[FUNCTION_ID:%.*]] = load i32 + // OGCG: [[FUNCTION_ID_ARG:%.*]] = load i32 + // OGCG: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID_ARG]], i32 0) + // OGCG: [[CPU_INFO_PTR:%.*]] = getelementptr inbounds [4 x i32], ptr + // OGCG: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 + // OGCG: [[ADDR_PTR_0:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 0 + // OGCG: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 + // OGCG: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 + // OGCG: [[ADDR_PTR_1:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 1 + // OGCG: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 + // OGCG: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 + // OGCG: [[ADDR_PTR_2:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 2 + // OGCG: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 + // OGCG: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 + // OGCG: [[ADDR_PTR_3:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 3 + // OGCG: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 +} +void test__cpuidex(int cpuInfo[4], int functionId, int subFunctionId) { + __cpuidex(cpuInfo, functionId, subFunctionId); + + // CIR-LABEL: __cpuidex + // CIR: [[CPU_INFO_PTR:%.*]] = cir.load align(8) + // CIR: [[FUNCTION_ID:%.*]] = cir.load align(4) + // CIR: [[SUB_FUNCTION_ID:%.*]] = cir.load align(4) + // CIR: cir.cpuid [[CPU_INFO_PTR]], [[FUNCTION_ID]], [[SUB_FUNCTION_ID]] : !cir.ptr<!s32i>, !s32i, !s32i + + // LLVM-LABEL: __cpuidex + // LLVM: [[CPU_INFO_PTR:%.*]] = load ptr + // LLVM: [[FUNCTION_ID:%.*]] = load i32 + // LLVM: [[SUB_FUNCTION_ID:%.*]] = load i32 + // LLVM: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID]], i32 [[SUB_FUNCTION_ID]]) + // LLVM: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 + // LLVM: [[ADDR_PTR_0:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 0 + // LLVM: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 + // LLVM: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 + // LLVM: [[ADDR_PTR_1:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 1 + // LLVM: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 + // LLVM: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 + // LLVM: [[ADDR_PTR_2:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 2 + // LLVM: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 + // LLVM: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 + // LLVM: [[ADDR_PTR_3:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 3 + // LLVM: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 + + // OGCG-LABEL: __cpuidex + // OGCG: [[FUNCTION_ID:%.*]] = load i32 + // OGCG: [[SUB_FUNCTION_ID:%.*]] = load i32 + // OGCG: [[FUNCTION_ID_ARG:%.*]] = load i32 + // OGCG: [[SUB_FUNCTION_ID_ARG:%.*]] = load i32 + // OGCG: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID_ARG]], i32 [[SUB_FUNCTION_ID_ARG]]) + // OGCG: [[CPU_INFO_PTR:%.*]] = load ptr + // OGCG: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 + // OGCG: [[ADDR_PTR_0:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 0 + // OGCG: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 + // OGCG: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 + // OGCG: [[ADDR_PTR_1:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 1 + // OGCG: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 + // OGCG: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 + // OGCG: [[ADDR_PTR_2:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 2 + // OGCG: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 + // OGCG: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 + // OGCG: [[ADDR_PTR_3:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 3 + // OGCG: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 } >From 65f1e6c5c8807c3af0f64c31a94e3ebfe58d51b2 Mon Sep 17 00:00:00 2001 From: Priyanshu Kumar <[email protected]> Date: Sun, 18 Jan 2026 16:14:37 +0000 Subject: [PATCH 7/7] Update test --- .../CodeGenBuiltins/X86/ms-x86-intrinsics.c | 162 ++---------------- 1 file changed, 10 insertions(+), 152 deletions(-) diff --git a/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c index 099df36df2570..e56310ac113ce 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c @@ -21,15 +21,14 @@ unsigned __int64 __shiftright128(unsigned __int64 low, unsigned __int64 high, // LLVM-LABEL: define {{.*}} i64 @test_shiftleft128 // LLVM-SAME: (i64 %{{.*}}, i64 %{{.*}}, i8 %{{.*}}) // LLVM: [[TMP1:%.*]] = zext i8 %{{.*}} to i64 -// LLVM-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.fshl.i64(i64 %{{.*}}, i64 %{{.*}}, i64 [[TMP1]]) -// LLVM: ret i64 [[TMP2]] +// LLVM-NEXT: {{.*}} = call i64 @llvm.fshl.i64(i64 %{{.*}}, i64 %{{.*}}, i64 [[TMP1]]) // OGCG-LABEL: define {{.*}} i64 @test_shiftleft128 -// OGCG-SAME: (i64 {{.*}} %[[ARG0:.*]], i64 {{.*}} %[[ARG1:.*]], i8 {{.*}} %[[ARG2:.*]]) +// OGCG-SAME: (i64 {{.*}} %{{.*}}, i64 {{.*}} %{{.*}}, i8 {{.*}} %{{.*}}) // OGCG-NEXT: entry: -// OGCG-NEXT: [[TMP0:%.*]] = zext i8 %[[ARG2]] to i64 -// OGCG-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.fshl.i64(i64 %[[ARG1]], i64 %[[ARG0]], i64 [[TMP0]]) -// OGCG-NEXT: ret i64 [[TMP1]] +// OGCG: [[TMP:%.*]] = zext i8 {{.*}} to i64 +// OGCG-NEXT: {{.*}} = call i64 @llvm.fshl.i64(i64 {{.*}}, i64 {{.*}}, i64 [[TMP]]) +// OGCG-NEXT: ret i64 unsigned __int64 test_shiftleft128(unsigned __int64 l, unsigned __int64 h, unsigned char d) { return __shiftleft128(l, h, d); @@ -44,15 +43,14 @@ unsigned __int64 test_shiftleft128(unsigned __int64 l, unsigned __int64 h, // LLVM-LABEL: define {{.*}} i64 @test_shiftright128 // LLVM-SAME: (i64 %{{.*}}, i64 %{{.*}}, i8 %{{.*}}) // LLVM: [[TMP1:%.*]] = zext i8 %{{.*}} to i64 -// LLVM-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.fshr.i64(i64 %{{.*}}, i64 %{{.*}}, i64 [[TMP1]]) -// LLVM: ret i64 [[TMP2]] +// LLVM-NEXT: {{.*}} = call i64 @llvm.fshr.i64(i64 %{{.*}}, i64 %{{.*}}, i64 [[TMP1]]) // OGCG-LABEL: define {{.*}} i64 @test_shiftright128 -// OGCG-SAME: (i64 {{.*}} %[[ARG0:.*]], i64 {{.*}} %[[ARG1:.*]], i8 {{.*}} %[[ARG2:.*]]) +// OGCG-SAME: (i64 {{.*}} %{{.*}}, i64 {{.*}} %{{.*}}, i8 {{.*}} %{{.*}}) // OGCG-NEXT: entry: -// OGCG-NEXT: [[TMP0:%.*]] = zext i8 %[[ARG2]] to i64 -// OGCG-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.fshr.i64(i64 %[[ARG1]], i64 %[[ARG0]], i64 [[TMP0]]) -// OGCG-NEXT: ret i64 [[TMP1]] +// OGCG: [[TMP:%.*]] = zext i8 {{.*}} to i64 +// OGCG-NEXT: {{.*}} = call i64 @llvm.fshr.i64(i64 {{.*}}, i64 {{.*}}, i64 [[TMP]]) +// OGCG-NEXT: ret i64 unsigned __int64 test_shiftright128(unsigned __int64 l, unsigned __int64 h, unsigned char d) { return __shiftright128(l, h, d); @@ -198,143 +196,3 @@ void test__cpuidex(int cpuInfo[4], int functionId, int subFunctionId) { // OGCG: [[ADDR_PTR_3:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 3 // OGCG: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 } -#pragma intrinsic(__cpuid) -#pragma intrinsic(__cpuidex) - -void test__cpuid_with_cpu_info_as_pointer(int cpuInfo[4], int functionId) { - __cpuid(cpuInfo, functionId); - - // CIR-LABEL: __cpuid_with_cpu_info_as_pointer - // CIR: [[CPU_INFO_PTR:%.*]] = cir.load align(8) - // CIR: [[FUNCTION_ID:%.*]] = cir.load align(4) - // CIR: [[SUB_FUNCTION_ID:%.*]] = cir.const #cir.int<0> : !s32i - // CIR: cir.cpuid [[CPU_INFO_PTR]], [[FUNCTION_ID]], [[SUB_FUNCTION_ID]] : !cir.ptr<!s32i>, !s32i, !s32i - - // LLVM-LABEL: __cpuid_with_cpu_info_as_pointer - // LLVM: [[CPU_INFO_PTR:%.*]] = load ptr - // LLVM: [[FUNCTION_ID:%.*]] = load i32 - // LLVM: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID]], i32 0) - // LLVM: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 - // LLVM: [[ADDR_PTR_0:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 0 - // LLVM: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 - // LLVM: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 - // LLVM: [[ADDR_PTR_1:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 1 - // LLVM: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 - // LLVM: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 - // LLVM: [[ADDR_PTR_2:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 2 - // LLVM: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 - // LLVM: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 - // LLVM: [[ADDR_PTR_3:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 3 - // LLVM: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 - - // OGCG-LABEL: __cpuid_with_cpu_info_as_pointer - // OGCG: [[FUNCTION_ID:%.*]] = load i32 - // OGCG: [[FUNCTION_ID_ARG:%.*]] = load i32 - // OGCG: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID_ARG]], i32 0) - // OGCG: [[CPU_INFO_PTR:%.*]] = load ptr - // OGCG: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 - // OGCG: [[ADDR_PTR_0:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 0 - // OGCG: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 - // OGCG: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 - // OGCG: [[ADDR_PTR_1:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 1 - // OGCG: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 - // OGCG: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 - // OGCG: [[ADDR_PTR_2:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 2 - // OGCG: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 - // OGCG: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 - // OGCG: [[ADDR_PTR_3:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 3 - // OGCG: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 -} - -void test__cpuid_with_cpu_info_as_array(int functionId) { - int cpuInfo[4]; - __cpuid(cpuInfo, functionId); - - // CIR-LABEL: _cpuid_with_cpu_info_as_array - // CIR: [[CPU_INFO:%.*]] = cir.cast array_to_ptrdecay - // CIR: [[FUNCTION_ID:%.*]] = cir.load align(4) - // CIR: [[SUB_FUNCTION_ID:%.*]] = cir.const #cir.int<0> : !s32i - // CIR: cir.cpuid [[CPU_INFO_PTR]], [[FUNCTION_ID]], [[SUB_FUNCTION_ID]] : !cir.ptr<!s32i>, !s32i, !s32i - - // LLVM-LABEL: _cpuid_with_cpu_info_as_array - // LLVM: [[CPU_INFO_PTR:%.*]] = getelementptr i32, ptr - // LLVM: [[FUNCTION_ID:%.*]] = load i32 - // LLVM: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID]], i32 0) - // LLVM: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 - // LLVM: [[ADDR_PTR_0:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 0 - // LLVM: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 - // LLVM: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 - // LLVM: [[ADDR_PTR_1:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 1 - // LLVM: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 - // LLVM: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 - // LLVM: [[ADDR_PTR_2:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 2 - // LLVM: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 - // LLVM: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 - // LLVM: [[ADDR_PTR_3:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 3 - // LLVM: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 - - // OGCG-LABEL: _cpuid_with_cpu_info_as_array - // OGCG: [[FUNCTION_ID:%.*]] = load i32 - // OGCG: [[FUNCTION_ID_ARG:%.*]] = load i32 - // OGCG: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID_ARG]], i32 0) - // OGCG: [[CPU_INFO_PTR:%.*]] = getelementptr inbounds [4 x i32], ptr - // OGCG: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 - // OGCG: [[ADDR_PTR_0:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 0 - // OGCG: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 - // OGCG: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 - // OGCG: [[ADDR_PTR_1:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 1 - // OGCG: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 - // OGCG: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 - // OGCG: [[ADDR_PTR_2:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 2 - // OGCG: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 - // OGCG: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 - // OGCG: [[ADDR_PTR_3:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 3 - // OGCG: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 -} -void test__cpuidex(int cpuInfo[4], int functionId, int subFunctionId) { - __cpuidex(cpuInfo, functionId, subFunctionId); - - // CIR-LABEL: __cpuidex - // CIR: [[CPU_INFO_PTR:%.*]] = cir.load align(8) - // CIR: [[FUNCTION_ID:%.*]] = cir.load align(4) - // CIR: [[SUB_FUNCTION_ID:%.*]] = cir.load align(4) - // CIR: cir.cpuid [[CPU_INFO_PTR]], [[FUNCTION_ID]], [[SUB_FUNCTION_ID]] : !cir.ptr<!s32i>, !s32i, !s32i - - // LLVM-LABEL: __cpuidex - // LLVM: [[CPU_INFO_PTR:%.*]] = load ptr - // LLVM: [[FUNCTION_ID:%.*]] = load i32 - // LLVM: [[SUB_FUNCTION_ID:%.*]] = load i32 - // LLVM: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID]], i32 [[SUB_FUNCTION_ID]]) - // LLVM: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 - // LLVM: [[ADDR_PTR_0:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 0 - // LLVM: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 - // LLVM: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 - // LLVM: [[ADDR_PTR_1:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 1 - // LLVM: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 - // LLVM: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 - // LLVM: [[ADDR_PTR_2:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 2 - // LLVM: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 - // LLVM: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 - // LLVM: [[ADDR_PTR_3:%.*]] = getelementptr i32, ptr [[CPU_INFO_PTR]], i64 3 - // LLVM: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 - - // OGCG-LABEL: __cpuidex - // OGCG: [[FUNCTION_ID:%.*]] = load i32 - // OGCG: [[SUB_FUNCTION_ID:%.*]] = load i32 - // OGCG: [[FUNCTION_ID_ARG:%.*]] = load i32 - // OGCG: [[SUB_FUNCTION_ID_ARG:%.*]] = load i32 - // OGCG: [[ASM_RESULTS:%.*]] = call { i32, i32, i32, i32 } asm "{{.*}}cpuid{{.*}}", "={ax},=r,={cx},={dx},0,2"(i32 [[FUNCTION_ID_ARG]], i32 [[SUB_FUNCTION_ID_ARG]]) - // OGCG: [[CPU_INFO_PTR:%.*]] = load ptr - // OGCG: [[RESULT_0:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 0 - // OGCG: [[ADDR_PTR_0:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 0 - // OGCG: store i32 [[RESULT_0]], ptr [[ADDR_PTR_0]], align 4 - // OGCG: [[RESULT_1:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 1 - // OGCG: [[ADDR_PTR_1:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 1 - // OGCG: store i32 [[RESULT_1]], ptr [[ADDR_PTR_1]], align 4 - // OGCG: [[RESULT_2:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 2 - // OGCG: [[ADDR_PTR_2:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 2 - // OGCG: store i32 [[RESULT_2]], ptr [[ADDR_PTR_2]], align 4 - // OGCG: [[RESULT_3:%.*]] = extractvalue { i32, i32, i32, i32 } [[ASM_RESULTS]], 3 - // OGCG: [[ADDR_PTR_3:%.*]] = getelementptr inbounds i32, ptr [[CPU_INFO_PTR]], i32 3 - // OGCG: store i32 [[RESULT_3]], ptr [[ADDR_PTR_3]], align 4 -} _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
