================
@@ -1119,6 +1119,28 @@ def HasStdExtZbkbOrP
"'Zbkb' (Bitmanip instructions for Cryptography) or "
"'Base P' (Packed-SIMD)">;
+// "Y" extension (CHERI support)
+
+def FeatureStdExtY : RISCVExperimentalExtension<0, 96, "'Base Y' (CHERI)">;
+def HasStdExtY
+ : Predicate<"Subtarget->hasStdExtY()">,
+ AssemblerPredicate<(all_of FeatureStdExtY), "'Base Y' (CHERI)">;
+
+// When enabled all memory operations (e.g. loads/stores) uses capability
+// registers as the base operand instead of the address sub-register.
+// Currently, capability mode needs to be chosen at assembly time, but
follow-up
+// commits will add support for "hybrid" mode that adds instructions to
+// dynamically switch between capability mode and address mode (the latter
being
+// fully backwards compatible with non-Y code).
+def FeatureCapMode : SubtargetFeature<"cap-mode", "IsCapMode", "true",
----------------
jrtc27 wrote:
We should name this based on whatever ended up in the RVY spec?
https://github.com/llvm/llvm-project/pull/176870
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