https://github.com/artagnon updated https://github.com/llvm/llvm-project/pull/178199
>From 684c68fd3978cdda9324275d6bf82992f4f13e17 Mon Sep 17 00:00:00 2001 From: Ramkumar Ramachandra <[email protected]> Date: Tue, 27 Jan 2026 12:39:16 +0000 Subject: [PATCH 1/2] [RISCV] Rename TensTorrent Ascalon D8 to Ascalon X As per the official release document. D8 is a former name, used internally. Ref: Brief from https://tenstorrent.com/en/ip/risc-v-cpu --- clang/test/Driver/riscv-cpus.c | 138 +++++++++--------- .../test/Misc/target-invalid-cpu-note/riscv.c | 4 +- llvm/lib/Target/RISCV/RISCV.td | 2 +- llvm/lib/Target/RISCV/RISCVProcessors.td | 4 +- ...TTAscalonD8.td => RISCVSchedTTAscalonX.td} | 6 +- .../{tt-ascalon-d8 => tt-ascalon-x}/fp.s | 2 +- .../{tt-ascalon-d8 => tt-ascalon-x}/fx.s | 2 +- .../vdiv_vsqrt.s | 2 +- .../vislide-vx.s | 2 +- .../vle-vse-vlm.s | 2 +- .../vlse-vsse.s | 2 +- .../vlseg-vsseg.s | 2 +- .../vlxe-vsxe.s | 2 +- .../{tt-ascalon-d8 => tt-ascalon-x}/vmv.s | 2 +- .../{tt-ascalon-d8 => tt-ascalon-x}/vreduce.s | 2 +- .../vrgather-vcompress.s | 2 +- .../vshift-vmul.s | 2 +- 17 files changed, 89 insertions(+), 89 deletions(-) rename llvm/lib/Target/RISCV/{RISCVSchedTTAscalonD8.td => RISCVSchedTTAscalonX.td} (99%) rename llvm/test/tools/llvm-mca/RISCV/{tt-ascalon-d8 => tt-ascalon-x}/fp.s (99%) rename llvm/test/tools/llvm-mca/RISCV/{tt-ascalon-d8 => tt-ascalon-x}/fx.s (99%) rename llvm/test/tools/llvm-mca/RISCV/{tt-ascalon-d8 => tt-ascalon-x}/vdiv_vsqrt.s (99%) rename llvm/test/tools/llvm-mca/RISCV/{tt-ascalon-d8 => tt-ascalon-x}/vislide-vx.s (98%) rename llvm/test/tools/llvm-mca/RISCV/{tt-ascalon-d8 => tt-ascalon-x}/vle-vse-vlm.s (99%) rename llvm/test/tools/llvm-mca/RISCV/{tt-ascalon-d8 => tt-ascalon-x}/vlse-vsse.s (99%) rename llvm/test/tools/llvm-mca/RISCV/{tt-ascalon-d8 => tt-ascalon-x}/vlseg-vsseg.s (99%) rename llvm/test/tools/llvm-mca/RISCV/{tt-ascalon-d8 => tt-ascalon-x}/vlxe-vsxe.s (99%) rename llvm/test/tools/llvm-mca/RISCV/{tt-ascalon-d8 => tt-ascalon-x}/vmv.s (99%) rename llvm/test/tools/llvm-mca/RISCV/{tt-ascalon-d8 => tt-ascalon-x}/vreduce.s (99%) rename llvm/test/tools/llvm-mca/RISCV/{tt-ascalon-d8 => tt-ascalon-x}/vrgather-vcompress.s (98%) rename llvm/test/tools/llvm-mca/RISCV/{tt-ascalon-d8 => tt-ascalon-x}/vshift-vmul.s (98%) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 46f2c390b6efe..c0e0f5b3b0794 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -205,75 +205,75 @@ // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-max | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-MAX %s // MTUNE-SYNTACORE-SCR1-MAX: "-tune-cpu" "syntacore-scr1-max" -// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=tt-ascalon-d8 | FileCheck -check-prefix=MTUNE-TT-ASCALON-D8 %s -// MTUNE-TT-ASCALON-D8: "-tune-cpu" "tt-ascalon-d8" - -// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=tt-ascalon-d8 | FileCheck -check-prefix=MCPU-TT-ASCALON-D8 %s -// MCPU-TT-ASCALON-D8: "-target-cpu" "tt-ascalon-d8" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+m" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+a" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+f" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+d" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+c" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+v" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+h" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicbom" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicbop" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicboz" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicntr" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicond" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicsr" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zifencei" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintntl" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintpause" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihpm" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zimop" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zmmul" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zawrs" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfa" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfbfmin" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfh" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfhmin" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zca" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zcb" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zba" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zbb" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zbs" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zkr" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zkt" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvbb" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvbc" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve32f" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve32x" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64d" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64f" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64x" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfbfmin" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfbfwma" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfh" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfhmin" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkb" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkg" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkn" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvknc" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkned" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkng" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvknhb" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkt" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl128b" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl256b" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl32b" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl64b" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+smaia" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+smmpm" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+smnpm" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+smrnmi" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+smstateen" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+sscofpmf" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svinval" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svnapot" -// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svpbmt" -// MCPU-TT-ASCALON-D8-SAME: "-target-abi" "lp64d" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=tt-ascalon-x | FileCheck -check-prefix=MTUNE-TT-ASCALON-X %s +// MTUNE-TT-ASCALON-X: "-tune-cpu" "tt-ascalon-x" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=tt-ascalon-x | FileCheck -check-prefix=MCPU-TT-ASCALON-X %s +// MCPU-TT-ASCALON-X: "-target-cpu" "tt-ascalon-x" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+m" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+a" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+f" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+d" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+c" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+v" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+h" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zicbom" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zicbop" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zicboz" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zicntr" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zicond" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zicsr" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zifencei" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zihintntl" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zihintpause" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zihpm" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zimop" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zmmul" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zawrs" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zfa" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zfbfmin" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zfh" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zfhmin" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zca" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zcb" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zba" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zbb" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zbs" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zkr" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zkt" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvbb" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvbc" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zve32f" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zve32x" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zve64d" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zve64f" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zve64x" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvfbfmin" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvfbfwma" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvfh" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvfhmin" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvkb" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvkg" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvkn" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvknc" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvkned" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvkng" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvknhb" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvkt" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvl128b" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvl256b" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvl32b" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvl64b" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+smaia" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+smmpm" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+smnpm" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+smrnmi" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+smstateen" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+sscofpmf" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+svinval" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+svnapot" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+svpbmt" +// MCPU-TT-ASCALON-X-SAME: "-target-abi" "lp64d" // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=veyron-v1 | FileCheck -check-prefix=MCPU-VEYRON-V1 %s // MCPU-VEYRON-V1: "-target-cpu" "veyron-v1" diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c index ca46f1d1e9a06..c79cad26f8f81 100644 --- a/clang/test/Misc/target-invalid-cpu-note/riscv.c +++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c @@ -55,7 +55,7 @@ // RISCV64-SAME: {{^}}, syntacore-scr4-rv64 // RISCV64-SAME: {{^}}, syntacore-scr5-rv64 // RISCV64-SAME: {{^}}, syntacore-scr7 -// RISCV64-SAME: {{^}}, tt-ascalon-d8 +// RISCV64-SAME: {{^}}, tt-ascalon-x // RISCV64-SAME: {{^}}, veyron-v1 // RISCV64-SAME: {{^}}, xiangshan-kunminghu // RISCV64-SAME: {{^}}, xiangshan-nanhu @@ -119,7 +119,7 @@ // TUNE-RISCV64-SAME: {{^}}, syntacore-scr4-rv64 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr5-rv64 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr7 -// TUNE-RISCV64-SAME: {{^}}, tt-ascalon-d8 +// TUNE-RISCV64-SAME: {{^}}, tt-ascalon-x // TUNE-RISCV64-SAME: {{^}}, veyron-v1 // TUNE-RISCV64-SAME: {{^}}, xiangshan-kunminghu // TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index f6f82fd9bb55f..70bf802cb4625 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -64,7 +64,7 @@ include "RISCVSchedSpacemitX60.td" include "RISCVSchedSyntacoreSCR1.td" include "RISCVSchedSyntacoreSCR345.td" include "RISCVSchedSyntacoreSCR7.td" -include "RISCVSchedTTAscalonD8.td" +include "RISCVSchedTTAscalonX.td" include "RISCVSchedXiangShanNanHu.td" //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index f7bc3b28fb3a4..79c9cef798b38 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -616,8 +616,8 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, TunePostRAScheduler]>; -def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8", - TTAscalonD8Model, +def TENSTORRENT_ASCALON_X : RISCVProcessorModel<"tt-ascalon-x", + TTAscalonXModel, !listconcat(RVA23S64Features, [FeatureStdExtSmaia, FeatureStdExtSmmpm, diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td similarity index 99% rename from llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td rename to llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td index 08ee180b2cb0f..eecae36a2d83d 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td +++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td @@ -1,4 +1,4 @@ -//=- RISCVSchedTTAscalonD8.td - TT Ascalon D8 Sched Defs -----*- tablegen -*-=// +//=- RISCVSchedTTAscalonX.td - TT Ascalon X Sched Defs -------*- tablegen -*-=// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -95,7 +95,7 @@ class AscalonGetCyclesStridedSegmented<string mx, int sew> { //===----------------------------------------------------------------------===// -def TTAscalonD8Model : SchedMachineModel { +def TTAscalonXModel : SchedMachineModel { let IssueWidth = 8; // 8-way decode and dispatch let MicroOpBufferSize = 256; // 256 micro-op re-order buffer let LoadLatency = 4; // Optimistic load latency @@ -110,7 +110,7 @@ def TTAscalonD8Model : SchedMachineModel { HasStdExtZkr]; } -let SchedModel = TTAscalonD8Model in { +let SchedModel = TTAscalonXModel in { //===----------------------------------------------------------------------===// // Define each kind of processor resource and number available. diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fp.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/fp.s similarity index 99% rename from llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fp.s rename to llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/fp.s index 7f44bd0eccdcb..be22f31b9d690 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fp.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/fp.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=tt-ascalon-d8 --iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=tt-ascalon-x --iterations=1 < %s | FileCheck %s fmin.s ft0, fa0, fa1 fmax.s ft1, fa0, fa1 diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fx.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/fx.s similarity index 99% rename from llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fx.s rename to llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/fx.s index d10cc3f57e970..18c584485e459 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fx.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/fx.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=tt-ascalon-d8 --iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=tt-ascalon-x --iterations=1 < %s | FileCheck %s mul t0, a0, t0 sub s2, a2, a3 diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vdiv_vsqrt.s similarity index 99% rename from llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s rename to llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vdiv_vsqrt.s index 53711ed515663..53468935969e8 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vdiv_vsqrt.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s vsetvli zero, zero, e8, mf8, tu, mu vdiv.vv v8, v16, v24 diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vislide-vx.s similarity index 98% rename from llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s rename to llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vislide-vx.s index d819922e114d0..b8ac1beea93bd 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vislide-vx.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s vsetvli zero, zero, e32, m2, tu, mu vslidedown.vx v5, v7, x6 diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vle-vse-vlm.s similarity index 99% rename from llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s rename to llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vle-vse-vlm.s index 807b9f94d2f02..291c810b423e2 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vle-vse-vlm.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s vsetvli zero, zero, e8, mf8, ta, ma vle8.v v8, (a0) diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlse-vsse.s similarity index 99% rename from llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s rename to llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlse-vsse.s index 96cec1327621b..4b9840eb77d44 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlse-vsse.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s vsetvli zero, zero, e8, mf8, ta, ma vlse8.v v8, (a0), t0 diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlseg-vsseg.s similarity index 99% rename from llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s rename to llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlseg-vsseg.s index c528f647b4bfd..8871d64582439 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlseg-vsseg.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s vsetvli zero, zero, e8, mf8, tu, mu vlseg2e8.v v8,(a0) diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlxe-vsxe.s similarity index 99% rename from llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s rename to llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlxe-vsxe.s index cf5f8b04374be..cc8dac76bf59c 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vlxe-vsxe.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s vsetvli zero, zero, e8, mf8, ta, ma vluxei8.v v8, (a0), v0 diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vmv.s similarity index 99% rename from llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s rename to llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vmv.s index c131414bc78e5..45838b902a9d6 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vmv.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s vsetvli zero, zero, e8, mf8, tu, mu vmv1r.v v8, v16 diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vreduce.s similarity index 99% rename from llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s rename to llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vreduce.s index 020a0a0192aa4..5a8b27eefaa3f 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vreduce.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s # Simple integer reductions: varies by LMUL vsetvli zero, zero, e32, m1, tu, mu diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vrgather-vcompress.s similarity index 98% rename from llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s rename to llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vrgather-vcompress.s index 9e2e0a5a2aa7a..0924322ac19f8 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vrgather-vcompress.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s vsetvli zero, zero, e32, m1, tu, mu vrgather.vv v5, v7, v8 diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vshift-vmul.s similarity index 98% rename from llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s rename to llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vshift-vmul.s index cbddf81d5867c..351d0653c0807 100644 --- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s +++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vshift-vmul.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s vsetvli zero, zero, e32, m1, ta, ma >From 7d6442516393e16fba5659bddbc288ff0935c2ed Mon Sep 17 00:00:00 2001 From: Ramkumar Ramachandra <[email protected]> Date: Tue, 27 Jan 2026 13:33:10 +0000 Subject: [PATCH 2/2] [clang/ReleaseNotes] Add note about rename --- clang/docs/ReleaseNotes.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index f0d3d81f14e43..c516d2395afad 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -254,6 +254,8 @@ LoongArch Support RISC-V Support ^^^^^^^^^^^^^^ +- Tenstorrent Ascalon D8 was renamed to Ascalon X. Use `tt-ascalon-x` with `-mcpu` or `-mtune`. + CUDA/HIP Language Changes ^^^^^^^^^^^^^^^^^^^^^^^^^ _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
