https://github.com/Men-cotton created 
https://github.com/llvm/llvm-project/pull/184005

Update bitfield-assignment codegen to emit stores at assignment-expression 
source locations.
Keep `cir.set_bitfield` aligned with other store-like operations.
Prevent regressions that reattach bitfield stores to declaration-site locations.

Add a CIR test on `clang/test/CIR/CodeGen/bitfield-assignment-loc.c`.]

Fix https://github.com/llvm/llvm-project/issues/183759

>From a5bc86a39cb28489f123e23ef2d66d6fc116fe24 Mon Sep 17 00:00:00 2001
From: mencotton <[email protected]>
Date: Sun, 1 Mar 2026 22:14:57 +0900
Subject: [PATCH] [CIR] Fix bitfield store locations for assignment codegen

---
 clang/lib/CIR/CodeGen/CIRGenExpr.cpp             |  4 ++--
 clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp       |  2 ++
 clang/test/CIR/CodeGen/bitfield-assignment-loc.c | 15 +++++++++++++++
 3 files changed, 19 insertions(+), 2 deletions(-)
 create mode 100644 clang/test/CIR/CodeGen/bitfield-assignment-loc.c

diff --git a/clang/lib/CIR/CodeGen/CIRGenExpr.cpp 
b/clang/lib/CIR/CodeGen/CIRGenExpr.cpp
index 4eccf430cd622..d0fa9234c73c3 100644
--- a/clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenExpr.cpp
@@ -384,9 +384,9 @@ mlir::Value 
CIRGenFunction::emitStoreThroughBitfieldLValue(RValue src,
                      dst.isVolatileQualified() &&
                      info.volatileStorageSize != 0 && isAAPCS(cgm.getTarget());
 
-  mlir::Value dstAddr = dst.getAddress().getPointer();
+  assert(currSrcLoc && "must pass in source location");
 
-  return builder.createSetBitfield(dstAddr.getLoc(), resLTy, ptr,
+  return builder.createSetBitfield(*currSrcLoc, resLTy, ptr,
                                    ptr.getElementType(), src.getValue(), info,
                                    dst.isVolatileQualified(), useVoaltile);
 }
diff --git a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp 
b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
index 03c8369753f35..c0be40d37701c 100644
--- a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
@@ -1251,6 +1251,8 @@ class ScalarExprEmitter : public 
StmtVisitor<ScalarExprEmitter, mlir::Value> {
       // 'An assignment expression has the value of the left operand after the
       // assignment...'.
       if (lhs.isBitField()) {
+        CIRGenFunction::SourceLocRAIIObject loc{
+            cgf, cgf.getLoc(e->getSourceRange())};
         rhs = cgf.emitStoreThroughBitfieldLValue(RValue::get(rhs), lhs);
       } else {
         cgf.emitNullabilityCheck(lhs, rhs, e->getExprLoc());
diff --git a/clang/test/CIR/CodeGen/bitfield-assignment-loc.c 
b/clang/test/CIR/CodeGen/bitfield-assignment-loc.c
new file mode 100644
index 0000000000000..aebcb614dbfa2
--- /dev/null
+++ b/clang/test/CIR/CodeGen/bitfield-assignment-loc.c
@@ -0,0 +1,15 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu 
-Wno-bitfield-constant-conversion -fclangir -emit-cir %s -o - | FileCheck %s
+
+struct C {
+  int c : 8;
+};
+
+void foo(void) {
+  struct C c;
+  c.c = 800;
+}
+
+// CHECK: %[[SETBF:.*]] = cir.set_bitfield{{.*}} loc(#[[SET_LOC:loc[0-9]+]])
+// CHECK-DAG: #[[SET_BEGIN:loc[0-9]+]] = 
loc("{{.*}}bitfield-assignment-loc.c":9:3)
+// CHECK-DAG: #[[SET_END:loc[0-9]+]] = 
loc("{{.*}}bitfield-assignment-loc.c":9:9)
+// CHECK-DAG: #[[SET_LOC]] = loc(fused[#[[SET_BEGIN]], #[[SET_END]]])

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