================
@@ -1001,6 +1004,71 @@ bool AArch64ExpandPseudo::expandStoreSwiftAsyncContext(
return true;
}
+bool AArch64ExpandPseudo::expandSTSHHAtomicStore(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
+ MachineInstr &MI = *MBBI;
+ DebugLoc DL(MI.getDebugLoc());
+
+ unsigned Order = MI.getOperand(2).getImm();
+ unsigned Policy = MI.getOperand(3).getImm();
+ unsigned Size = MI.getOperand(4).getImm();
+
+ bool IsRelaxed = Order == 0;
+ unsigned StoreOpc = 0;
+
+ // __ATOMIC_RELAXED uses STR. __ATOMIC_{RELEASE/SEQ_CST} use STLR.
+ switch (Size) {
+ case 8:
+ StoreOpc = IsRelaxed ? AArch64::STRBBui : AArch64::STLRB;
+ break;
+ case 16:
+ StoreOpc = IsRelaxed ? AArch64::STRHHui : AArch64::STLRH;
+ break;
+ case 32:
+ StoreOpc = IsRelaxed ? AArch64::STRWui : AArch64::STLRW;
+ break;
+ case 64:
+ StoreOpc = IsRelaxed ? AArch64::STRXui : AArch64::STLRX;
+ break;
+ default:
+ llvm_unreachable("Unexpected STSHH atomic store size");
+ }
+
+ // Emit the hint with the retention policy immediate.
+ MachineInstr *Hint = BuildMI(MBB, MBBI, DL, TII->get(AArch64::STSHH))
+ .addImm(Policy)
+ .getInstr();
+
+ // Emit the associated store instruction.
+ Register ValReg = MI.getOperand(0).getReg();
+
+ if (Size < 64) {
+ const TargetRegisterInfo *TRI =
+ MBB.getParent()->getSubtarget().getRegisterInfo();
+ Register SubReg = TRI->getSubReg(ValReg, AArch64::sub_32);
+ if (SubReg)
+ ValReg = SubReg;
+ }
+
+ MachineInstrBuilder Store = BuildMI(MBB, MBBI, DL, TII->get(StoreOpc))
+ .addReg(ValReg)
+ .add(MI.getOperand(1));
+
+ // Relaxed uses base+imm addressing with a zero offset.
----------------
CarolineConcatto wrote:
I imagine this will always be zero.
https://github.com/llvm/llvm-project/pull/181386
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