================
@@ -516,14 +516,16 @@ BitVector X86RegisterInfo::getReservedRegs(const
MachineFunction &MF) const {
Reserved.set(X86::SSP);
auto &ST = MF.getSubtarget<X86Subtarget>();
- if (ST.is64Bit()) {
- for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
- // Set r# as reserved register if user required
- if (ST.isRegisterReservedByUser(Reg)) {
+ if (ST.is64Bit() && ST.hasUserReservedRegisters()) {
+ // Set r# as reserved register if user required
+ for (unsigned Reg = X86::R8; Reg <= X86::R15; ++Reg)
+ if (ST.isRegisterReservedByUser(Reg))
+ for (const MCPhysReg &SubReg : subregs_inclusive(Reg))
+ Reserved.set(SubReg);
+ for (unsigned Reg = X86::R16; Reg <= X86::R31; ++Reg)
----------------
zhouguangyuan0718 wrote:
Done
https://github.com/llvm/llvm-project/pull/184606
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