Author: Craig Topper Date: 2026-03-25T20:14:51-07:00 New Revision: 901073a9a8d81c24742e884ed7aa371758a5bfdb
URL: https://github.com/llvm/llvm-project/commit/901073a9a8d81c24742e884ed7aa371758a5bfdb DIFF: https://github.com/llvm/llvm-project/commit/901073a9a8d81c24742e884ed7aa371758a5bfdb.diff LOG: [RISCV] Update P extension to 0.21 (#188121) Add the new shift and pnclip instructions. Spec PR https://github.com/riscv/riscv-p-spec/pull/237 Added: Modified: clang/test/Driver/print-supported-extensions-riscv.c clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.md llvm/lib/Target/RISCV/RISCVFeatures.td llvm/lib/Target/RISCV/RISCVInstrInfoP.td llvm/test/CodeGen/RISCV/attributes.ll llvm/test/MC/RISCV/attribute-arch.s llvm/test/MC/RISCV/rv32p-valid.s llvm/test/MC/RISCV/rv64p-valid.s llvm/unittests/TargetParser/RISCVISAInfoTest.cpp Removed: ################################################################################ diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 4ee470a76f213..b9696f0c7ec7d 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -241,7 +241,7 @@ // CHECK-NEXT: xwchc 2.2 'Xwchc' (WCH/QingKe additional compressed opcodes) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions -// CHECK-NEXT: p 0.20 'P' ('Base P' (Packed SIMD)) +// CHECK-NEXT: p 0.21 'P' ('Base P' (Packed SIMD)) // CHECK-NEXT: y 0.96 'Y' ('Base Y' (CHERI)) // CHECK-NEXT: zibi 0.1 'Zibi' (Branch with Immediate) // CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 1c8018c57ece2..3882f2889eb59 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -1586,12 +1586,12 @@ // Experimental extensions // RUN: %clang --target=riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_p0p20 -E -dM %s \ +// RUN: -march=rv32i_p0p21 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s // RUN: %clang --target=riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_p0p20 -E -dM %s \ +// RUN: -march=rv64i_p0p21 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s -// CHECK-P-EXT: __riscv_p 20000{{$}} +// CHECK-P-EXT: __riscv_p 21000{{$}} // // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32izfbfmin1p0 -E -dM %s \ diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index c1aff252eeac5..bfc7d0afa008b 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -336,7 +336,7 @@ LLVM supports (to various degrees) a number of experimental extensions. All exp The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised. ``experimental-p`` - LLVM implements the `0.20 draft specification <https://github.com/riscv/riscv-p-spec/blob/master/P-ext-proposal.adoc>`__. + LLVM implements the `0.21 draft specification <https://github.com/riscv/riscv-p-spec/blob/master/P-ext-proposal.adoc>`__. ``experimental-zibi`` LLVM implements the `0.1 release specification <https://github.com/riscv/zibi/releases/tag/v0.1.0>`__. diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 6be21fd2baf9f..e3e655009d148 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -167,7 +167,7 @@ Changes to the RISC-V Backend * `llvm-objdump` now has support for `--symbolize-operands` with RISC-V. * `-mcpu=spacemit-x100` was added. -* Change P extension version to match the 0.20 draft specification. +* Change P extension version to match the 0.21 draft specification. * Mnemonics for MOP/HINT-based instructions (`lpad`, `pause`, `ntl.*`, `c.ntl.*`, `sspush`, `sspopchk`, `ssrdp`, `c.sspush`, `c.sspopchk`) are now always available in the assembler and disassembler without requiring their respective diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 0fe89072e5aa9..78abee4bdf15a 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1114,7 +1114,7 @@ def HasStdExtSmctrOrSsctr : Predicate<"Subtarget->hasStdExtSmctrOrSsctr()">, // Packed SIMD Extensions def FeatureStdExtP - : RISCVExperimentalExtension<0, 20, + : RISCVExperimentalExtension<0, 21, "'Base P' (Packed SIMD)", [FeatureStdExtZmmul, FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZicsr]>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td index 826abfa689682..5ca1fc637e9c0 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td @@ -622,6 +622,12 @@ let Predicates = [HasStdExtP] in { def PADD_HS : RVPBinaryScalar_rr<0b001, 0b00, 0b010, "padd.hs">; def PADD_BS : RVPBinaryScalar_rr<0b001, 0b10, 0b010, "padd.bs">; + let Defs = [VXSAT] in + def PSSHL_HS : RVPBinaryScalar_rr<0b010, 0b00, 0b010, "psshl.hs">; + + let Defs = [VXSAT] in + def PSSHLR_HS : RVPBinaryScalar_rr<0b011, 0b00, 0b010, "psshlr.hs">; + let Defs = [VXSAT] in def PSSHA_HS : RVPBinaryScalar_rr<0b110, 0b00, 0b010, "pssha.hs">; @@ -629,6 +635,12 @@ let Predicates = [HasStdExtP] in { def PSSHAR_HS : RVPBinaryScalar_rr<0b111, 0b00, 0b010, "psshar.hs">; } // Predicates = [HasStdExtP] let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in { + let Defs = [VXSAT] in + def SSHL : RVPBinaryScalar_rr<0b010, 0b01, 0b010, "sshl">; + + let Defs = [VXSAT] in + def SSHLR : RVPBinaryScalar_rr<0b011, 0b01, 0b010, "sshlr">; + let Defs = [VXSAT] in def SSHA : RVPBinaryScalar_rr<0b110, 0b01, 0b010, "ssha">; @@ -640,6 +652,16 @@ let Predicates = [HasStdExtP, IsRV64] in { def PADD_WS : RVPBinaryScalar_rr<0b001, 0b01, 0b010, "padd.ws">; + let Defs = [VXSAT] in { + def PSSHL_WS : RVPBinaryScalar_rr<0b010, 0b01, 0b010, "psshl.ws">; + def SHL : RVPBinaryScalar_rr<0b010, 0b11, 0b010, "shl">; + } // Defs = [VXSAT] + + let Defs = [VXSAT] in { + def PSSHLR_WS : RVPBinaryScalar_rr<0b011, 0b01, 0b010, "psshlr.ws">; + def SHLR : RVPBinaryScalar_rr<0b011, 0b11, 0b010, "shlr">; + } // Defs = [VXSAT] + let Defs = [VXSAT] in { def PSSHA_WS : RVPBinaryScalar_rr<0b110, 0b01, 0b010, "pssha.ws">; def SHA : RVPBinaryScalar_rr<0b110, 0b11, 0b010, "sha">; @@ -849,30 +871,42 @@ let Predicates = [HasStdExtP, IsRV64] in { // Note the spec has a 3-bit f field in bits 30:28 with 0 in bit 27. // Here we include the 0 in the f field to reduce number of tablegen classes. let Predicates = [HasStdExtP] in { - def PSH1ADD_H : RVPBinary_rr<0b0100, 0b00, 0b010, "psh1add.h">; + def PSH1ADD_H : RVPBinary_rr<0b0100, 0b00, 0b010, "psh1add.h">; let Defs = [VXSAT] in - def PSSH1SADD_H : RVPBinary_rr<0b0110, 0b00, 0b010, "pssh1sadd.h">; + def PSSH1SADD_H : RVPBinary_rr<0b0110, 0b00, 0b010, "pssh1sadd.h">; } // Predicates = [HasStdExtP] let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in { let Defs = [VXSAT] in - def SSH1SADD : RVPBinary_rr<0b0110, 0b01, 0b010, "ssh1sadd">; + def SSH1SADD : RVPBinary_rr<0b0110, 0b01, 0b010, "ssh1sadd">; } // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" let Predicates = [HasStdExtP, IsRV64] in { - def PSH1ADD_W : RVPBinary_rr<0b0100, 0b01, 0b010, "psh1add.w">; + let Defs = [VXSAT] in { + def PNCLIPUP_B : RVPBinary_rr<0b0000, 0b00, 0b010, "pnclipup.b">; + def PNCLIPUP_H : RVPBinary_rr<0b0000, 0b01, 0b010, "pnclipup.h">; + def PNCLIPUP_W : RVPBinary_rr<0b0000, 0b11, 0b010, "pnclipup.w">; + } + + def PSH1ADD_W : RVPBinary_rr<0b0100, 0b01, 0b010, "psh1add.w">; let Defs = [VXSAT] in - def PSSH1SADD_W : RVPBinary_rr<0b0110, 0b01, 0b010, "pssh1sadd.w">; + def PSSH1SADD_W : RVPBinary_rr<0b0110, 0b01, 0b010, "pssh1sadd.w">; + + let Defs = [VXSAT] in { + def PNCLIPP_B : RVPBinary_rr<0b1000, 0b00, 0b010, "pnclipp.b">; + def PNCLIPP_H : RVPBinary_rr<0b1000, 0b01, 0b010, "pnclipp.h">; + def PNCLIPP_W : RVPBinary_rr<0b1000, 0b11, 0b010, "pnclipp.w">; + } - def UNZIP8P : RVPBinary_rr<0b1100, 0b00, 0b010, "unzip8p">; - def UNZIP16P : RVPBinary_rr<0b1100, 0b01, 0b010, "unzip16p">; - def UNZIP8HP : RVPBinary_rr<0b1100, 0b10, 0b010, "unzip8hp">; - def UNZIP16HP : RVPBinary_rr<0b1100, 0b11, 0b010, "unzip16hp">; + def UNZIP8P : RVPBinary_rr<0b1100, 0b00, 0b010, "unzip8p">; + def UNZIP16P : RVPBinary_rr<0b1100, 0b01, 0b010, "unzip16p">; + def UNZIP8HP : RVPBinary_rr<0b1100, 0b10, 0b010, "unzip8hp">; + def UNZIP16HP : RVPBinary_rr<0b1100, 0b11, 0b010, "unzip16hp">; - def ZIP8P : RVPBinary_rr<0b1110, 0b00, 0b010, "zip8p">; - def ZIP16P : RVPBinary_rr<0b1110, 0b01, 0b010, "zip16p">; - def ZIP8HP : RVPBinary_rr<0b1110, 0b10, 0b010, "zip8hp">; - def ZIP16HP : RVPBinary_rr<0b1110, 0b11, 0b010, "zip16hp">; + def ZIP8P : RVPBinary_rr<0b1110, 0b00, 0b010, "zip8p">; + def ZIP16P : RVPBinary_rr<0b1110, 0b01, 0b010, "zip16p">; + def ZIP8HP : RVPBinary_rr<0b1110, 0b10, 0b010, "zip8hp">; + def ZIP16HP : RVPBinary_rr<0b1110, 0b11, 0b010, "zip16hp">; } // Predicates = [HasStdExtP, IsRV64] let Predicates = [HasStdExtP] in { @@ -1477,6 +1511,16 @@ let Predicates = [HasStdExtP, IsRV32] in { def PADD_DWS : RVPPairShift_rr<0b001, 0b01, "padd.dws">; def PADD_DBS : RVPPairShift_rr<0b001, 0b10, "padd.dbs">; + let Defs = [VXSAT] in { + def PSSHL_DHS : RVPPairShift_rr<0b010, 0b00, "psshl.dhs">; + def PSSHL_DWS : RVPPairShift_rr<0b010, 0b01, "psshl.dws">; + } // Defs = [VXSAT] + + let Defs = [VXSAT] in { + def PSSHLR_DHS : RVPPairShift_rr<0b011, 0b00, "psshlr.dhs">; + def PSSHLR_DWS : RVPPairShift_rr<0b011, 0b01, "psshlr.dws">; + } // Defs = [VXSAT] + let Defs = [VXSAT] in { def PSSHA_DHS : RVPPairShift_rr<0b110, 0b00, "pssha.dhs">; def PSSHA_DWS : RVPPairShift_rr<0b110, 0b01, "pssha.dws">; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 2f0e35d339f01..311418fc845ab 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -626,7 +626,7 @@ ; RV64SSCTR: .attribute 5, "rv64i2p1_sscsrind1p0_ssctr1p0" ; RV64SDEXT: .attribute 5, "rv64i2p1_sdext1p0" ; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0" -; RV64P: .attribute 5, "rv64i2p1_p0p20_zicsr2p0_zmmul1p0_zba1p0_zbb1p0" +; RV64P: .attribute 5, "rv64i2p1_p0p21_zicsr2p0_zmmul1p0_zba1p0_zbb1p0" ; RV64Y: .attribute 5, "rv64i2p1_y0p96" ; RV64ZIBI: .attribute 5, "rv64i2p1_zibi0p1" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 7d49558295cb3..241fac8f2bd17 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -510,8 +510,8 @@ .attribute arch, "rv32i_sdtrig1p0" # CHECK: attribute 5, "rv32i2p1_sdtrig1p0" -.attribute arch, "rv32i_p0p20" -# CHECK: attribute 5, "rv32i2p1_p0p20_zicsr2p0_zmmul1p0_zba1p0_zbb1p0" +.attribute arch, "rv32i_p0p21" +# CHECK: attribute 5, "rv32i2p1_p0p21_zicsr2p0_zmmul1p0_zba1p0_zbb1p0" -.attribute arch, "rv64i_p0p20" -# CHECK: attribute 5, "rv64i2p1_p0p20_zicsr2p0_zmmul1p0_zba1p0_zbb1p0" +.attribute arch, "rv64i_p0p21" +# CHECK: attribute 5, "rv64i2p1_p0p21_zicsr2p0_zmmul1p0_zba1p0_zbb1p0" diff --git a/llvm/test/MC/RISCV/rv32p-valid.s b/llvm/test/MC/RISCV/rv32p-valid.s index 9729fd6610147..70dae5b5cd81e 100644 --- a/llvm/test/MC/RISCV/rv32p-valid.s +++ b/llvm/test/MC/RISCV/rv32p-valid.s @@ -73,6 +73,18 @@ padd.hs t0, t1, t2 # CHECK-ASM-AND-OBJ: padd.bs ra, a1, a2 # CHECK-ASM: encoding: [0x9b,0xa0,0xc5,0x9c] padd.bs ra, a1, a2 +# CHECK-ASM-AND-OBJ: psshl.hs a3, a4, a5 +# CHECK-ASM: encoding: [0x9b,0x26,0xf7,0xa8] +psshl.hs a3, a4, a5 +# CHECK-ASM-AND-OBJ: sshl gp, a4, a5 +# CHECK-ASM: encoding: [0x9b,0x21,0xf7,0xaa] +sshl gp, a4, a5 +# CHECK-ASM-AND-OBJ: psshlr.hs a6, a7, a0 +# CHECK-ASM: encoding: [0x1b,0xa8,0xa8,0xb8] +psshlr.hs a6, a7, a0 +# CHECK-ASM-AND-OBJ: sshlr t1, a7, a0 +# CHECK-ASM: encoding: [0x1b,0xa3,0xa8,0xba] +sshlr t1, a7, a0 # CHECK-ASM-AND-OBJ: pssha.hs a3, a4, a5 # CHECK-ASM: encoding: [0x9b,0x26,0xf7,0xe8] pssha.hs a3, a4, a5 @@ -1065,6 +1077,18 @@ psshar.dhs a2, a4, t3 # CHECK-ASM-AND-OBJ: psshar.dws s0, t3, s0 # CHECK-ASM: encoding: [0x1b,0x64,0x8e,0x7a] psshar.dws s0, t3, s0 +# CHECK-ASM-AND-OBJ: psshl.dhs a0, s0, s2 +# CHECK-ASM: encoding: [0x1b,0x65,0x24,0x29] +psshl.dhs a0, s0, s2 +# CHECK-ASM-AND-OBJ: psshl.dws a0, t1, s2 +# CHECK-ASM: encoding: [0x1b,0x65,0x23,0x2b] +psshl.dws a0, t1, s2 +# CHECK-ASM-AND-OBJ: psshlr.dhs a2, a4, t3 +# CHECK-ASM: encoding: [0x1b,0x66,0xc7,0x39] +psshlr.dhs a2, a4, t3 +# CHECK-ASM-AND-OBJ: psshlr.dws s0, t3, s0 +# CHECK-ASM: encoding: [0x1b,0x64,0x8e,0x3a] +psshlr.dws s0, t3, s0 # CHECK-ASM-AND-OBJ: psrli.db t5, a2, 0 # CHECK-ASM: encoding: [0x1b,0xef,0x86,0x00] psrli.db t5, a2, 0 diff --git a/llvm/test/MC/RISCV/rv64p-valid.s b/llvm/test/MC/RISCV/rv64p-valid.s index 7d91057327117..755b0524b604e 100644 --- a/llvm/test/MC/RISCV/rv64p-valid.s +++ b/llvm/test/MC/RISCV/rv64p-valid.s @@ -100,6 +100,12 @@ padd.hs t1, a2, s0 # CHECK-ASM-AND-OBJ: padd.bs t3, t1, t3 # CHECK-ASM: encoding: [0x1b,0x2e,0xc3,0x9d] padd.bs t3, t1, t3 +# CHECK-ASM-AND-OBJ: psshl.hs a3, a4, a5 +# CHECK-ASM: encoding: [0x9b,0x26,0xf7,0xa8] +psshl.hs a3, a4, a5 +# CHECK-ASM-AND-OBJ: psshlr.hs a6, a7, a0 +# CHECK-ASM: encoding: [0x1b,0xa8,0xa8,0xb8] +psshlr.hs a6, a7, a0 # CHECK-ASM-AND-OBJ: pssha.hs s0, t1, a2 # CHECK-ASM: encoding: [0x1b,0x24,0xc3,0xe8] pssha.hs s0, t1, a2 @@ -112,12 +118,24 @@ psll.ws s0, t1, a0 # CHECK-ASM-AND-OBJ: padd.ws s2, a2, a0 # CHECK-ASM: encoding: [0x1b,0x29,0xa6,0x9a] padd.ws s2, a2, a0 +# CHECK-ASM-AND-OBJ: psshl.ws a3, a4, a5 +# CHECK-ASM: encoding: [0x9b,0x26,0xf7,0xaa] +psshl.ws a3, a4, a5 +# CHECK-ASM-AND-OBJ: psshlr.ws a6, a7, a0 +# CHECK-ASM: encoding: [0x1b,0xa8,0xa8,0xba] +psshlr.ws a6, a7, a0 # CHECK-ASM-AND-OBJ: pssha.ws a4, a2, t1 # CHECK-ASM: encoding: [0x1b,0x27,0x66,0xea] pssha.ws a4, a2, t1 # CHECK-ASM-AND-OBJ: psshar.ws a2, a0, a4 # CHECK-ASM: encoding: [0x1b,0x26,0xe5,0xfa] psshar.ws a2, a0, a4 +# CHECK-ASM-AND-OBJ: shl gp, a4, a5 +# CHECK-ASM: encoding: [0x9b,0x21,0xf7,0xae] +shl gp, a4, a5 +# CHECK-ASM-AND-OBJ: shlr t1, a7, a0 +# CHECK-ASM: encoding: [0x1b,0xa3,0xa8,0xbe] +shlr t1, a7, a0 # CHECK-ASM-AND-OBJ: sha a0, t5, t5 # CHECK-ASM: encoding: [0x1b,0x25,0xef,0xef] sha a0, t5, t5 @@ -358,6 +376,15 @@ pabdsumau.b s2, a2, a0 # CHECK-ASM-AND-OBJ: maccu.w01 a0, a0, t1 # CHECK-ASM: encoding: [0x3b,0x15,0x65,0xbe] maccu.w01 a0, a0, t1 +# CHECK-ASM-AND-OBJ: pnclipup.b a0, a1, a2 +# CHECK-ASM: encoding: [0x3b,0xa5,0xc5,0x80] +pnclipup.b a0, a1, a2 +# CHECK-ASM-AND-OBJ: pnclipup.h a3, a4, a5 +# CHECK-ASM: encoding: [0xbb,0x26,0xf7,0x82] +pnclipup.h a3, a4, a5 +# CHECK-ASM-AND-OBJ: pnclipup.w a6, a7, s0 +# CHECK-ASM: encoding: [0x3b,0xa8,0x88,0x86] +pnclipup.w a6, a7, s0 # CHECK-ASM-AND-OBJ: psh1add.h a2, a2, t3 # CHECK-ASM: encoding: [0x3b,0x26,0xc6,0xa1] psh1add.h a2, a2, t3 @@ -370,6 +397,15 @@ psh1add.w s2, t5, a2 # CHECK-ASM-AND-OBJ: pssh1sadd.w a4, t3, s0 # CHECK-ASM: encoding: [0x3b,0x27,0x8e,0xb2] pssh1sadd.w a4, t3, s0 +# CHECK-ASM-AND-OBJ: pnclipp.b s1, s2, s3 +# CHECK-ASM: encoding: [0xbb,0x24,0x39,0xc1] +pnclipp.b s1, s2, s3 +# CHECK-ASM-AND-OBJ: pnclipp.h s4, s5, s6 +# CHECK-ASM: encoding: [0x3b,0xaa,0x6a,0xc3] +pnclipp.h s4, s5, s6 +# CHECK-ASM-AND-OBJ: pnclipp.w s7, s8, s9 +# CHECK-ASM: encoding: [0xbb,0x2b,0x9c,0xc7] +pnclipp.w s7, s8, s9 # CHECK-ASM-AND-OBJ: unzip8p a4, t3, t1 # CHECK-ASM: encoding: [0x3b,0x27,0x6e,0xe0] unzip8p a4, t3, t1 diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 374db30891bab..5c7b8c665a9b2 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1372,7 +1372,7 @@ R"(All available -march extensions for RISC-V xwchc 2.2 Experimental extensions - p 0.20 + p 0.21 y 0.96 zibi 0.1 zicfilp 1.0 This is a long dummy description _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
