https://github.com/albertbolt1 updated https://github.com/llvm/llvm-project/pull/187516
>From bb2f0d341c45ebdc8ffa04005fd4fc25b17e163e Mon Sep 17 00:00:00 2001 From: albertbolt <[email protected]> Date: Thu, 19 Mar 2026 19:33:16 +0530 Subject: [PATCH 1/7] adding vector intrinsics for shift left --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 14 +- clang/test/CodeGen/AArch64/neon/intrinsics.c | 255 ++++++++++++++---- 2 files changed, 222 insertions(+), 47 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index d9d303cd07b92..cbc01b5dcfc51 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -212,6 +212,7 @@ static mlir::Value emitCommonNeonBuiltinExpr( cir::VectorType vTy = getNeonType(&cgf, neonType, loc, hasLegalHalfType, false, allowBFloatArgsAndRet); mlir::Type ty = vTy; + if (!ty) return nullptr; @@ -413,8 +414,17 @@ static mlir::Value emitCommonNeonBuiltinExpr( case NEON::BI__builtin_neon_vsha512h2q_u64: case NEON::BI__builtin_neon_vsha512su0q_u64: case NEON::BI__builtin_neon_vsha512su1q_u64: + cgf.cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AArch64 builtin call: ") + + ctx.BuiltinInfo.getName(builtinID)); + return mlir::Value{}; case NEON::BI__builtin_neon_vshl_n_v: - case NEON::BI__builtin_neon_vshlq_n_v: + case NEON::BI__builtin_neon_vshlq_n_v: { + auto rhsScalar = cgf.getBuilder().createIntCast(ops[1], vTy.getElementType()); + auto rhsVec = cir::VecSplatOp::create(cgf.getBuilder(),loc, vTy, rhsScalar); + auto lhsVec = cgf.getBuilder().createBitcast(ops[0], vTy); + return cgf.getBuilder().createShiftLeft(loc, lhsVec, rhsVec); + } case NEON::BI__builtin_neon_vshll_n_v: case NEON::BI__builtin_neon_vshrn_n_v: case NEON::BI__builtin_neon_vshr_n_v: @@ -1961,7 +1971,7 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, // defer to common code if it's been added to our special map. builtin = findARMVectorIntrinsicInMap(AArch64SIMDIntrinsicMap, builtinID, aarch64SIMDIntrinsicsProvenSorted); - + if (builtin) return emitCommonNeonBuiltinExpr( *this, builtin->BuiltinID, builtin->LLVMIntrinsic, diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index 6fd5bfdc98174..195844df0d813 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -936,51 +936,6 @@ uint32x4_t test_vabaq_u32(uint32x4_t v1, uint32x4_t v2, uint32x4_t v3) { // LLVM-NEXT: ret <4 x i32> [[ADD_I]] return vabaq_u32(v1, v2, v3); } -//===------------------------------------------------------===// -// 2.1.3.1.1. Vector Shift Left -//===------------------------------------------------------===// - -// ALL-LABEL: test_vshld_n_s64 -int64_t test_vshld_n_s64(int64_t a) { - // CIR: cir.shift(left, {{.*}}) - - // LLVM-SAME: i64 {{.*}} [[A:%.*]]) - // LLVM: [[SHL_N:%.*]] = shl i64 [[A]], 1 - // LLVM: ret i64 [[SHL_N]] - return (int64_t)vshld_n_s64(a, 1); -} - -// ALL-LABEL: test_vshld_n_u64 -int64_t test_vshld_n_u64(int64_t a) { - // CIR: cir.shift(left, {{.*}}) - - // LLVM-SAME: i64 {{.*}} [[A:%.*]]) - // LLVM: [[SHL_N:%.*]] = shl i64 [[A]], 1 - // LLVM: ret i64 [[SHL_N]] - return (int64_t)vshld_n_u64(a, 1); -} - -// LLVM-LABEL: test_vshld_s64 -// CIR-LABEL: vshld_s64 -int64_t test_vshld_s64(int64_t a,int64_t b) { - // CIR: cir.call_llvm_intrinsic "aarch64.neon.sshl" %{{.*}}, %{{.*}} : (!s64i, !s64i) -> !s64i - - // LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { - // LLVM: [[VSHLD_S64_I:%.*]] = call i64 @llvm.aarch64.neon.sshl.i64(i64 [[A]], i64 [[B]]) - // LLVM: ret i64 [[VSHLD_S64_I]] - return (int64_t)vshld_s64(a, b); -} - -// LLVM-LABEL: test_vshld_u64 -// CIR-LABEL: vshld_u64 -int64_t test_vshld_u64(int64_t a,int64_t b) { - // CIR: cir.call_llvm_intrinsic "aarch64.neon.ushl" %{{.*}}, %{{.*}} : (!u64i, !s64i) -> !u64i - - // LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { - // LLVM: [[VSHLD_S64_I:%.*]] = call i64 @llvm.aarch64.neon.ushl.i64(i64 [[A]], i64 [[B]]) - // LLVM: ret i64 [[VSHLD_S64_I]] - return (int64_t)vshld_u64(a, b); -} //===----------------------------------------------------------------------===// // 2.1.1.7. Maximum @@ -1518,3 +1473,213 @@ poly16x8_t test_vmull_high_p8(poly8x16_t a, poly8x16_t b) { // LLVM-NEXT: ret <8 x i16> [[VMULL_I_I]] return vmull_high_p8(a, b); } + +//===------------------------------------------------------===// +// 2.1.3.1.1. Vector Shift Left +//===------------------------------------------------------===// + +// ALL-LABEL: test_vshld_n_s64 +int64_t test_vshld_n_s64(int64_t a) { + // CIR: cir.shift(left, {{.*}}) + + // LLVM-SAME: i64 {{.*}} [[A:%.*]]) + // LLVM: [[SHL_N:%.*]] = shl i64 [[A]], 1 + // LLVM: ret i64 [[SHL_N]] + return (int64_t)vshld_n_s64(a, 1); +} + +// ALL-LABEL: test_vshld_n_u64 +int64_t test_vshld_n_u64(int64_t a) { + // CIR: cir.shift(left, {{.*}}) + + // LLVM-SAME: i64 {{.*}} [[A:%.*]]) + // LLVM: [[SHL_N:%.*]] = shl i64 [[A]], 1 + // LLVM: ret i64 [[SHL_N]] + return (int64_t)vshld_n_u64(a, 1); +} + +// LLVM-LABEL: test_vshld_s64 +// CIR-LABEL: vshld_s64 +int64_t test_vshld_s64(int64_t a,int64_t b) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.sshl" %{{.*}}, %{{.*}} : (!s64i, !s64i) -> !s64i + + // LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { + // LLVM: [[VSHLD_S64_I:%.*]] = call i64 @llvm.aarch64.neon.sshl.i64(i64 [[A]], i64 [[B]]) + // LLVM: ret i64 [[VSHLD_S64_I]] + return (int64_t)vshld_s64(a, b); +} + +// LLVM-LABEL: test_vshld_u64 +// CIR-LABEL: vshld_u64 +int64_t test_vshld_u64(int64_t a,int64_t b) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.ushl" %{{.*}}, %{{.*}} : (!u64i, !s64i) -> !u64i + + // LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { + // LLVM: [[VSHLD_S64_I:%.*]] = call i64 @llvm.aarch64.neon.ushl.i64(i64 [[A]], i64 [[B]]) + // LLVM: ret i64 [[VSHLD_S64_I]] + return (int64_t)vshld_u64(a, b); +} + +// ALL-LABEL: test_vshlq_n_s8 +int8x16_t test_vshlq_n_s8(int8x16_t a, int64_t b) { + // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<16 x !s8i>, %{{.*}} : !cir.vector<16 x !s8i>) -> !cir.vector<16 x !s8i> + + // LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { + // LLVM: [[SHL:%.*]] = shl <16 x i8> {{.*}}, splat (i8 1) + // LLVM: ret <16 x i8> [[SHL]] + return vshlq_n_s8(a, 1); +} + +// ALL-LABEL: test_vshlq_n_s16 +int16x8_t test_vshlq_n_s16(int16x8_t a, int64_t b) { + // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<8 x !s16i>, %{{.*}} : !cir.vector<8 x !s16i>) -> !cir.vector<8 x !s16i> + + // LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { + // LLVM: [[SHL:%.*]] = shl <8 x i16> {{.*}}, splat (i16 1) + // LLVM: ret <8 x i16> [[SHL]] + return vshlq_n_s16(a, 1); +} + +// ALL-LABEL: test_vshlq_n_s32 +int32x4_t test_vshlq_n_s32(int32x4_t a, int64_t b) { + // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<4 x !s32i>, %{{.*}} : !cir.vector<4 x !s32i>) -> !cir.vector<4 x !s32i> + + // LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { + // LLVM: [[SHL:%.*]] = shl <4 x i32> {{.*}}, splat (i32 1) + // LLVM: ret <4 x i32> [[SHL]] + return vshlq_n_s32(a, 1); +} + +// ALL-LABEL: test_vshlq_n_s64 +int64x2_t test_vshlq_n_s64(int64x2_t a, int64_t b) { + // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<2 x !s64i>, %{{.*}} : !cir.vector<2 x !s64i>) -> !cir.vector<2 x !s64i> + + // LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { + // LLVM: [[SHL:%.*]] = shl <2 x i64> {{.*}}, splat (i64 1) + // LLVM: ret <2 x i64> [[SHL]] + return vshlq_n_s64(a, 1); +} + +// ALL-LABEL: test_vshlq_n_u8 +uint8x16_t test_vshlq_n_u8(uint8x16_t a, int64_t b) { + // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<16 x !u8i>, %{{.*}} : !cir.vector<16 x !u8i>) -> !cir.vector<16 x !u8i> + + // LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { + // LLVM: [[SHL:%.*]] = shl <16 x i8> {{.*}}, splat (i8 1) + // LLVM: ret <16 x i8> [[SHL]] + return vshlq_n_u8(a, 1); +} + +// ALL-LABEL: test_vshlq_n_u16 +uint16x8_t test_vshlq_n_u16(uint16x8_t a, int64_t b) { + // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<8 x !u16i>, %{{.*}} : !cir.vector<8 x !u16i>) -> !cir.vector<8 x !u16i> + + // LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { + // LLVM: [[SHL:%.*]] = shl <8 x i16> {{.*}}, splat (i16 1) + // LLVM: ret <8 x i16> [[SHL]] + return vshlq_n_u16(a, 1); +} + +// ALL-LABEL: test_vshlq_n_u32 +uint32x4_t test_vshlq_n_u32(uint32x4_t a, int64_t b) { + // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<4 x !u32i>, %{{.*}} : !cir.vector<4 x !u32i>) -> !cir.vector<4 x !u32i> + + // LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { + // LLVM: [[SHL:%.*]] = shl <4 x i32> {{.*}}, splat (i32 1) + // LLVM: ret <4 x i32> [[SHL]] + return vshlq_n_u32(a, 1); +} + +// ALL-LABEL: test_vshlq_n_u64 +uint64x2_t test_vshlq_n_u64(uint64x2_t a, int64_t b) { + // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<2 x !u64i>, %{{.*}} : !cir.vector<2 x !u64i>) -> !cir.vector<2 x !u64i> + + // LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { + // LLVM: [[SHL:%.*]] = shl <2 x i64> {{.*}}, splat (i64 1) + // LLVM: ret <2 x i64> [[SHL]] + return vshlq_n_u64(a, 1); +} + +// ALL-LABEL: test_vshl_n_s8 +int8x8_t test_vshl_n_s8(int8x8_t a, int64_t b) { + // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<8 x !s8i>, %{{.*}} : !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s8i> + + // LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { + // LLVM: [[SHL:%.*]] = shl <8 x i8> {{.*}}, splat (i8 1) + // LLVM: ret <8 x i8> [[SHL]] + return vshl_n_s8(a, 1); +} + +// ALL-LABEL: test_vshl_n_s16 +int16x4_t test_vshl_n_s16(int16x4_t a, int64_t b) { + // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<4 x !s16i>, %{{.*}} : !cir.vector<4 x !s16i>) -> !cir.vector<4 x !s16i> + + // LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { + // LLVM: [[SHL:%.*]] = shl <4 x i16> {{.*}}, splat (i16 1) + // LLVM: ret <4 x i16> [[SHL]] + return vshl_n_s16(a, 1); +} + +// ALL-LABEL: test_vshl_n_s32 +int32x2_t test_vshl_n_s32(int32x2_t a, int64_t b) { + // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<2 x !s32i>, %{{.*}} : !cir.vector<2 x !s32i>) -> !cir.vector<2 x !s32i> + + // LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { + // LLVM: [[SHL:%.*]] = shl <2 x i32> {{.*}}, splat (i32 1) + // LLVM: ret <2 x i32> [[SHL]] + return vshl_n_s32(a, 1); +} + +// ALL-LABEL: test_vshl_n_s64 +int64x1_t test_vshl_n_s64(int64x1_t a, int64_t b) { + // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<1 x !s64i>, %{{.*}} : !cir.vector<1 x !s64i>) -> !cir.vector<1 x !s64i> + + // LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { + // LLVM: [[SHL:%.*]] = shl <1 x i64> {{.*}}, splat (i64 1) + // LLVM: ret <1 x i64> [[SHL]] + return vshl_n_s64(a, 1); +} + +// ALL-LABEL: test_vshl_n_u8 +uint8x8_t test_vshl_n_u8(uint8x8_t a, int64_t b) { + // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<8 x !u8i>, %{{.*}} : !cir.vector<8 x !u8i>) -> !cir.vector<8 x !u8i> + + // LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { + // LLVM: [[SHL:%.*]] = shl <8 x i8> {{.*}}, splat (i8 1) + // LLVM: ret <8 x i8> [[SHL]] + return vshl_n_u8(a, 1); +} + +// ALL-LABEL: test_vshl_n_u16 +uint16x4_t test_vshl_n_u16(uint16x4_t a, int64_t b) { + // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<4 x !u16i>, %{{.*}} : !cir.vector<4 x !u16i>) -> !cir.vector<4 x !u16i> + + + // LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { + // LLVM: [[SHL:%.*]] = shl <4 x i16> {{.*}}, splat (i16 1) + // LLVM: ret <4 x i16> [[SHL]] + return vshl_n_u16(a, 1); +} + +// ALL-LABEL: test_vshl_n_u32 +uint32x2_t test_vshl_n_u32(uint32x2_t a, int64_t b) { + // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<2 x !u32i>, %{{.*}} : !cir.vector<2 x !u32i>) -> !cir.vector<2 x !u32i> + + // LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { + // LLVM: [[SHL:%.*]] = shl <2 x i32> {{.*}}, splat (i32 1) + // LLVM: ret <2 x i32> [[SHL]] + return vshl_n_u32(a, 1); +} + +// ALL-LABEL: test_vshl_n_u64 +uint64x1_t test_vshl_n_u64(uint64x1_t a, int64_t b) { + // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<1 x !u64i>, %{{.*}} : !cir.vector<1 x !u64i>) -> !cir.vector<1 x !u64i> + + // LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { + // LLVM: [[SHL:%.*]] = shl <1 x i64> {{.*}}, splat (i64 1) + // LLVM: ret <1 x i64> [[SHL]] + return vshl_n_u64(a, 1); +} + + + >From e8c8a20f7c4c7f58c40169ef0c3002e7bea49e6a Mon Sep 17 00:00:00 2001 From: albertbolt <[email protected]> Date: Sat, 21 Mar 2026 11:00:47 +0530 Subject: [PATCH 2/7] used code from incubator, ported test cases --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 37 +++- clang/test/CodeGen/AArch64/neon-intrinsics.c | 208 +++--------------- clang/test/CodeGen/AArch64/neon/intrinsics.c | 186 +++++++++------- 3 files changed, 167 insertions(+), 264 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index cbc01b5dcfc51..a84d9321c7700 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -180,6 +180,35 @@ static mlir::Value emitNeonSplat(CIRGenBuilderTy &builder, mlir::Location loc, int64_t laneCst = getIntValueFromConstOp(lane); llvm::SmallVector<int64_t, 4> shuffleMask(resEltCnt, laneCst); return builder.createVecShuffle(loc, v, shuffleMask); + } + +/// Build a constant shift amount vector of `vecTy` to shift a vector +/// Here `shitfVal` is a constant integer that will be splated into a +/// a const vector of `vecTy` which is the return of this function +static mlir::Value emitNeonShiftVector(CIRGenBuilderTy &builder, + mlir::Value shiftVal, + cir::VectorType vecTy, + mlir::Location loc, bool neg) { + int shiftAmt = getIntValueFromConstOp(shiftVal); + if (neg) + shiftAmt = -shiftAmt; + llvm::SmallVector<mlir::Attribute> vecAttr{ + vecTy.getSize(), + // ConstVectorAttr requires cir::IntAttr + cir::IntAttr::get(vecTy.getElementType(), shiftAmt)}; + cir::ConstVectorAttr constVecAttr = cir::ConstVectorAttr::get( + vecTy, mlir::ArrayAttr::get(builder.getContext(), vecAttr)); + return cir::ConstantOp::create(builder, loc, constVecAttr); +} + +static mlir::Value +emitCommonNeonShift(CIRGenBuilderTy &builder, mlir::Location loc, + cir::VectorType resTy, mlir::Value shifTgt, + mlir::Value shiftAmt, bool shiftLeft, bool negAmt = false) { + shiftAmt = emitNeonShiftVector(builder, shiftAmt, resTy, loc, negAmt); + return cir::ShiftOp::create(builder, loc, resTy, + builder.createBitcast(shifTgt, resTy), shiftAmt, + shiftLeft); } static mlir::Value emitCommonNeonBuiltinExpr( @@ -419,12 +448,8 @@ static mlir::Value emitCommonNeonBuiltinExpr( ctx.BuiltinInfo.getName(builtinID)); return mlir::Value{}; case NEON::BI__builtin_neon_vshl_n_v: - case NEON::BI__builtin_neon_vshlq_n_v: { - auto rhsScalar = cgf.getBuilder().createIntCast(ops[1], vTy.getElementType()); - auto rhsVec = cir::VecSplatOp::create(cgf.getBuilder(),loc, vTy, rhsScalar); - auto lhsVec = cgf.getBuilder().createBitcast(ops[0], vTy); - return cgf.getBuilder().createShiftLeft(loc, lhsVec, rhsVec); - } + case NEON::BI__builtin_neon_vshlq_n_v: + return emitCommonNeonShift(cgf.getBuilder(), loc, vTy, ops[0], ops[1], true); case NEON::BI__builtin_neon_vshll_n_v: case NEON::BI__builtin_neon_vshrn_n_v: case NEON::BI__builtin_neon_vshr_n_v: diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index 80bb22cc43c78..8e76e296798cf 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -6342,166 +6342,6 @@ float64x2_t test_vmulxq_f64(float64x2_t a, float64x2_t b) { return vmulxq_f64(a, b); } -// CHECK-LABEL: define dso_local <8 x i8> @test_vshl_n_s8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <8 x i8> [[A]], splat (i8 3) -// CHECK-NEXT: ret <8 x i8> [[VSHL_N]] -// -int8x8_t test_vshl_n_s8(int8x8_t a) { - return vshl_n_s8(a, 3); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vshl_n_s16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <4 x i16> [[TMP1]], splat (i16 3) -// CHECK-NEXT: ret <4 x i16> [[VSHL_N]] -// -int16x4_t test_vshl_n_s16(int16x4_t a) { - return vshl_n_s16(a, 3); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vshl_n_s32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <2 x i32> [[TMP1]], splat (i32 3) -// CHECK-NEXT: ret <2 x i32> [[VSHL_N]] -// -int32x2_t test_vshl_n_s32(int32x2_t a) { - return vshl_n_s32(a, 3); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vshlq_n_s8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <16 x i8> [[A]], splat (i8 3) -// CHECK-NEXT: ret <16 x i8> [[VSHL_N]] -// -int8x16_t test_vshlq_n_s8(int8x16_t a) { - return vshlq_n_s8(a, 3); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vshlq_n_s16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <8 x i16> [[TMP1]], splat (i16 3) -// CHECK-NEXT: ret <8 x i16> [[VSHL_N]] -// -int16x8_t test_vshlq_n_s16(int16x8_t a) { - return vshlq_n_s16(a, 3); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vshlq_n_s32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <4 x i32> [[TMP1]], splat (i32 3) -// CHECK-NEXT: ret <4 x i32> [[VSHL_N]] -// -int32x4_t test_vshlq_n_s32(int32x4_t a) { - return vshlq_n_s32(a, 3); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vshlq_n_s64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <2 x i64> [[TMP1]], splat (i64 3) -// CHECK-NEXT: ret <2 x i64> [[VSHL_N]] -// -int64x2_t test_vshlq_n_s64(int64x2_t a) { - return vshlq_n_s64(a, 3); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vshl_n_u8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <8 x i8> [[A]], splat (i8 3) -// CHECK-NEXT: ret <8 x i8> [[VSHL_N]] -// -uint8x8_t test_vshl_n_u8(uint8x8_t a) { - return vshl_n_u8(a, 3); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vshl_n_u16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <4 x i16> [[TMP1]], splat (i16 3) -// CHECK-NEXT: ret <4 x i16> [[VSHL_N]] -// -uint16x4_t test_vshl_n_u16(uint16x4_t a) { - return vshl_n_u16(a, 3); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vshl_n_u32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <2 x i32> [[TMP1]], splat (i32 3) -// CHECK-NEXT: ret <2 x i32> [[VSHL_N]] -// -uint32x2_t test_vshl_n_u32(uint32x2_t a) { - return vshl_n_u32(a, 3); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vshlq_n_u8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <16 x i8> [[A]], splat (i8 3) -// CHECK-NEXT: ret <16 x i8> [[VSHL_N]] -// -uint8x16_t test_vshlq_n_u8(uint8x16_t a) { - return vshlq_n_u8(a, 3); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vshlq_n_u16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <8 x i16> [[TMP1]], splat (i16 3) -// CHECK-NEXT: ret <8 x i16> [[VSHL_N]] -// -uint16x8_t test_vshlq_n_u16(uint16x8_t a) { - return vshlq_n_u16(a, 3); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vshlq_n_u32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <4 x i32> [[TMP1]], splat (i32 3) -// CHECK-NEXT: ret <4 x i32> [[VSHL_N]] -// -uint32x4_t test_vshlq_n_u32(uint32x4_t a) { - return vshlq_n_u32(a, 3); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vshlq_n_u64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <2 x i64> [[TMP1]], splat (i64 3) -// CHECK-NEXT: ret <2 x i64> [[VSHL_N]] -// -uint64x2_t test_vshlq_n_u64(uint64x2_t a) { - return vshlq_n_u64(a, 3); -} - // CHECK-LABEL: define dso_local <8 x i8> @test_vshr_n_s8( // CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -11598,6 +11438,26 @@ uint64_t test_vqsubd_u64(uint64_t a, uint64_t b) { return vqsubd_u64(a, b); } +// CHECK-LABEL: define dso_local i64 @test_vshld_s64( +// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[VSHLD_S64_I:%.*]] = call i64 @llvm.aarch64.neon.sshl.i64(i64 [[A]], i64 [[B]]) +// CHECK-NEXT: ret i64 [[VSHLD_S64_I]] +// +int64_t test_vshld_s64(int64_t a, int64_t b) { + return vshld_s64(a, b); +} + +// CHECK-LABEL: define dso_local i64 @test_vshld_u64( +// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[VSHLD_U64_I:%.*]] = call i64 @llvm.aarch64.neon.ushl.i64(i64 [[A]], i64 [[B]]) +// CHECK-NEXT: ret i64 [[VSHLD_U64_I]] +// +uint64_t test_vshld_u64(uint64_t a, int64_t b) { + return vshld_u64(a, b); +} + // CHECK-LABEL: define dso_local i8 @test_vqshlb_s8( // CHECK-SAME: i8 noundef [[A:%.*]], i8 noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -17413,28 +17273,24 @@ uint64x1_t test_vrsra_n_u64(uint64x1_t a, uint64x1_t b) { return vrsra_n_u64(a, b, 1); } -// CHECK-LABEL: define dso_local <1 x i64> @test_vshl_n_s64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-LABEL: define dso_local i64 @test_vshld_n_s64( +// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <1 x i64> [[TMP1]], splat (i64 1) -// CHECK-NEXT: ret <1 x i64> [[VSHL_N]] +// CHECK-NEXT: [[SHLD_N:%.*]] = shl i64 [[A]], 1 +// CHECK-NEXT: ret i64 [[SHLD_N]] // -int64x1_t test_vshl_n_s64(int64x1_t a) { - return vshl_n_s64(a, 1); +int64_t test_vshld_n_s64(int64_t a) { + return (int64_t)vshld_n_s64(a, 1); } -// CHECK-LABEL: define dso_local <1 x i64> @test_vshl_n_u64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-LABEL: define dso_local i64 @test_vshld_n_u64( +// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <1 x i64> [[TMP1]], splat (i64 1) -// CHECK-NEXT: ret <1 x i64> [[VSHL_N]] +// CHECK-NEXT: [[SHLD_N:%.*]] = shl i64 [[A]], 63 +// CHECK-NEXT: ret i64 [[SHLD_N]] // -uint64x1_t test_vshl_n_u64(uint64x1_t a) { - return vshl_n_u64(a, 1); +uint64_t test_vshld_n_u64(uint64_t a) { + return (uint64_t)vshld_n_u64(a, 63); } // CHECK-LABEL: define dso_local i8 @test_vqshlb_n_s8( diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index 195844df0d813..e54fc494bd32c 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -1521,165 +1521,187 @@ int64_t test_vshld_u64(int64_t a,int64_t b) { } // ALL-LABEL: test_vshlq_n_s8 -int8x16_t test_vshlq_n_s8(int8x16_t a, int64_t b) { - // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<16 x !s8i>, %{{.*}} : !cir.vector<16 x !s8i>) -> !cir.vector<16 x !s8i> +int8x16_t test_vshlq_n_s8(int8x16_t a) { +// CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<16 x !s8i>, %{{.*}} : !cir.vector<16 x !s8i>) -> !cir.vector<16 x !s8i> - // LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { - // LLVM: [[SHL:%.*]] = shl <16 x i8> {{.*}}, splat (i8 1) - // LLVM: ret <16 x i8> [[SHL]] - return vshlq_n_s8(a, 1); +// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]]) #[[ATTR0]] { +// LLVM: [[VSHL_N:%.*]] = shl <16 x i8> [[A]], splat (i8 3) +// LLVM: ret <16 x i8> [[VSHL_N]] +// + return vshlq_n_s8(a, 3); } // ALL-LABEL: test_vshlq_n_s16 -int16x8_t test_vshlq_n_s16(int16x8_t a, int64_t b) { +int16x8_t test_vshlq_n_s16(int16x8_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<8 x !s16i>, %{{.*}} : !cir.vector<8 x !s16i>) -> !cir.vector<8 x !s16i> - // LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { - // LLVM: [[SHL:%.*]] = shl <8 x i16> {{.*}}, splat (i16 1) - // LLVM: ret <8 x i16> [[SHL]] - return vshlq_n_s16(a, 1); +// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]]) #[[ATTR0]] { +// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> +// LLVM-NEXT: [[VSHL_N:%.*]] = shl <8 x i16> [[TMP1]], splat (i16 3) +// LLVM: ret <8 x i16> [[VSHL_N]] + return vshlq_n_s16(a, 3); } // ALL-LABEL: test_vshlq_n_s32 -int32x4_t test_vshlq_n_s32(int32x4_t a, int64_t b) { +int32x4_t test_vshlq_n_s32(int32x4_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<4 x !s32i>, %{{.*}} : !cir.vector<4 x !s32i>) -> !cir.vector<4 x !s32i> - // LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { - // LLVM: [[SHL:%.*]] = shl <4 x i32> {{.*}}, splat (i32 1) - // LLVM: ret <4 x i32> [[SHL]] - return vshlq_n_s32(a, 1); +// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]]) #[[ATTR0]] { +// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> +// LLVM-NEXT: [[VSHL_N:%.*]] = shl <4 x i32> [[TMP1]], splat (i32 3) +// LLVM: ret <4 x i32> [[VSHL_N]] + return vshlq_n_s32(a, 3); } // ALL-LABEL: test_vshlq_n_s64 -int64x2_t test_vshlq_n_s64(int64x2_t a, int64_t b) { +int64x2_t test_vshlq_n_s64(int64x2_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<2 x !s64i>, %{{.*}} : !cir.vector<2 x !s64i>) -> !cir.vector<2 x !s64i> - // LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { - // LLVM: [[SHL:%.*]] = shl <2 x i64> {{.*}}, splat (i64 1) - // LLVM: ret <2 x i64> [[SHL]] - return vshlq_n_s64(a, 1); +// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]]) #[[ATTR0]] { +// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> +// LLVM-NEXT: [[VSHL_N:%.*]] = shl <2 x i64> [[TMP1]], splat (i64 3) +// LLVM: ret <2 x i64> [[VSHL_N]] + return vshlq_n_s64(a, 3); } // ALL-LABEL: test_vshlq_n_u8 -uint8x16_t test_vshlq_n_u8(uint8x16_t a, int64_t b) { +uint8x16_t test_vshlq_n_u8(uint8x16_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<16 x !u8i>, %{{.*}} : !cir.vector<16 x !u8i>) -> !cir.vector<16 x !u8i> - // LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { - // LLVM: [[SHL:%.*]] = shl <16 x i8> {{.*}}, splat (i8 1) - // LLVM: ret <16 x i8> [[SHL]] - return vshlq_n_u8(a, 1); +// LLVM-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM: [[VSHL_N:%.*]] = shl <16 x i8> [[A]], splat (i8 3) +// LLVM: ret <16 x i8> [[VSHL_N]] + return vshlq_n_u8(a, 3); } // ALL-LABEL: test_vshlq_n_u16 -uint16x8_t test_vshlq_n_u16(uint16x8_t a, int64_t b) { +uint16x8_t test_vshlq_n_u16(uint16x8_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<8 x !u16i>, %{{.*}} : !cir.vector<8 x !u16i>) -> !cir.vector<8 x !u16i> - // LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { - // LLVM: [[SHL:%.*]] = shl <8 x i16> {{.*}}, splat (i16 1) - // LLVM: ret <8 x i16> [[SHL]] - return vshlq_n_u16(a, 1); +// LLVM-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> +// LLVM-NEXT: [[VSHL_N:%.*]] = shl <8 x i16> [[TMP1]], splat (i16 3) +// LLVM: ret <8 x i16> [[VSHL_N]] + return vshlq_n_u16(a, 3); } // ALL-LABEL: test_vshlq_n_u32 -uint32x4_t test_vshlq_n_u32(uint32x4_t a, int64_t b) { +uint32x4_t test_vshlq_n_u32(uint32x4_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<4 x !u32i>, %{{.*}} : !cir.vector<4 x !u32i>) -> !cir.vector<4 x !u32i> - // LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { - // LLVM: [[SHL:%.*]] = shl <4 x i32> {{.*}}, splat (i32 1) - // LLVM: ret <4 x i32> [[SHL]] - return vshlq_n_u32(a, 1); +// LLVM-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> +// LLVM-NEXT: [[VSHL_N:%.*]] = shl <4 x i32> [[TMP1]], splat (i32 3) +// LLVM: ret <4 x i32> [[VSHL_N]] + return vshlq_n_u32(a, 3); } // ALL-LABEL: test_vshlq_n_u64 -uint64x2_t test_vshlq_n_u64(uint64x2_t a, int64_t b) { +uint64x2_t test_vshlq_n_u64(uint64x2_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<2 x !u64i>, %{{.*}} : !cir.vector<2 x !u64i>) -> !cir.vector<2 x !u64i> - // LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { - // LLVM: [[SHL:%.*]] = shl <2 x i64> {{.*}}, splat (i64 1) - // LLVM: ret <2 x i64> [[SHL]] - return vshlq_n_u64(a, 1); +// LLVM-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> +// LLVM-NEXT: [[VSHL_N:%.*]] = shl <2 x i64> [[TMP1]], splat (i64 3) +// LLVM: ret <2 x i64> [[VSHL_N]] + return vshlq_n_u64(a, 3); } // ALL-LABEL: test_vshl_n_s8 -int8x8_t test_vshl_n_s8(int8x8_t a, int64_t b) { +int8x8_t test_vshl_n_s8(int8x8_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<8 x !s8i>, %{{.*}} : !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s8i> - // LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { - // LLVM: [[SHL:%.*]] = shl <8 x i8> {{.*}}, splat (i8 1) - // LLVM: ret <8 x i8> [[SHL]] - return vshl_n_s8(a, 1); +// LLVM-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM: [[VSHL_N:%.*]] = shl <8 x i8> [[A]], splat (i8 3) +// LLVM: ret <8 x i8> [[VSHL_N]] + return vshl_n_s8(a, 3); } // ALL-LABEL: test_vshl_n_s16 -int16x4_t test_vshl_n_s16(int16x4_t a, int64_t b) { +int16x4_t test_vshl_n_s16(int16x4_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<4 x !s16i>, %{{.*}} : !cir.vector<4 x !s16i>) -> !cir.vector<4 x !s16i> - // LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { - // LLVM: [[SHL:%.*]] = shl <4 x i16> {{.*}}, splat (i16 1) - // LLVM: ret <4 x i16> [[SHL]] - return vshl_n_s16(a, 1); +// LLVM-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM-NEXT: [[VSHL_N:%.*]] = shl <4 x i16> [[TMP1]], splat (i16 3) +// LLVM: ret <4 x i16> [[VSHL_N]] + return vshl_n_s16(a, 3); } // ALL-LABEL: test_vshl_n_s32 -int32x2_t test_vshl_n_s32(int32x2_t a, int64_t b) { +int32x2_t test_vshl_n_s32(int32x2_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<2 x !s32i>, %{{.*}} : !cir.vector<2 x !s32i>) -> !cir.vector<2 x !s32i> - // LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { - // LLVM: [[SHL:%.*]] = shl <2 x i32> {{.*}}, splat (i32 1) - // LLVM: ret <2 x i32> [[SHL]] - return vshl_n_s32(a, 1); +// LLVM-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM-NEXT: [[VSHL_N:%.*]] = shl <2 x i32> [[TMP1]], splat (i32 3) +// LLVM: ret <2 x i32> [[VSHL_N]] + return vshl_n_s32(a, 3); } // ALL-LABEL: test_vshl_n_s64 -int64x1_t test_vshl_n_s64(int64x1_t a, int64_t b) { +int64x1_t test_vshl_n_s64(int64x1_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<1 x !s64i>, %{{.*}} : !cir.vector<1 x !s64i>) -> !cir.vector<1 x !s64i> - // LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { - // LLVM: [[SHL:%.*]] = shl <1 x i64> {{.*}}, splat (i64 1) - // LLVM: ret <1 x i64> [[SHL]] +// LLVM-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> +// LLVM-NEXT: [[VSHL_N:%.*]] = shl <1 x i64> [[TMP1]], splat (i64 1) +// LLVM: ret <1 x i64> [[VSHL_N]] return vshl_n_s64(a, 1); } // ALL-LABEL: test_vshl_n_u8 -uint8x8_t test_vshl_n_u8(uint8x8_t a, int64_t b) { +uint8x8_t test_vshl_n_u8(uint8x8_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<8 x !u8i>, %{{.*}} : !cir.vector<8 x !u8i>) -> !cir.vector<8 x !u8i> - // LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { - // LLVM: [[SHL:%.*]] = shl <8 x i8> {{.*}}, splat (i8 1) - // LLVM: ret <8 x i8> [[SHL]] - return vshl_n_u8(a, 1); +// LLVM-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM: [[VSHL_N:%.*]] = shl <8 x i8> [[A]], splat (i8 3) +// LLVM: ret <8 x i8> [[VSHL_N]] + return vshl_n_u8(a, 3); } // ALL-LABEL: test_vshl_n_u16 -uint16x4_t test_vshl_n_u16(uint16x4_t a, int64_t b) { +uint16x4_t test_vshl_n_u16(uint16x4_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<4 x !u16i>, %{{.*}} : !cir.vector<4 x !u16i>) -> !cir.vector<4 x !u16i> - - // LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { - // LLVM: [[SHL:%.*]] = shl <4 x i16> {{.*}}, splat (i16 1) - // LLVM: ret <4 x i16> [[SHL]] - return vshl_n_u16(a, 1); +// LLVM-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM-NEXT: [[VSHL_N:%.*]] = shl <4 x i16> [[TMP1]], splat (i16 3) +// LLVM: ret <4 x i16> [[VSHL_N]] + return vshl_n_u16(a, 3); } // ALL-LABEL: test_vshl_n_u32 -uint32x2_t test_vshl_n_u32(uint32x2_t a, int64_t b) { +uint32x2_t test_vshl_n_u32(uint32x2_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<2 x !u32i>, %{{.*}} : !cir.vector<2 x !u32i>) -> !cir.vector<2 x !u32i> - // LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { - // LLVM: [[SHL:%.*]] = shl <2 x i32> {{.*}}, splat (i32 1) - // LLVM: ret <2 x i32> [[SHL]] - return vshl_n_u32(a, 1); +// LLVM-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM-NEXT: [[VSHL_N:%.*]] = shl <2 x i32> [[TMP1]], splat (i32 3) +// LLVM: ret <2 x i32> [[VSHL_N]] + return vshl_n_u32(a, 3); } // ALL-LABEL: test_vshl_n_u64 -uint64x1_t test_vshl_n_u64(uint64x1_t a, int64_t b) { +uint64x1_t test_vshl_n_u64(uint64x1_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<1 x !u64i>, %{{.*}} : !cir.vector<1 x !u64i>) -> !cir.vector<1 x !u64i> - // LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) #[[ATTR0:[0-9]+]] { - // LLVM: [[SHL:%.*]] = shl <1 x i64> {{.*}}, splat (i64 1) - // LLVM: ret <1 x i64> [[SHL]] +// LLVM-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> +// LLVM-NEXT: [[VSHL_N:%.*]] = shl <1 x i64> [[TMP1]], splat (i64 1) +// LLVM: ret <1 x i64> [[VSHL_N]] return vshl_n_u64(a, 1); } - - >From 487694eb1864defa24adca7531a0199ab45f6432 Mon Sep 17 00:00:00 2001 From: albertbolt <[email protected]> Date: Sat, 21 Mar 2026 11:09:25 +0530 Subject: [PATCH 3/7] cleaning --- clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index a84d9321c7700..f5ee4379d3918 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -449,7 +449,8 @@ static mlir::Value emitCommonNeonBuiltinExpr( return mlir::Value{}; case NEON::BI__builtin_neon_vshl_n_v: case NEON::BI__builtin_neon_vshlq_n_v: - return emitCommonNeonShift(cgf.getBuilder(), loc, vTy, ops[0], ops[1], true); + return emitCommonNeonShift(cgf.getBuilder(), loc, vTy, ops[0], ops[1], + true); case NEON::BI__builtin_neon_vshll_n_v: case NEON::BI__builtin_neon_vshrn_n_v: case NEON::BI__builtin_neon_vshr_n_v: >From 1ca9620c876758945011cce2fd9f59a8c12ce42d Mon Sep 17 00:00:00 2001 From: albertbolt <[email protected]> Date: Sat, 21 Mar 2026 11:13:34 +0530 Subject: [PATCH 4/7] cleaning --- clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index f5ee4379d3918..d6b9a22080885 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -1997,7 +1997,6 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, // defer to common code if it's been added to our special map. builtin = findARMVectorIntrinsicInMap(AArch64SIMDIntrinsicMap, builtinID, aarch64SIMDIntrinsicsProvenSorted); - if (builtin) return emitCommonNeonBuiltinExpr( *this, builtin->BuiltinID, builtin->LLVMIntrinsic, >From 6610c056d6031d7bee458bad8e47f3517fae3fe1 Mon Sep 17 00:00:00 2001 From: albertbolt <[email protected]> Date: Sat, 21 Mar 2026 12:58:55 +0530 Subject: [PATCH 5/7] restored neon-intrinsics files --- clang/test/CodeGen/AArch64/neon-intrinsics.c | 208 ++++++++++++++++--- 1 file changed, 176 insertions(+), 32 deletions(-) diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index 8e76e296798cf..80bb22cc43c78 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -6342,6 +6342,166 @@ float64x2_t test_vmulxq_f64(float64x2_t a, float64x2_t b) { return vmulxq_f64(a, b); } +// CHECK-LABEL: define dso_local <8 x i8> @test_vshl_n_s8( +// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[VSHL_N:%.*]] = shl <8 x i8> [[A]], splat (i8 3) +// CHECK-NEXT: ret <8 x i8> [[VSHL_N]] +// +int8x8_t test_vshl_n_s8(int8x8_t a) { + return vshl_n_s8(a, 3); +} + +// CHECK-LABEL: define dso_local <4 x i16> @test_vshl_n_s16( +// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// CHECK-NEXT: [[VSHL_N:%.*]] = shl <4 x i16> [[TMP1]], splat (i16 3) +// CHECK-NEXT: ret <4 x i16> [[VSHL_N]] +// +int16x4_t test_vshl_n_s16(int16x4_t a) { + return vshl_n_s16(a, 3); +} + +// CHECK-LABEL: define dso_local <2 x i32> @test_vshl_n_s32( +// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// CHECK-NEXT: [[VSHL_N:%.*]] = shl <2 x i32> [[TMP1]], splat (i32 3) +// CHECK-NEXT: ret <2 x i32> [[VSHL_N]] +// +int32x2_t test_vshl_n_s32(int32x2_t a) { + return vshl_n_s32(a, 3); +} + +// CHECK-LABEL: define dso_local <16 x i8> @test_vshlq_n_s8( +// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[VSHL_N:%.*]] = shl <16 x i8> [[A]], splat (i8 3) +// CHECK-NEXT: ret <16 x i8> [[VSHL_N]] +// +int8x16_t test_vshlq_n_s8(int8x16_t a) { + return vshlq_n_s8(a, 3); +} + +// CHECK-LABEL: define dso_local <8 x i16> @test_vshlq_n_s16( +// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> +// CHECK-NEXT: [[VSHL_N:%.*]] = shl <8 x i16> [[TMP1]], splat (i16 3) +// CHECK-NEXT: ret <8 x i16> [[VSHL_N]] +// +int16x8_t test_vshlq_n_s16(int16x8_t a) { + return vshlq_n_s16(a, 3); +} + +// CHECK-LABEL: define dso_local <4 x i32> @test_vshlq_n_s32( +// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> +// CHECK-NEXT: [[VSHL_N:%.*]] = shl <4 x i32> [[TMP1]], splat (i32 3) +// CHECK-NEXT: ret <4 x i32> [[VSHL_N]] +// +int32x4_t test_vshlq_n_s32(int32x4_t a) { + return vshlq_n_s32(a, 3); +} + +// CHECK-LABEL: define dso_local <2 x i64> @test_vshlq_n_s64( +// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> +// CHECK-NEXT: [[VSHL_N:%.*]] = shl <2 x i64> [[TMP1]], splat (i64 3) +// CHECK-NEXT: ret <2 x i64> [[VSHL_N]] +// +int64x2_t test_vshlq_n_s64(int64x2_t a) { + return vshlq_n_s64(a, 3); +} + +// CHECK-LABEL: define dso_local <8 x i8> @test_vshl_n_u8( +// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[VSHL_N:%.*]] = shl <8 x i8> [[A]], splat (i8 3) +// CHECK-NEXT: ret <8 x i8> [[VSHL_N]] +// +uint8x8_t test_vshl_n_u8(uint8x8_t a) { + return vshl_n_u8(a, 3); +} + +// CHECK-LABEL: define dso_local <4 x i16> @test_vshl_n_u16( +// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// CHECK-NEXT: [[VSHL_N:%.*]] = shl <4 x i16> [[TMP1]], splat (i16 3) +// CHECK-NEXT: ret <4 x i16> [[VSHL_N]] +// +uint16x4_t test_vshl_n_u16(uint16x4_t a) { + return vshl_n_u16(a, 3); +} + +// CHECK-LABEL: define dso_local <2 x i32> @test_vshl_n_u32( +// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// CHECK-NEXT: [[VSHL_N:%.*]] = shl <2 x i32> [[TMP1]], splat (i32 3) +// CHECK-NEXT: ret <2 x i32> [[VSHL_N]] +// +uint32x2_t test_vshl_n_u32(uint32x2_t a) { + return vshl_n_u32(a, 3); +} + +// CHECK-LABEL: define dso_local <16 x i8> @test_vshlq_n_u8( +// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[VSHL_N:%.*]] = shl <16 x i8> [[A]], splat (i8 3) +// CHECK-NEXT: ret <16 x i8> [[VSHL_N]] +// +uint8x16_t test_vshlq_n_u8(uint8x16_t a) { + return vshlq_n_u8(a, 3); +} + +// CHECK-LABEL: define dso_local <8 x i16> @test_vshlq_n_u16( +// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> +// CHECK-NEXT: [[VSHL_N:%.*]] = shl <8 x i16> [[TMP1]], splat (i16 3) +// CHECK-NEXT: ret <8 x i16> [[VSHL_N]] +// +uint16x8_t test_vshlq_n_u16(uint16x8_t a) { + return vshlq_n_u16(a, 3); +} + +// CHECK-LABEL: define dso_local <4 x i32> @test_vshlq_n_u32( +// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> +// CHECK-NEXT: [[VSHL_N:%.*]] = shl <4 x i32> [[TMP1]], splat (i32 3) +// CHECK-NEXT: ret <4 x i32> [[VSHL_N]] +// +uint32x4_t test_vshlq_n_u32(uint32x4_t a) { + return vshlq_n_u32(a, 3); +} + +// CHECK-LABEL: define dso_local <2 x i64> @test_vshlq_n_u64( +// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> +// CHECK-NEXT: [[VSHL_N:%.*]] = shl <2 x i64> [[TMP1]], splat (i64 3) +// CHECK-NEXT: ret <2 x i64> [[VSHL_N]] +// +uint64x2_t test_vshlq_n_u64(uint64x2_t a) { + return vshlq_n_u64(a, 3); +} + // CHECK-LABEL: define dso_local <8 x i8> @test_vshr_n_s8( // CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -11438,26 +11598,6 @@ uint64_t test_vqsubd_u64(uint64_t a, uint64_t b) { return vqsubd_u64(a, b); } -// CHECK-LABEL: define dso_local i64 @test_vshld_s64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSHLD_S64_I:%.*]] = call i64 @llvm.aarch64.neon.sshl.i64(i64 [[A]], i64 [[B]]) -// CHECK-NEXT: ret i64 [[VSHLD_S64_I]] -// -int64_t test_vshld_s64(int64_t a, int64_t b) { - return vshld_s64(a, b); -} - -// CHECK-LABEL: define dso_local i64 @test_vshld_u64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSHLD_U64_I:%.*]] = call i64 @llvm.aarch64.neon.ushl.i64(i64 [[A]], i64 [[B]]) -// CHECK-NEXT: ret i64 [[VSHLD_U64_I]] -// -uint64_t test_vshld_u64(uint64_t a, int64_t b) { - return vshld_u64(a, b); -} - // CHECK-LABEL: define dso_local i8 @test_vqshlb_s8( // CHECK-SAME: i8 noundef [[A:%.*]], i8 noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -17273,24 +17413,28 @@ uint64x1_t test_vrsra_n_u64(uint64x1_t a, uint64x1_t b) { return vrsra_n_u64(a, b, 1); } -// CHECK-LABEL: define dso_local i64 @test_vshld_n_s64( -// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-LABEL: define dso_local <1 x i64> @test_vshl_n_s64( +// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[SHLD_N:%.*]] = shl i64 [[A]], 1 -// CHECK-NEXT: ret i64 [[SHLD_N]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> +// CHECK-NEXT: [[VSHL_N:%.*]] = shl <1 x i64> [[TMP1]], splat (i64 1) +// CHECK-NEXT: ret <1 x i64> [[VSHL_N]] // -int64_t test_vshld_n_s64(int64_t a) { - return (int64_t)vshld_n_s64(a, 1); +int64x1_t test_vshl_n_s64(int64x1_t a) { + return vshl_n_s64(a, 1); } -// CHECK-LABEL: define dso_local i64 @test_vshld_n_u64( -// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-LABEL: define dso_local <1 x i64> @test_vshl_n_u64( +// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[SHLD_N:%.*]] = shl i64 [[A]], 63 -// CHECK-NEXT: ret i64 [[SHLD_N]] +// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> +// CHECK-NEXT: [[VSHL_N:%.*]] = shl <1 x i64> [[TMP1]], splat (i64 1) +// CHECK-NEXT: ret <1 x i64> [[VSHL_N]] // -uint64_t test_vshld_n_u64(uint64_t a) { - return (uint64_t)vshld_n_u64(a, 63); +uint64x1_t test_vshl_n_u64(uint64x1_t a) { + return vshl_n_u64(a, 1); } // CHECK-LABEL: define dso_local i8 @test_vqshlb_n_s8( >From 9786f5ec3fbd6538dd70746a7e6a1ba2e9cac4d0 Mon Sep 17 00:00:00 2001 From: albertbolt <[email protected]> Date: Sat, 21 Mar 2026 13:01:24 +0530 Subject: [PATCH 6/7] removed tests from neon intrinsics --- clang/test/CodeGen/AArch64/neon-intrinsics.c | 184 ------------------- 1 file changed, 184 deletions(-) diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index 80bb22cc43c78..4d511e508430d 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -6342,166 +6342,6 @@ float64x2_t test_vmulxq_f64(float64x2_t a, float64x2_t b) { return vmulxq_f64(a, b); } -// CHECK-LABEL: define dso_local <8 x i8> @test_vshl_n_s8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <8 x i8> [[A]], splat (i8 3) -// CHECK-NEXT: ret <8 x i8> [[VSHL_N]] -// -int8x8_t test_vshl_n_s8(int8x8_t a) { - return vshl_n_s8(a, 3); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vshl_n_s16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <4 x i16> [[TMP1]], splat (i16 3) -// CHECK-NEXT: ret <4 x i16> [[VSHL_N]] -// -int16x4_t test_vshl_n_s16(int16x4_t a) { - return vshl_n_s16(a, 3); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vshl_n_s32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <2 x i32> [[TMP1]], splat (i32 3) -// CHECK-NEXT: ret <2 x i32> [[VSHL_N]] -// -int32x2_t test_vshl_n_s32(int32x2_t a) { - return vshl_n_s32(a, 3); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vshlq_n_s8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <16 x i8> [[A]], splat (i8 3) -// CHECK-NEXT: ret <16 x i8> [[VSHL_N]] -// -int8x16_t test_vshlq_n_s8(int8x16_t a) { - return vshlq_n_s8(a, 3); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vshlq_n_s16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <8 x i16> [[TMP1]], splat (i16 3) -// CHECK-NEXT: ret <8 x i16> [[VSHL_N]] -// -int16x8_t test_vshlq_n_s16(int16x8_t a) { - return vshlq_n_s16(a, 3); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vshlq_n_s32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <4 x i32> [[TMP1]], splat (i32 3) -// CHECK-NEXT: ret <4 x i32> [[VSHL_N]] -// -int32x4_t test_vshlq_n_s32(int32x4_t a) { - return vshlq_n_s32(a, 3); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vshlq_n_s64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <2 x i64> [[TMP1]], splat (i64 3) -// CHECK-NEXT: ret <2 x i64> [[VSHL_N]] -// -int64x2_t test_vshlq_n_s64(int64x2_t a) { - return vshlq_n_s64(a, 3); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vshl_n_u8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <8 x i8> [[A]], splat (i8 3) -// CHECK-NEXT: ret <8 x i8> [[VSHL_N]] -// -uint8x8_t test_vshl_n_u8(uint8x8_t a) { - return vshl_n_u8(a, 3); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vshl_n_u16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <4 x i16> [[TMP1]], splat (i16 3) -// CHECK-NEXT: ret <4 x i16> [[VSHL_N]] -// -uint16x4_t test_vshl_n_u16(uint16x4_t a) { - return vshl_n_u16(a, 3); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vshl_n_u32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <2 x i32> [[TMP1]], splat (i32 3) -// CHECK-NEXT: ret <2 x i32> [[VSHL_N]] -// -uint32x2_t test_vshl_n_u32(uint32x2_t a) { - return vshl_n_u32(a, 3); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vshlq_n_u8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <16 x i8> [[A]], splat (i8 3) -// CHECK-NEXT: ret <16 x i8> [[VSHL_N]] -// -uint8x16_t test_vshlq_n_u8(uint8x16_t a) { - return vshlq_n_u8(a, 3); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vshlq_n_u16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <8 x i16> [[TMP1]], splat (i16 3) -// CHECK-NEXT: ret <8 x i16> [[VSHL_N]] -// -uint16x8_t test_vshlq_n_u16(uint16x8_t a) { - return vshlq_n_u16(a, 3); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vshlq_n_u32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <4 x i32> [[TMP1]], splat (i32 3) -// CHECK-NEXT: ret <4 x i32> [[VSHL_N]] -// -uint32x4_t test_vshlq_n_u32(uint32x4_t a) { - return vshlq_n_u32(a, 3); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vshlq_n_u64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <2 x i64> [[TMP1]], splat (i64 3) -// CHECK-NEXT: ret <2 x i64> [[VSHL_N]] -// -uint64x2_t test_vshlq_n_u64(uint64x2_t a) { - return vshlq_n_u64(a, 3); -} - // CHECK-LABEL: define dso_local <8 x i8> @test_vshr_n_s8( // CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -17413,30 +17253,6 @@ uint64x1_t test_vrsra_n_u64(uint64x1_t a, uint64x1_t b) { return vrsra_n_u64(a, b, 1); } -// CHECK-LABEL: define dso_local <1 x i64> @test_vshl_n_s64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <1 x i64> [[TMP1]], splat (i64 1) -// CHECK-NEXT: ret <1 x i64> [[VSHL_N]] -// -int64x1_t test_vshl_n_s64(int64x1_t a) { - return vshl_n_s64(a, 1); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vshl_n_u64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VSHL_N:%.*]] = shl <1 x i64> [[TMP1]], splat (i64 1) -// CHECK-NEXT: ret <1 x i64> [[VSHL_N]] -// -uint64x1_t test_vshl_n_u64(uint64x1_t a) { - return vshl_n_u64(a, 1); -} - // CHECK-LABEL: define dso_local i8 @test_vqshlb_n_s8( // CHECK-SAME: i8 noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] >From accf36d6f2b9a457a98e6deccbacca6227c02044 Mon Sep 17 00:00:00 2001 From: albertbolt <[email protected]> Date: Sat, 28 Mar 2026 19:40:34 +0530 Subject: [PATCH 7/7] review suggestions resolved --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 23 +++--- clang/test/CodeGen/AArch64/neon/intrinsics.c | 81 +++++++++---------- 2 files changed, 49 insertions(+), 55 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index d6b9a22080885..e447275679e6e 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -188,24 +188,19 @@ static mlir::Value emitNeonSplat(CIRGenBuilderTy &builder, mlir::Location loc, static mlir::Value emitNeonShiftVector(CIRGenBuilderTy &builder, mlir::Value shiftVal, cir::VectorType vecTy, - mlir::Location loc, bool neg) { - int shiftAmt = getIntValueFromConstOp(shiftVal); - if (neg) - shiftAmt = -shiftAmt; - llvm::SmallVector<mlir::Attribute> vecAttr{ - vecTy.getSize(), - // ConstVectorAttr requires cir::IntAttr - cir::IntAttr::get(vecTy.getElementType(), shiftAmt)}; - cir::ConstVectorAttr constVecAttr = cir::ConstVectorAttr::get( - vecTy, mlir::ArrayAttr::get(builder.getContext(), vecAttr)); - return cir::ConstantOp::create(builder, loc, constVecAttr); + mlir::Location loc) { + mlir::Type eltTy = vecTy.getElementType(); + if (shiftVal.getType() != eltTy) { + shiftVal = builder.createIntCast(shiftVal, eltTy); + } + return cir::VecSplatOp::create(builder, loc, vecTy, shiftVal); } static mlir::Value emitCommonNeonShift(CIRGenBuilderTy &builder, mlir::Location loc, cir::VectorType resTy, mlir::Value shifTgt, - mlir::Value shiftAmt, bool shiftLeft, bool negAmt = false) { - shiftAmt = emitNeonShiftVector(builder, shiftAmt, resTy, loc, negAmt); + mlir::Value shiftAmt, bool shiftLeft) { + shiftAmt = emitNeonShiftVector(builder, shiftAmt, resTy, loc); return cir::ShiftOp::create(builder, loc, resTy, builder.createBitcast(shifTgt, resTy), shiftAmt, shiftLeft); @@ -450,7 +445,7 @@ static mlir::Value emitCommonNeonBuiltinExpr( case NEON::BI__builtin_neon_vshl_n_v: case NEON::BI__builtin_neon_vshlq_n_v: return emitCommonNeonShift(cgf.getBuilder(), loc, vTy, ops[0], ops[1], - true); + /*shiftLeft=*/true); case NEON::BI__builtin_neon_vshll_n_v: case NEON::BI__builtin_neon_vshrn_n_v: case NEON::BI__builtin_neon_vshr_n_v: diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index e54fc494bd32c..da4463e21d0ff 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -1524,7 +1524,7 @@ int64_t test_vshld_u64(int64_t a,int64_t b) { int8x16_t test_vshlq_n_s8(int8x16_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<16 x !s8i>, %{{.*}} : !cir.vector<16 x !s8i>) -> !cir.vector<16 x !s8i> -// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]]) {{.*}} { // LLVM: [[VSHL_N:%.*]] = shl <16 x i8> [[A]], splat (i8 3) // LLVM: ret <16 x i8> [[VSHL_N]] // @@ -1535,10 +1535,10 @@ int8x16_t test_vshlq_n_s8(int8x16_t a) { int16x8_t test_vshlq_n_s16(int16x8_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<8 x !s16i>, %{{.*}} : !cir.vector<8 x !s16i>) -> !cir.vector<8 x !s16i> -// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]]) {{.*}} { // LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> // LLVM-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// LLVM-NEXT: [[VSHL_N:%.*]] = shl <8 x i16> [[TMP1]], splat (i16 3) +// LLVM: [[VSHL_N:%.*]] = shl <8 x i16> [[TMP1]], splat (i16 3) // LLVM: ret <8 x i16> [[VSHL_N]] return vshlq_n_s16(a, 3); } @@ -1547,10 +1547,10 @@ int16x8_t test_vshlq_n_s16(int16x8_t a) { int32x4_t test_vshlq_n_s32(int32x4_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<4 x !s32i>, %{{.*}} : !cir.vector<4 x !s32i>) -> !cir.vector<4 x !s32i> -// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]]) {{.*}} { // LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// LLVM-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// LLVM-NEXT: [[VSHL_N:%.*]] = shl <4 x i32> [[TMP1]], splat (i32 3) +// LLVM: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> +// LLVM: [[VSHL_N:%.*]] = shl <4 x i32> [[TMP1]], splat (i32 3) // LLVM: ret <4 x i32> [[VSHL_N]] return vshlq_n_s32(a, 3); } @@ -1559,10 +1559,10 @@ int32x4_t test_vshlq_n_s32(int32x4_t a) { int64x2_t test_vshlq_n_s64(int64x2_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<2 x !s64i>, %{{.*}} : !cir.vector<2 x !s64i>) -> !cir.vector<2 x !s64i> -// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]]) {{.*}} { // LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// LLVM-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// LLVM-NEXT: [[VSHL_N:%.*]] = shl <2 x i64> [[TMP1]], splat (i64 3) +// LLVM: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> +// LLVM: [[VSHL_N:%.*]] = shl <2 x i64> [[TMP1]], splat (i64 3) // LLVM: ret <2 x i64> [[VSHL_N]] return vshlq_n_s64(a, 3); } @@ -1571,7 +1571,7 @@ int64x2_t test_vshlq_n_s64(int64x2_t a) { uint8x16_t test_vshlq_n_u8(uint8x16_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<16 x !u8i>, %{{.*}} : !cir.vector<16 x !u8i>) -> !cir.vector<16 x !u8i> -// LLVM-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]]) {{.*}} { // LLVM: [[VSHL_N:%.*]] = shl <16 x i8> [[A]], splat (i8 3) // LLVM: ret <16 x i8> [[VSHL_N]] return vshlq_n_u8(a, 3); @@ -1581,10 +1581,10 @@ uint8x16_t test_vshlq_n_u8(uint8x16_t a) { uint16x8_t test_vshlq_n_u16(uint16x8_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<8 x !u16i>, %{{.*}} : !cir.vector<8 x !u16i>) -> !cir.vector<8 x !u16i> -// LLVM-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]]) {{.*}} { // LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// LLVM-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// LLVM-NEXT: [[VSHL_N:%.*]] = shl <8 x i16> [[TMP1]], splat (i16 3) +// LLVM: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> +// LLVM: [[VSHL_N:%.*]] = shl <8 x i16> [[TMP1]], splat (i16 3) // LLVM: ret <8 x i16> [[VSHL_N]] return vshlq_n_u16(a, 3); } @@ -1593,10 +1593,10 @@ uint16x8_t test_vshlq_n_u16(uint16x8_t a) { uint32x4_t test_vshlq_n_u32(uint32x4_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<4 x !u32i>, %{{.*}} : !cir.vector<4 x !u32i>) -> !cir.vector<4 x !u32i> -// LLVM-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]]) {{.*}} { // LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// LLVM-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// LLVM-NEXT: [[VSHL_N:%.*]] = shl <4 x i32> [[TMP1]], splat (i32 3) +// LLVM: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> +// LLVM: [[VSHL_N:%.*]] = shl <4 x i32> [[TMP1]], splat (i32 3) // LLVM: ret <4 x i32> [[VSHL_N]] return vshlq_n_u32(a, 3); } @@ -1605,10 +1605,10 @@ uint32x4_t test_vshlq_n_u32(uint32x4_t a) { uint64x2_t test_vshlq_n_u64(uint64x2_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<2 x !u64i>, %{{.*}} : !cir.vector<2 x !u64i>) -> !cir.vector<2 x !u64i> -// LLVM-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]]) {{.*}} { // LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// LLVM-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// LLVM-NEXT: [[VSHL_N:%.*]] = shl <2 x i64> [[TMP1]], splat (i64 3) +// LLVM: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> +// LLVM: [[VSHL_N:%.*]] = shl <2 x i64> [[TMP1]], splat (i64 3) // LLVM: ret <2 x i64> [[VSHL_N]] return vshlq_n_u64(a, 3); } @@ -1617,7 +1617,7 @@ uint64x2_t test_vshlq_n_u64(uint64x2_t a) { int8x8_t test_vshl_n_s8(int8x8_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<8 x !s8i>, %{{.*}} : !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s8i> -// LLVM-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]]) {{.*}} { // LLVM: [[VSHL_N:%.*]] = shl <8 x i8> [[A]], splat (i8 3) // LLVM: ret <8 x i8> [[VSHL_N]] return vshl_n_s8(a, 3); @@ -1627,10 +1627,10 @@ int8x8_t test_vshl_n_s8(int8x8_t a) { int16x4_t test_vshl_n_s16(int16x4_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<4 x !s16i>, %{{.*}} : !cir.vector<4 x !s16i>) -> !cir.vector<4 x !s16i> -// LLVM-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]]) {{.*}} { // LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// LLVM-NEXT: [[VSHL_N:%.*]] = shl <4 x i16> [[TMP1]], splat (i16 3) +// LLVM: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM: [[VSHL_N:%.*]] = shl <4 x i16> [[TMP1]], splat (i16 3) // LLVM: ret <4 x i16> [[VSHL_N]] return vshl_n_s16(a, 3); } @@ -1639,10 +1639,10 @@ int16x4_t test_vshl_n_s16(int16x4_t a) { int32x2_t test_vshl_n_s32(int32x2_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<2 x !s32i>, %{{.*}} : !cir.vector<2 x !s32i>) -> !cir.vector<2 x !s32i> -// LLVM-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]]) {{.*}} { // LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// LLVM-NEXT: [[VSHL_N:%.*]] = shl <2 x i32> [[TMP1]], splat (i32 3) +// LLVM: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM: [[VSHL_N:%.*]] = shl <2 x i32> [[TMP1]], splat (i32 3) // LLVM: ret <2 x i32> [[VSHL_N]] return vshl_n_s32(a, 3); } @@ -1651,10 +1651,10 @@ int32x2_t test_vshl_n_s32(int32x2_t a) { int64x1_t test_vshl_n_s64(int64x1_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<1 x !s64i>, %{{.*}} : !cir.vector<1 x !s64i>) -> !cir.vector<1 x !s64i> -// LLVM-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]]) {{.*}} { // LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// LLVM-NEXT: [[VSHL_N:%.*]] = shl <1 x i64> [[TMP1]], splat (i64 1) +// LLVM: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> +// LLVM: [[VSHL_N:%.*]] = shl <1 x i64> [[TMP1]], splat (i64 1) // LLVM: ret <1 x i64> [[VSHL_N]] return vshl_n_s64(a, 1); } @@ -1663,7 +1663,7 @@ int64x1_t test_vshl_n_s64(int64x1_t a) { uint8x8_t test_vshl_n_u8(uint8x8_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<8 x !u8i>, %{{.*}} : !cir.vector<8 x !u8i>) -> !cir.vector<8 x !u8i> -// LLVM-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]]) {{.*}} { // LLVM: [[VSHL_N:%.*]] = shl <8 x i8> [[A]], splat (i8 3) // LLVM: ret <8 x i8> [[VSHL_N]] return vshl_n_u8(a, 3); @@ -1673,10 +1673,10 @@ uint8x8_t test_vshl_n_u8(uint8x8_t a) { uint16x4_t test_vshl_n_u16(uint16x4_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<4 x !u16i>, %{{.*}} : !cir.vector<4 x !u16i>) -> !cir.vector<4 x !u16i> -// LLVM-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]]) {{.*}} { // LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// LLVM-NEXT: [[VSHL_N:%.*]] = shl <4 x i16> [[TMP1]], splat (i16 3) +// LLVM: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM: [[VSHL_N:%.*]] = shl <4 x i16> [[TMP1]], splat (i16 3) // LLVM: ret <4 x i16> [[VSHL_N]] return vshl_n_u16(a, 3); } @@ -1685,10 +1685,10 @@ uint16x4_t test_vshl_n_u16(uint16x4_t a) { uint32x2_t test_vshl_n_u32(uint32x2_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<2 x !u32i>, %{{.*}} : !cir.vector<2 x !u32i>) -> !cir.vector<2 x !u32i> -// LLVM-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]]) {{.*}} { // LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// LLVM-NEXT: [[VSHL_N:%.*]] = shl <2 x i32> [[TMP1]], splat (i32 3) +// LLVM: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM: [[VSHL_N:%.*]] = shl <2 x i32> [[TMP1]], splat (i32 3) // LLVM: ret <2 x i32> [[VSHL_N]] return vshl_n_u32(a, 3); } @@ -1697,11 +1697,10 @@ uint32x2_t test_vshl_n_u32(uint32x2_t a) { uint64x1_t test_vshl_n_u64(uint64x1_t a) { // CIR: [[RES:%.*]] = cir.shift(left, %{{.*}} : !cir.vector<1 x !u64i>, %{{.*}} : !cir.vector<1 x !u64i>) -> !cir.vector<1 x !u64i> -// LLVM-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]]) {{.*}} { // LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// LLVM-NEXT: [[VSHL_N:%.*]] = shl <1 x i64> [[TMP1]], splat (i64 1) +// LLVM: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> +// LLVM: [[VSHL_N:%.*]] = shl <1 x i64> [[TMP1]], splat (i64 1) // LLVM: ret <1 x i64> [[VSHL_N]] return vshl_n_u64(a, 1); -} - +} \ No newline at end of file _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
