================
@@ -29,3 +29,32 @@ define i1 @sqrt_neginf_v4f32(<4 x float> %a0, ptr %p1) {
%res = tail call i1 @llvm.is.fpclass.f32(float %elt, i32 4) ; 0x4 = "neginf"
ret i1 %res
}
+
+define i1 @demanded_elts_safe_lane(float %unknown) {
----------------
joaovam wrote:
Hi @RKSimon, I have added some riscv tests to a new file, as I didn't know
where to append them to. Thanks for your suggestion of commenting out the
isKnownNeverNaN and checking what breaks.
https://github.com/llvm/llvm-project/pull/190185
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