https://github.com/banach-space updated https://github.com/llvm/llvm-project/pull/188547
From 254b8449dcca4919a7b4ea334bb8e51570133d4d Mon Sep 17 00:00:00 2001 From: Andrzej Warzynski <[email protected]> Date: Wed, 25 Mar 2026 17:10:34 +0000 Subject: [PATCH 1/3] [clang][test] Add `%clang_cc1_arm64_neon` substitution Add a LIT substitution `%clang_cc1_arm64_neon` expanding to: clang -cc1 -internal-isystem <path> \ -nostdsysteminc -triple arm64-none-linux-gnu \ -target-feature +neon -disable-O0-optnone \ -flax-vector-conversions=none This invocation is repeated across multiple tests. Introducing a substitution reduces duplication, shortens RUN lines, and ensures consistency across `clang -cc1` invocations. Shorter RUN lines also make test-specific flags easier to spot. --- .../test/CodeGen/AArch64/bf16-getset-intrinsics.c | 2 +- clang/test/CodeGen/AArch64/lit.local.cfg | 14 ++++++++++++++ clang/test/CodeGen/AArch64/neon-intrinsics.c | 6 +----- clang/test/CodeGen/AArch64/neon/bf16-getset.c | 6 +++--- clang/test/CodeGen/AArch64/neon/fullfp16.c | 6 +++--- clang/test/CodeGen/AArch64/neon/intrinsics.c | 6 +++--- 6 files changed, 25 insertions(+), 15 deletions(-) create mode 100644 clang/test/CodeGen/AArch64/lit.local.cfg diff --git a/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c b/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c index 89b332d14d588..6944faffdc593 100644 --- a/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c +++ b/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s +// RUN: %clang_cc1_arm64_neon -target-feature +bf16 -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/AArch64/lit.local.cfg b/clang/test/CodeGen/AArch64/lit.local.cfg new file mode 100644 index 0000000000000..d6d1683f867bc --- /dev/null +++ b/clang/test/CodeGen/AArch64/lit.local.cfg @@ -0,0 +1,14 @@ +import re +from lit.llvm import llvm_config + +# Retrieve the substitution for %clang_cc1 +target = "%clang_cc1" +clang_cc1 = next( + (value for pattern, value in config.substitutions if re.search(pattern, target)), + None +) + +# Standard `clang -cc1` invocaiton for code-gen/lowering tests for +# Aarch64/arm64. +config.substitutions.append(("%clang_cc1_arm64_neon", + clang_cc1 + " -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none")) diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index beda97854e3e1..06e93fedcebba 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -1,9 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 -// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -disable-O0-optnone \ -// RUN: -flax-vector-conversions=none -emit-llvm -o - %s \ -// RUN: | opt -S -passes=mem2reg,sroa \ -// RUN: | FileCheck %s +// RUN: %clang_cc1_arm64_neon -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/AArch64/neon/bf16-getset.c b/clang/test/CodeGen/AArch64/neon/bf16-getset.c index f860bfb7e40aa..dcc4466984ba4 100644 --- a/clang/test/CodeGen/AArch64/neon/bf16-getset.c +++ b/clang/test/CodeGen/AArch64/neon/bf16-getset.c @@ -1,8 +1,8 @@ // REQUIRES: aarch64-registered-target || arm-registered-target -// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +bf16 -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM -// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +bf16 -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM %} -// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +bf16 -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=ALL,CIR %} +// RUN: %clang_cc1_arm64_neon -target-feature +bf16 -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM +// RUN: %if cir-enabled %{%clang_cc1_arm64_neon -target-feature +bf16 -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_arm64_neon -target-feature +bf16 -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=ALL,CIR %} #include <arm_neon.h> diff --git a/clang/test/CodeGen/AArch64/neon/fullfp16.c b/clang/test/CodeGen/AArch64/neon/fullfp16.c index 056b0df253e48..45d4b32fff87e 100644 --- a/clang/test/CodeGen/AArch64/neon/fullfp16.c +++ b/clang/test/CodeGen/AArch64/neon/fullfp16.c @@ -1,8 +1,8 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s --check-prefixes=ALL,LLVM -// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,simplifycfg | FileCheck %s --check-prefixes=ALL,LLVM %} -// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=ALL,CIR %} +// RUN: %clang_cc1_arm64_neon -target-feature +fullfp16 -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s --check-prefixes=ALL,LLVM +// RUN: %if cir-enabled %{%clang_cc1_arm64_neon -target-feature +fullfp16 -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,simplifycfg | FileCheck %s --check-prefixes=ALL,LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_arm64_neon -target-feature +fullfp16 -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=ALL,CIR %} //============================================================================= // NOTES diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index 4c58fecb87fa5..2708ba9ebb918 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -1,8 +1,8 @@ // REQUIRES: aarch64-registered-target || arm-registered-target -// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM -// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM %} -// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=ALL,CIR %} +// RUN: %clang_cc1_arm64_neon -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM +// RUN: %if cir-enabled %{%clang_cc1_arm64_neon -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_arm64_neon -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=ALL,CIR %} //============================================================================= // NOTES From 3cb8eb08c9320479289d4aa313973c2db130a58d Mon Sep 17 00:00:00 2001 From: Andrzej Warzynski <[email protected]> Date: Tue, 7 Apr 2026 16:29:41 +0000 Subject: [PATCH 2/3] Incorporate suggestions from Aaron and Eli --- clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c | 2 +- clang/test/CodeGen/AArch64/lit.local.cfg | 4 ++-- clang/test/CodeGen/AArch64/neon-intrinsics.c | 2 +- clang/test/CodeGen/AArch64/neon/bf16-getset.c | 6 +++--- clang/test/CodeGen/AArch64/neon/fullfp16.c | 6 +++--- clang/test/CodeGen/AArch64/neon/intrinsics.c | 6 +++--- 6 files changed, 13 insertions(+), 13 deletions(-) diff --git a/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c b/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c index 6944faffdc593..7df38a8263e50 100644 --- a/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c +++ b/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1_arm64_neon -target-feature +bf16 -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s +// RUN: %clang_cc1_cg_arm64_neon %sema_flags -target-feature +bf16 -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/AArch64/lit.local.cfg b/clang/test/CodeGen/AArch64/lit.local.cfg index d6d1683f867bc..6b2eeedb7dc50 100644 --- a/clang/test/CodeGen/AArch64/lit.local.cfg +++ b/clang/test/CodeGen/AArch64/lit.local.cfg @@ -10,5 +10,5 @@ clang_cc1 = next( # Standard `clang -cc1` invocaiton for code-gen/lowering tests for # Aarch64/arm64. -config.substitutions.append(("%clang_cc1_arm64_neon", - clang_cc1 + " -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none")) +config.substitutions.append(("%clang_cc1_cg_arm64_neon", clang_cc1 + " -triple arm64-none-linux-gnu -target-feature +neon -o -")) +config.substitutions.append(("%sema_flags", "-flax-vector-conversions=none -Wall -Werror")) diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index 06e93fedcebba..d36484e674d74 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 -// RUN: %clang_cc1_arm64_neon -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s +// RUN: %clang_cc1_cg_arm64_neon %sema_flags -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/AArch64/neon/bf16-getset.c b/clang/test/CodeGen/AArch64/neon/bf16-getset.c index dcc4466984ba4..5d489512283b8 100644 --- a/clang/test/CodeGen/AArch64/neon/bf16-getset.c +++ b/clang/test/CodeGen/AArch64/neon/bf16-getset.c @@ -1,8 +1,8 @@ // REQUIRES: aarch64-registered-target || arm-registered-target -// RUN: %clang_cc1_arm64_neon -target-feature +bf16 -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM -// RUN: %if cir-enabled %{%clang_cc1_arm64_neon -target-feature +bf16 -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM %} -// RUN: %if cir-enabled %{%clang_cc1_arm64_neon -target-feature +bf16 -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=ALL,CIR %} +// RUN: %clang_cc1_cg_arm64_neon %sema_flags -target-feature +bf16 -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon %sema_flags -target-feature +bf16 -fclangir -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon %sema_flags -target-feature +bf16 -fclangir -emit-cir %s -disable-O0-optnone | FileCheck %s --check-prefixes=ALL,CIR %} #include <arm_neon.h> diff --git a/clang/test/CodeGen/AArch64/neon/fullfp16.c b/clang/test/CodeGen/AArch64/neon/fullfp16.c index 45d4b32fff87e..e66e72a9e21aa 100644 --- a/clang/test/CodeGen/AArch64/neon/fullfp16.c +++ b/clang/test/CodeGen/AArch64/neon/fullfp16.c @@ -1,8 +1,8 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1_arm64_neon -target-feature +fullfp16 -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s --check-prefixes=ALL,LLVM -// RUN: %if cir-enabled %{%clang_cc1_arm64_neon -target-feature +fullfp16 -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,simplifycfg | FileCheck %s --check-prefixes=ALL,LLVM %} -// RUN: %if cir-enabled %{%clang_cc1_arm64_neon -target-feature +fullfp16 -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=ALL,CIR %} +// RUN: %clang_cc1_cg_arm64_neon %sema_flags -target-feature +fullfp16 -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg | FileCheck %s --check-prefixes=ALL,LLVM +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon %sema_flags -target-feature +fullfp16 -fclangir -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,simplifycfg | FileCheck %s --check-prefixes=ALL,LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon %sema_flags -target-feature +fullfp16 -fclangir -emit-cir %s -disable-O0-optnone | FileCheck %s --check-prefixes=ALL,CIR %} //============================================================================= // NOTES diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index 2708ba9ebb918..dcee153f9ccb8 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -1,8 +1,8 @@ // REQUIRES: aarch64-registered-target || arm-registered-target -// RUN: %clang_cc1_arm64_neon -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM -// RUN: %if cir-enabled %{%clang_cc1_arm64_neon -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM %} -// RUN: %if cir-enabled %{%clang_cc1_arm64_neon -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=ALL,CIR %} +// RUN: %clang_cc1_cg_arm64_neon %sema_flags -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon %sema_flags -fclangir -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon %sema_flags -fclangir -emit-cir %s -disable-O0-optnone | FileCheck %s --check-prefixes=ALL,CIR %} //============================================================================= // NOTES From edf82389fd6a9e7da4adf05937960aa885fafd64 Mon Sep 17 00:00:00 2001 From: Andrzej Warzynski <[email protected]> Date: Tue, 7 Apr 2026 19:13:09 +0000 Subject: [PATCH 3/3] Remove %sema_flags --- clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c | 2 +- clang/test/CodeGen/AArch64/lit.local.cfg | 1 - clang/test/CodeGen/AArch64/neon-intrinsics.c | 2 +- clang/test/CodeGen/AArch64/neon/bf16-getset.c | 6 +++--- clang/test/CodeGen/AArch64/neon/fullfp16.c | 6 +++--- clang/test/CodeGen/AArch64/neon/intrinsics.c | 6 +++--- 6 files changed, 11 insertions(+), 12 deletions(-) diff --git a/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c b/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c index 7df38a8263e50..c93e3ca31896c 100644 --- a/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c +++ b/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1_cg_arm64_neon %sema_flags -target-feature +bf16 -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s +// RUN: %clang_cc1_cg_arm64_neon -target-feature +bf16 -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/AArch64/lit.local.cfg b/clang/test/CodeGen/AArch64/lit.local.cfg index 6b2eeedb7dc50..8b011ac32bdeb 100644 --- a/clang/test/CodeGen/AArch64/lit.local.cfg +++ b/clang/test/CodeGen/AArch64/lit.local.cfg @@ -11,4 +11,3 @@ clang_cc1 = next( # Standard `clang -cc1` invocaiton for code-gen/lowering tests for # Aarch64/arm64. config.substitutions.append(("%clang_cc1_cg_arm64_neon", clang_cc1 + " -triple arm64-none-linux-gnu -target-feature +neon -o -")) -config.substitutions.append(("%sema_flags", "-flax-vector-conversions=none -Wall -Werror")) diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index d36484e674d74..5a1cbc492cd85 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 -// RUN: %clang_cc1_cg_arm64_neon %sema_flags -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s +// RUN: %clang_cc1_cg_arm64_neon -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/AArch64/neon/bf16-getset.c b/clang/test/CodeGen/AArch64/neon/bf16-getset.c index 5d489512283b8..a00e2fcc01e81 100644 --- a/clang/test/CodeGen/AArch64/neon/bf16-getset.c +++ b/clang/test/CodeGen/AArch64/neon/bf16-getset.c @@ -1,8 +1,8 @@ // REQUIRES: aarch64-registered-target || arm-registered-target -// RUN: %clang_cc1_cg_arm64_neon %sema_flags -target-feature +bf16 -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM -// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon %sema_flags -target-feature +bf16 -fclangir -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM %} -// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon %sema_flags -target-feature +bf16 -fclangir -emit-cir %s -disable-O0-optnone | FileCheck %s --check-prefixes=ALL,CIR %} +// RUN: %clang_cc1_cg_arm64_neon -target-feature +bf16 -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -target-feature +bf16 -fclangir -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -target-feature +bf16 -fclangir -emit-cir %s -disable-O0-optnone | FileCheck %s --check-prefixes=ALL,CIR %} #include <arm_neon.h> diff --git a/clang/test/CodeGen/AArch64/neon/fullfp16.c b/clang/test/CodeGen/AArch64/neon/fullfp16.c index e66e72a9e21aa..b9bd4311cde58 100644 --- a/clang/test/CodeGen/AArch64/neon/fullfp16.c +++ b/clang/test/CodeGen/AArch64/neon/fullfp16.c @@ -1,8 +1,8 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1_cg_arm64_neon %sema_flags -target-feature +fullfp16 -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg | FileCheck %s --check-prefixes=ALL,LLVM -// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon %sema_flags -target-feature +fullfp16 -fclangir -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,simplifycfg | FileCheck %s --check-prefixes=ALL,LLVM %} -// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon %sema_flags -target-feature +fullfp16 -fclangir -emit-cir %s -disable-O0-optnone | FileCheck %s --check-prefixes=ALL,CIR %} +// RUN: %clang_cc1_cg_arm64_neon -target-feature +fullfp16 -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg | FileCheck %s --check-prefixes=ALL,LLVM +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -target-feature +fullfp16 -fclangir -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,simplifycfg | FileCheck %s --check-prefixes=ALL,LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -target-feature +fullfp16 -fclangir -emit-cir %s -disable-O0-optnone | FileCheck %s --check-prefixes=ALL,CIR %} //============================================================================= // NOTES diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index dcee153f9ccb8..7e71ea4c00422 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -1,8 +1,8 @@ // REQUIRES: aarch64-registered-target || arm-registered-target -// RUN: %clang_cc1_cg_arm64_neon %sema_flags -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM -// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon %sema_flags -fclangir -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM %} -// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon %sema_flags -fclangir -emit-cir %s -disable-O0-optnone | FileCheck %s --check-prefixes=ALL,CIR %} +// RUN: %clang_cc1_cg_arm64_neon -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -fclangir -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -fclangir -emit-cir %s -disable-O0-optnone | FileCheck %s --check-prefixes=ALL,CIR %} //============================================================================= // NOTES _______________________________________________ cfe-commits mailing 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