llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Pengcheng Wang (wangpc-pp) <details> <summary>Changes</summary> I don't know how this slipped our eyes... --- Patch is 660.72 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/196921.diff 45 Files Affected: - (modified) clang/include/clang/Basic/riscv_vector.td (+8-8) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c (+40-40) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c (+40-40) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vv.c (+40-40) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vx.c (+40-40) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vv.c (+40-40) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vx.c (+40-40) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4us_vx.c (+40-40) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vv.c (+40-40) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vx.c (+40-40) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vv.c (+40-40) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vx.c (+40-40) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vv.c (+40-40) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vx.c (+40-40) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4us_vx.c (+40-40) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vv.c (+80-80) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vx.c (+80-80) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vv.c (+80-80) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vx.c (+80-80) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vv.c (+80-80) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vx.c (+80-80) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4us_vx.c (+80-80) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vv.c (+80-80) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vx.c (+80-80) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vv.c (+80-80) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vx.c (+80-80) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vv.c (+80-80) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vx.c (+80-80) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4us_vx.c (+80-80) - (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+9-9) - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+17-17) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+10-10) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZvdot4a8i.td (+26-26) - (modified) llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp (+3-3) - (modified) llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp (+2-2) - (modified) llvm/test/CodeGen/RISCV/rvv/commutable-zvdot4a8i.ll (+29-29) - (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvdot4a8i.ll (+129-129) - (modified) llvm/test/CodeGen/RISCV/rvv/vdota4.ll (+80-80) - (modified) llvm/test/CodeGen/RISCV/rvv/vdota4su.ll (+80-80) - (modified) llvm/test/CodeGen/RISCV/rvv/vdota4u.ll (+80-80) - (modified) llvm/test/CodeGen/RISCV/rvv/vdota4us.ll (+40-40) - (modified) llvm/test/CodeGen/RISCV/rvv/zvdot4a8i-sdnode.ll (+72-72) - (modified) llvm/test/MC/RISCV/rvv/zvdot4a8i-invalid.s (+4-4) - (modified) llvm/test/MC/RISCV/rvv/zvdot4a8i.s (+28-28) - (modified) llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll (+24-24) ``````````diff diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index 06b13dd5725f8..386290f8b4ba1 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -2116,7 +2116,7 @@ let UnMaskedPolicyScheme = HasPolicyOperand, HasMasked = false in { } // Zvdot4a8i -multiclass RVVVDOTA4QBuiltinSet<list<list<string>> suffixes_prototypes> { +multiclass RVVVDOT4AQBuiltinSet<list<list<string>> suffixes_prototypes> { let UnMaskedPolicyScheme = HasPolicyOperand, HasMaskedOffOperand = false, OverloadedName = NAME, @@ -2128,16 +2128,16 @@ multiclass RVVVDOTA4QBuiltinSet<list<list<string>> suffixes_prototypes> { // Only SEW=32 is defined for zvdot4a8i so far, and since inputs are in fact // four 8-bit integer bundles, we use unsigned type to represent all of them let RequiredFeatures = ["zvdot4a8i"] in { - defm vdota4 - : RVVVDOTA4QBuiltinSet<[["vv", "v", "vvUvUv"], + defm vdot4a + : RVVVDOT4AQBuiltinSet<[["vv", "v", "vvUvUv"], ["vx", "v", "vvUvUe"]]>; - defm vdota4u - : RVVVDOTA4QBuiltinSet<[["vv", "Uv", "UvUvUvUv"], + defm vdot4au + : RVVVDOT4AQBuiltinSet<[["vv", "Uv", "UvUvUvUv"], ["vx", "Uv", "UvUvUvUe"]]>; - defm vdota4su - : RVVVDOTA4QBuiltinSet<[["vv", "v", "vvUvUv"], + defm vdot4asu + : RVVVDOT4AQBuiltinSet<[["vv", "v", "vvUvUv"], ["vx", "v", "vvUvUe"]]>; - defm vdota4us : RVVVDOTA4QBuiltinSet<[["vx", "v", "vvUvUe"]]>; + defm vdot4aus : RVVVDOT4AQBuiltinSet<[["vx", "v", "vvUvUe"]]>; } // Zvzip diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c index 22f9053ce4a18..d5c1a241dbd60 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c @@ -6,112 +6,112 @@ #include <sifive_vector.h> -// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2( +// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2( // CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // -vint32mf2_t test_vdota4_vv_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1, +vint32mf2_t test_vdot4a_vv_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) { - return __riscv_vdota4_vv_i32mf2(vd, vs2, vs1, vl); + return __riscv_vdot4a_vv_i32mf2(vd, vs2, vs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1( +// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1( // CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // -vint32m1_t test_vdota4_vv_i32m1(vint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1, +vint32m1_t test_vdot4a_vv_i32m1(vint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) { - return __riscv_vdota4_vv_i32m1(vd, vs2, vs1, vl); + return __riscv_vdot4a_vv_i32m1(vd, vs2, vs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2( +// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2( // CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // -vint32m2_t test_vdota4_vv_i32m2(vint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1, +vint32m2_t test_vdot4a_vv_i32m2(vint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) { - return __riscv_vdota4_vv_i32m2(vd, vs2, vs1, vl); + return __riscv_vdot4a_vv_i32m2(vd, vs2, vs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4( +// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4( // CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // -vint32m4_t test_vdota4_vv_i32m4(vint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1, +vint32m4_t test_vdot4a_vv_i32m4(vint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) { - return __riscv_vdota4_vv_i32m4(vd, vs2, vs1, vl); + return __riscv_vdot4a_vv_i32m4(vd, vs2, vs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8( +// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8( // CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // -vint32m8_t test_vdota4_vv_i32m8(vint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1, +vint32m8_t test_vdot4a_vv_i32m8(vint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) { - return __riscv_vdota4_vv_i32m8(vd, vs2, vs1, vl); + return __riscv_vdot4a_vv_i32m8(vd, vs2, vs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_m( +// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_m( // CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // -vint32mf2_t test_vdota4_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vuint32mf2_t vs2, +vint32mf2_t test_vdot4a_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) { - return __riscv_vdota4_vv_i32mf2_m(vm, vd, vs2, vs1, vl); + return __riscv_vdot4a_vv_i32mf2_m(vm, vd, vs2, vs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_m( +// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_m( // CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // -vint32m1_t test_vdota4_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2, +vint32m1_t test_vdot4a_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) { - return __riscv_vdota4_vv_i32m1_m(vm, vd, vs2, vs1, vl); + return __riscv_vdot4a_vv_i32m1_m(vm, vd, vs2, vs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_m( +// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_m( // CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // -vint32m2_t test_vdota4_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2, +vint32m2_t test_vdot4a_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) { - return __riscv_vdota4_vv_i32m2_m(vm, vd, vs2, vs1, vl); + return __riscv_vdot4a_vv_i32m2_m(vm, vd, vs2, vs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_m( +// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_m( // CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // -vint32m4_t test_vdota4_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2, +vint32m4_t test_vdot4a_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) { - return __riscv_vdota4_vv_i32m4_m(vm, vd, vs2, vs1, vl); + return __riscv_vdot4a_vv_i32m4_m(vm, vd, vs2, vs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_m( +// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_m( // CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // -vint32m8_t test_vdota4_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2, +vint32m8_t test_vdot4a_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) { - return __riscv_vdota4_vv_i32m8_m(vm, vd, vs2, vs1, vl); + return __riscv_vdot4a_vv_i32m8_m(vm, vd, vs2, vs1, vl); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c index 2045577d58ca1..be62f7fb1c644 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c @@ -6,112 +6,112 @@ #include <sifive_vector.h> -// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2( +// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2( // CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // -vint32mf2_t test_vdota4_vx_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2, uint32_t rs1, +vint32mf2_t test_vdot4a_vx_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2, uint32_t rs1, size_t vl) { - return __riscv_vdota4_vx_i32mf2(vd, vs2, rs1, vl); + return __riscv_vdot4a_vx_i32mf2(vd, vs2, rs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1( +// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1( // CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // -vint32m1_t test_vdota4_vx_i32m1(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1, +vint32m1_t test_vdot4a_vx_i32m1(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1, size_t vl) { - return __riscv_vdota4_vx_i32m1(vd, vs2, rs1, vl); + return __riscv_vdot4a_vx_i32m1(vd, vs2, rs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2( +// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2( // CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // -vint32m2_t test_vdota4_vx_i32m2(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1, +vint32m2_t test_vdot4a_vx_i32m2(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1, size_t vl) { - return __riscv_vdota4_vx_i32m2(vd, vs2, rs1, vl); + return __riscv_vdot4a_vx_i32m2(vd, vs2, rs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4( +// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4( // CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // -vint32m4_t test_vdota4_vx_i32m4(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1, +vint32m4_t test_vdot4a_vx_i32m4(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1, size_t vl) { - return __riscv_vdota4_vx_i32m4(vd, vs2, rs1, vl); + return __riscv_vdot4a_vx_i32m4(vd, vs2, rs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8( +// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8( // CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // -vint32m8_t test_vdota4_vx_i32m8(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1, +vint32m8_t test_vdot4a_vx_i32m8(vint32m8_t vd, vuint32m8_t vs2, uint32_t rs1, size_t vl) { - return __riscv_vdota4_vx_i32m8(vd, vs2, rs1, vl); + return __riscv_vdot4a_vx_i32m8(vd, vs2, rs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2_m( +// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_m( // CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/196921 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
