https://github.com/Ko496-glitch updated https://github.com/llvm/llvm-project/pull/197095
>From 925e67057efa3d3bbf66b3b05b0bd4038eb55aab Mon Sep 17 00:00:00 2001 From: Kartik Ohlan <[email protected]> Date: Mon, 11 May 2026 23:55:13 -0400 Subject: [PATCH 1/4] maximum-across-vector intrinsics --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 28 ++- clang/test/CodeGen/AArch64/neon-across.c | 122 ------------- clang/test/CodeGen/AArch64/neon/intrinsics.c | 169 ++++++++++++++++++ 3 files changed, 195 insertions(+), 124 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index c142b69f6be6e..3972963ad0fca 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -354,6 +354,22 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr( case NEON::BI__builtin_neon_vrecpxh_f16: case NEON::BI__builtin_neon_vrsqrteh_f16: case NEON::BI__builtin_neon_vrsqrtsh_f16: + case NEON::BI__builtin_neon_vmaxv_s8: + case NEON::BI__builtin_neon_vmaxv_s8: + case NEON::BI__builtin_neon_vmaxvq_s8: + case NEON::BI__builtin_neon_vmaxv_s16: + case NEON::BI__builtin_neon_vmaxvq_s16: + case NEON::BI__builtin_neon_vmaxv_s32: + case NEON::BI__builtin_neon_vmaxvq_s32: + case NEON::BI__builtin_neon_vmaxv_u8: + case NEON::BI__builtin_neon_vmaxvq_u8: + case NEON::BI__builtin_neon_vmaxv_u16: + case NEON::BI__builtin_neon_vmaxvq_u16: + case NEON::BI__builtin_neon_vmaxv_u32: + case NEON::BI__builtin_neon_vmaxvq_u32: + case NEON::BI__builtin_neon_vmaxv_f32: + case NEON::BI__builtin_neon_vmaxvq_f32: + case NEON::BI__builtin_neon_vmaxvq_f64: return emitNeonCall(cgf.cgm, cgf.getBuilder(), {cgf.convertType(expr->getArg(0)->getType())}, ops, llvmIntrName, cgf.convertType(expr->getType()), loc); @@ -2793,10 +2809,18 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, case NEON::BI__builtin_neon_vsqrtq_v: assert(!cir::MissingFeatures::emitConstrainedFPCall()); return emitNeonCall(cgm, builder, {ty}, ops, "sqrt", ty, loc); + case NEON::BI__builtin_neon_vmaxv_f16: { + cir::VectorType vecTy = cir::VectorType::get(fP16Ty, 4); + return emitNeonCall(cgm, builder, {vecTy}, ops, "aarch64.neon.fmaxv", + fP16Ty, loc); + } + case NEON::BI__builtin_neon_vmaxvq_f16: { + cir::VectorType vecTy = cir::VectorType::get(fP16Ty, 8); + return emitNeonCall(cgm, builder, {vecTy}, ops, "aarch64.neon.fmaxv", + fP16Ty, loc); + } case NEON::BI__builtin_neon_vrbit_v: case NEON::BI__builtin_neon_vrbitq_v: - case NEON::BI__builtin_neon_vmaxv_f16: - case NEON::BI__builtin_neon_vmaxvq_f16: case NEON::BI__builtin_neon_vminv_f16: case NEON::BI__builtin_neon_vminvq_f16: case NEON::BI__builtin_neon_vmaxnmv_f16: diff --git a/clang/test/CodeGen/AArch64/neon-across.c b/clang/test/CodeGen/AArch64/neon-across.c index 50044eb0ed045..6324904215f5f 100644 --- a/clang/test/CodeGen/AArch64/neon-across.c +++ b/clang/test/CodeGen/AArch64/neon-across.c @@ -5,125 +5,3 @@ // REQUIRES: aarch64-registered-target || arm-registered-target #include <arm_neon.h> - -// CHECK-LABEL: define {{[^@]+}}@test_vmaxv_s8 -// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VMAXV_S8_I:%.*]] = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> [[A]]) -// CHECK-NEXT: ret i8 [[VMAXV_S8_I]] -// -int8_t test_vmaxv_s8(int8x8_t a) { - return vmaxv_s8(a); -} - -// CHECK-LABEL: define {{[^@]+}}@test_vmaxv_s16 -// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VMAXV_S16_I:%.*]] = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> [[A]]) -// CHECK-NEXT: ret i16 [[VMAXV_S16_I]] -// -int16_t test_vmaxv_s16(int16x4_t a) { - return vmaxv_s16(a); -} - -// CHECK-LABEL: define {{[^@]+}}@test_vmaxv_u8 -// CHECK-SAME: (<8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VMAXV_U8_I:%.*]] = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> [[A]]) -// CHECK-NEXT: ret i8 [[VMAXV_U8_I]] -// -uint8_t test_vmaxv_u8(uint8x8_t a) { - return vmaxv_u8(a); -} - -// CHECK-LABEL: define {{[^@]+}}@test_vmaxv_u16 -// CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VMAXV_U16_I:%.*]] = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> [[A]]) -// CHECK-NEXT: ret i16 [[VMAXV_U16_I]] -// -uint16_t test_vmaxv_u16(uint16x4_t a) { - return vmaxv_u16(a); -} - -// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_s8 -// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VMAXVQ_S8_I:%.*]] = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> [[A]]) -// CHECK-NEXT: ret i8 [[VMAXVQ_S8_I]] -// -int8_t test_vmaxvq_s8(int8x16_t a) { - return vmaxvq_s8(a); -} - -// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_s16 -// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VMAXVQ_S16_I:%.*]] = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> [[A]]) -// CHECK-NEXT: ret i16 [[VMAXVQ_S16_I]] -// -int16_t test_vmaxvq_s16(int16x8_t a) { - return vmaxvq_s16(a); -} - -// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_s32 -// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VMAXVQ_S32_I:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[A]]) -// CHECK-NEXT: ret i32 [[VMAXVQ_S32_I]] -// -int32_t test_vmaxvq_s32(int32x4_t a) { - return vmaxvq_s32(a); -} - -// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_u8 -// CHECK-SAME: (<16 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VMAXVQ_U8_I:%.*]] = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> [[A]]) -// CHECK-NEXT: ret i8 [[VMAXVQ_U8_I]] -// -uint8_t test_vmaxvq_u8(uint8x16_t a) { - return vmaxvq_u8(a); -} - -// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_u16 -// CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VMAXVQ_U16_I:%.*]] = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> [[A]]) -// CHECK-NEXT: ret i16 [[VMAXVQ_U16_I]] -// -uint16_t test_vmaxvq_u16(uint16x8_t a) { - return vmaxvq_u16(a); -} - -// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_u32 -// CHECK-SAME: (<4 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VMAXVQ_U32_I:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[A]]) -// CHECK-NEXT: ret i32 [[VMAXVQ_U32_I]] -// -uint32_t test_vmaxvq_u32(uint32x4_t a) { - return vmaxvq_u32(a); -} - -// CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_f32 -// CHECK-SAME: (<4 x float> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VMAXVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> [[A]]) -// CHECK-NEXT: ret float [[VMAXVQ_F32_I]] -// -float32_t test_vmaxvq_f32(float32x4_t a) { - return vmaxvq_f32(a); -} - -// CHECK-LABEL: define {{[^@]+}}@test_vmaxnmvq_f32 -// CHECK-SAME: (<4 x float> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VMAXNMVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> [[A]]) -// CHECK-NEXT: ret float [[VMAXNMVQ_F32_I]] -// -float32_t test_vmaxnmvq_f32(float32x4_t a) { - return vmaxnmvq_f32(a); -} - - diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index b4fbdcc5436ed..7d3fb8fd7a3ca 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -24,6 +24,175 @@ #include <arm_neon.h> +//===------------------------------------------------------===// +// 2.1.1.13.3 Maximum across vector +//===------------------------------------------------------===// + +// LLVM-LABEL: @test_vmaxv_s8( +// CIR-LABEL: @vmaxv_s8( +int8_t test_vmaxv_s8(int8x8_t a) { +// CIR: {{%.*}} = cir.call @vmaxv_s8({{%.*}}) : (!cir.vector<8 x !s8i> {{.*}}) -> !s8i + +// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]]) +// LLVM: [[VMAXV_S8_I:%.*]] = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> [[A]]) +// LLVM: ret i8 [[VMAXV_S8_I]] + return vmaxv_s8(a); +} + +// LLVM-LABEL: @test_vmaxvq_s8( +// CIR-LABEL: @vmaxvq_s8( +int8_t test_vmaxvq_s8(int8x16_t a) { +// CIR: {{%.*}} = cir.call @vmaxvq_s8({{%.*}}) : (!cir.vector<16 x !s8i> {{.*}}) -> !s8i + +// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]]) +// LLVM: [[VMAXVQ_S8_I:%.*]] = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> [[A]]) +// LLVM: ret i8 [[VMAXVQ_S8_I]] + return vmaxvq_s8(a); +} + +// LLVM-LABEL: @test_vmaxv_s16( +// CIR-LABEL: @vmaxv_s16( +int16_t test_vmaxv_s16(int16x4_t a) { +// CIR: {{%.*}} = cir.call @vmaxv_s16({{%.*}}) : (!cir.vector<4 x !s16i> {{.*}}) -> !s16i + +// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]]) +// LLVM: [[VMAXV_S16_I:%.*]] = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> [[A]]) +// LLVM: ret i16 [[VMAXV_S16_I]] + return vmaxv_s16(a); +} + +// LLVM-LABEL: @test_vmaxvq_s16( +// CIR-LABEL: @vmaxvq_s16( +int16_t test_vmaxvq_s16(int16x8_t a) { +// CIR: {{%.*}} = cir.call @vmaxvq_s16({{%.*}}) : (!cir.vector<8 x !s16i> {{.*}}) -> !s16i + +// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]]) +// LLVM: [[VMAXVQ_S16_I:%.*]] = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> [[A]]) +// LLVM: ret i16 [[VMAXVQ_S16_I]] + return vmaxvq_s16(a); +} + +//LLVM-LABEL: @test_vmaxv_s32 +//CIR-LABEL : @vmaxv_s32 +int32_t test_vmaxv_s32(int32x2_t a) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "vector.reduce.smax" {{%.*}} + +// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]]) +// LLVM: [[VMAXV_S32_I:%.*]] = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> [[A]]) +// LLVM: ret i32 [[VMAXV_S32_I]] + return vmaxv_s32(a); +} + +// LLVM-LABEL: @test_vmaxvq_s32( +// CIR-LABEL: @vmaxvq_s32( +int32_t test_vmaxvq_s32(int32x4_t a) { +// CIR: {{%.*}} = cir.call @vmaxvq_s32({{%.*}}) : (!cir.vector<4 x !s32i> {{.*}}) -> !s32i + +// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]]) +// LLVM: [[VMAXVQ_S32_I:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[A]]) +// LLVM: ret i32 [[VMAXVQ_S32_I]] + return vmaxvq_s32(a); +} + +// LLVM-LABEL: @test_vmaxv_u8( +// CIR-LABEL: @vmaxv_u8( +uint8_t test_vmaxv_u8(uint8x8_t a) { +// CIR: {{%.*}} = cir.call @vmaxv_u8({{%.*}}) : (!cir.vector<8 x !u8i> {{.*}}) -> !u8i + +// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]]) +// LLVM: [[VMAXV_U8_I:%.*]] = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> [[A]]) +// LLVM: ret i8 [[VMAXV_U8_I]] + return vmaxv_u8(a); +} + +// LLVM-LABEL: @test_vmaxvq_u8( +// CIR-LABEL: @vmaxvq_u8( +uint8_t test_vmaxvq_u8(uint8x16_t a) { +// CIR: {{%.*}} = cir.call @vmaxvq_u8({{%.*}}) : (!cir.vector<16 x !u8i> {{.*}}) -> !u8i + +// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]]) +// LLVM: [[VMAXVQ_U8_I:%.*]] = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> [[A]]) +// LLVM: ret i8 [[VMAXVQ_U8_I]] + return vmaxvq_u8(a); +} + +// LLVM-LABEL: @test_vmaxv_u16( +// CIR-LABEL: @vmaxv_u16( +uint16_t test_vmaxv_u16(uint16x4_t a) { +// CIR: {{%.*}} = cir.call @vmaxv_u16({{%.*}}) : (!cir.vector<4 x !u16i> {{.*}}) -> !u16i + +// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]]) +// LLVM: [[VMAXV_U16_I:%.*]] = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> [[A]]) +// LLVM: ret i16 [[VMAXV_U16_I]] + return vmaxv_u16(a); +} + +// LLVM-LABEL: @test_vmaxvq_u16( +// CIR-LABEL: @vmaxvq_u16( +uint16_t test_vmaxvq_u16(uint16x8_t a) { +// CIR: {{%.*}} = cir.call @vmaxvq_u16({{%.*}}) : (!cir.vector<8 x !u16i> {{.*}}) -> !u16i + +// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]]) +// LLVM: [[VMAXVQ_U16_I:%.*]] = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> [[A]]) +// LLVM: ret i16 [[VMAXVQ_U16_I]] + return vmaxvq_u16(a); +} + +//LLVM-LABEL: @test_vmaxv_u32( +//CIR-LABEL : @vmaxv_u32( +uint32_t test_vmaxv_u32(uint32x2_t a) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "vector.reduce.umax" {{%.*}} + +// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]]) +// LLVM: [[VMAXV_U32_I:%.*]] = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> [[A]]) +// LLVM: ret i32 [[VMAXV_U32_I]] + return vmaxv_u32(a); +} + +// LLVM-LABEL: @test_vmaxvq_u32( +// CIR-LABEL: @vmaxvq_u32( +uint32_t test_vmaxvq_u32(uint32x4_t a) { +// CIR: {{%.*}} = cir.call @vmaxvq_u32({{%.*}}) : (!cir.vector<4 x !u32i> {{.*}}) -> !u32i + +// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]]) +// LLVM: [[VMAXVQ_U32_I:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[A]]) +// LLVM: ret i32 [[VMAXVQ_U32_I]] + return vmaxvq_u32(a); +} + +//LLVM-LABEL: @test_vmaxv_f32 +//CIR-LABEL : @vmaxv_f32 +float32_t test_vmaxv_f32(float32x2_t a) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}} + +// LLVM-SAME: <2 x float> {{.*}}[[A:%.*]]) +// LLVM: [[VMAXV_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> [[A]]) +// LLVM: ret float [[VMAXV_F32_I]] + return vmaxv_f32(a); +} + +// LLVM-LABEL: @test_vmaxvq_f32( +// CIR-LABEL: @vmaxvq_f32( +float32_t test_vmaxvq_f32(float32x4_t a) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}} + +// LLVM-SAME: <4 x float> {{.*}}[[A:%.*]]) +// LLVM: [[VMAXVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> [[A]]) +// LLVM: ret float [[VMAXVQ_F32_I]] + return vmaxvq_f32(a); +} + +//LLVM-LABEL: @test_vmaxvq_f64( +//CIR-LABEL : @vmaxvq_f64( +float64_t test_vmaxvq_f64(float64x2_t a) { +// CIR: {{%.*}} = cir.call_llvm_intrinsic "aarch64.neon.fmaxv" {{%.*}} + +// LLVM-SAME: <2 x double> {{.*}}[[A:%.*]]) +// LLVM: [[VMAXVQ_F64_I:%.*]] = call double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double> [[A]]) +// LLVM: ret double [[VMAXVQ_F64_I]] + return vmaxvq_f64(a); +} + //===------------------------------------------------------===// // 2.1.3.2 Vector Saturating Shift Left // >From b1276202881c1ae6b57f9bceff41ae7b9bc613e5 Mon Sep 17 00:00:00 2001 From: Kartik Ohlan <[email protected]> Date: Tue, 12 May 2026 00:05:26 -0400 Subject: [PATCH 2/4] Added vmaxv --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 28 ++----------------- 1 file changed, 2 insertions(+), 26 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index 3972963ad0fca..c142b69f6be6e 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -354,22 +354,6 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr( case NEON::BI__builtin_neon_vrecpxh_f16: case NEON::BI__builtin_neon_vrsqrteh_f16: case NEON::BI__builtin_neon_vrsqrtsh_f16: - case NEON::BI__builtin_neon_vmaxv_s8: - case NEON::BI__builtin_neon_vmaxv_s8: - case NEON::BI__builtin_neon_vmaxvq_s8: - case NEON::BI__builtin_neon_vmaxv_s16: - case NEON::BI__builtin_neon_vmaxvq_s16: - case NEON::BI__builtin_neon_vmaxv_s32: - case NEON::BI__builtin_neon_vmaxvq_s32: - case NEON::BI__builtin_neon_vmaxv_u8: - case NEON::BI__builtin_neon_vmaxvq_u8: - case NEON::BI__builtin_neon_vmaxv_u16: - case NEON::BI__builtin_neon_vmaxvq_u16: - case NEON::BI__builtin_neon_vmaxv_u32: - case NEON::BI__builtin_neon_vmaxvq_u32: - case NEON::BI__builtin_neon_vmaxv_f32: - case NEON::BI__builtin_neon_vmaxvq_f32: - case NEON::BI__builtin_neon_vmaxvq_f64: return emitNeonCall(cgf.cgm, cgf.getBuilder(), {cgf.convertType(expr->getArg(0)->getType())}, ops, llvmIntrName, cgf.convertType(expr->getType()), loc); @@ -2809,18 +2793,10 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, case NEON::BI__builtin_neon_vsqrtq_v: assert(!cir::MissingFeatures::emitConstrainedFPCall()); return emitNeonCall(cgm, builder, {ty}, ops, "sqrt", ty, loc); - case NEON::BI__builtin_neon_vmaxv_f16: { - cir::VectorType vecTy = cir::VectorType::get(fP16Ty, 4); - return emitNeonCall(cgm, builder, {vecTy}, ops, "aarch64.neon.fmaxv", - fP16Ty, loc); - } - case NEON::BI__builtin_neon_vmaxvq_f16: { - cir::VectorType vecTy = cir::VectorType::get(fP16Ty, 8); - return emitNeonCall(cgm, builder, {vecTy}, ops, "aarch64.neon.fmaxv", - fP16Ty, loc); - } case NEON::BI__builtin_neon_vrbit_v: case NEON::BI__builtin_neon_vrbitq_v: + case NEON::BI__builtin_neon_vmaxv_f16: + case NEON::BI__builtin_neon_vmaxvq_f16: case NEON::BI__builtin_neon_vminv_f16: case NEON::BI__builtin_neon_vminvq_f16: case NEON::BI__builtin_neon_vmaxnmv_f16: >From 5a674b07c9b997601b934ede67da944e7180bacb Mon Sep 17 00:00:00 2001 From: Kartik Ohlan <[email protected]> Date: Tue, 12 May 2026 00:09:42 -0400 Subject: [PATCH 3/4] added vmaxv --- clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index c142b69f6be6e..dbff2d91af4ba 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -354,6 +354,22 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr( case NEON::BI__builtin_neon_vrecpxh_f16: case NEON::BI__builtin_neon_vrsqrteh_f16: case NEON::BI__builtin_neon_vrsqrtsh_f16: + case NEON::BI__builtin_neon_vmaxv_s8: + case NEON::BI__builtin_neon_vmaxv_s8: + case NEON::BI__builtin_neon_vmaxvq_s8: + case NEON::BI__builtin_neon_vmaxv_s16: + case NEON::BI__builtin_neon_vmaxvq_s16: + case NEON::BI__builtin_neon_vmaxv_s32: + case NEON::BI__builtin_neon_vmaxvq_s32: + case NEON::BI__builtin_neon_vmaxv_u8: + case NEON::BI__builtin_neon_vmaxvq_u8: + case NEON::BI__builtin_neon_vmaxv_u16: + case NEON::BI__builtin_neon_vmaxvq_u16: + case NEON::BI__builtin_neon_vmaxv_u32: + case NEON::BI__builtin_neon_vmaxvq_u32: + case NEON::BI__builtin_neon_vmaxv_f32: + case NEON::BI__builtin_neon_vmaxvq_f32: + case NEON::BI__builtin_neon_vmaxvq_f64: return emitNeonCall(cgf.cgm, cgf.getBuilder(), {cgf.convertType(expr->getArg(0)->getType())}, ops, llvmIntrName, cgf.convertType(expr->getType()), loc); >From 62d2d506e173b8aa591cf2ca3c82e90a9b3de954 Mon Sep 17 00:00:00 2001 From: Kartik Ohlan <[email protected]> Date: Tue, 12 May 2026 00:25:26 -0400 Subject: [PATCH 4/4] Added vmaxv --- clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index dbff2d91af4ba..0f7bcedc59d42 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -355,7 +355,6 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr( case NEON::BI__builtin_neon_vrsqrteh_f16: case NEON::BI__builtin_neon_vrsqrtsh_f16: case NEON::BI__builtin_neon_vmaxv_s8: - case NEON::BI__builtin_neon_vmaxv_s8: case NEON::BI__builtin_neon_vmaxvq_s8: case NEON::BI__builtin_neon_vmaxv_s16: case NEON::BI__builtin_neon_vmaxvq_s16: _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
