github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code.
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<details>
<summary>
You can test this locally with the following command:
</summary>
``````````bash
git-clang-format --diff origin/main HEAD --extensions cl --
libclc/test/conversion/convert.cl libclc/test/geometric/cross.cl
libclc/test/integer/add_sat.cl libclc/test/integer/sub_sat.cl
libclc/test/math/cos.cl libclc/test/math/fabs.cl libclc/test/math/rsqrt.cl
libclc/test/misc/as_type.cl libclc/test/work-item/get_group_id.cl
--diff_from_common_commit
``````````
:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:
</details>
<details>
<summary>
View the diff from clang-format here.
</summary>
``````````diff
diff --git a/libclc/test/conversion/convert.cl
b/libclc/test/conversion/convert.cl
index 00b524bb8..d8a482c38 100644
--- a/libclc/test/conversion/convert.cl
+++ b/libclc/test/conversion/convert.cl
@@ -1,14 +1,13 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 6
-// REQUIRES: AMDGCN
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// UTC_ARGS: --version 6 REQUIRES: AMDGCN
-// RUN: %clang -target %libclc_target -O2 -emit-llvm -S -o - %s | FileCheck %s
--check-prefix=%check_prefix
+// RUN: %clang -target %libclc_target -O2 -emit-llvm -S -o - %s | FileCheck %s
+// --check-prefix=%check_prefix
// AMDGCN-LABEL: define hidden <4 x i32> @float4_to_int4(
-// AMDGCN-SAME: <4 x float> noundef [[X:%.*]]) local_unnamed_addr
#[[ATTR0:[0-9]+]] {
-// AMDGCN-NEXT: [[ENTRY:.*:]]
-// AMDGCN-NEXT: [[TMP0:%.*]] = fptosi <4 x float> [[X]] to <4 x i32>
-// AMDGCN-NEXT: ret <4 x i32> [[TMP0]]
+// AMDGCN-SAME: <4 x float> noundef [[X:%.*]]) local_unnamed_addr
+// #[[ATTR0:[0-9]+]] { AMDGCN-NEXT: [[ENTRY:.*:]] AMDGCN-NEXT: [[TMP0:%.*]]
+// = fptosi <4 x float> [[X]] to <4 x i32> AMDGCN-NEXT: ret <4 x i32>
+// [[TMP0]]
//
-int4 float4_to_int4(float4 x) {
- return convert_int4(x);
-}
+int4 float4_to_int4(float4 x) { return convert_int4(x); }
diff --git a/libclc/test/geometric/cross.cl b/libclc/test/geometric/cross.cl
index 5aa7541b4..997ad8cc6 100644
--- a/libclc/test/geometric/cross.cl
+++ b/libclc/test/geometric/cross.cl
@@ -1,11 +1,12 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 6
-// REQUIRES: AMDGCN
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// UTC_ARGS: --version 6 REQUIRES: AMDGCN
-// RUN: %clang -target %libclc_target -O2 -emit-llvm -S -o - %s | FileCheck %s
--check-prefix=%check_prefix
+// RUN: %clang -target %libclc_target -O2 -emit-llvm -S -o - %s | FileCheck %s
+// --check-prefix=%check_prefix
// AMDGCN-LABEL: define hidden <4 x float> @test_float4(
-// AMDGCN-SAME: <4 x float> noundef [[X:%.*]], <4 x float> noundef [[Y:%.*]])
local_unnamed_addr #[[ATTR0:[0-9]+]] {
-// AMDGCN-NEXT: [[ENTRY:.*:]]
+// AMDGCN-SAME: <4 x float> noundef [[X:%.*]], <4 x float> noundef [[Y:%.*]])
+// local_unnamed_addr #[[ATTR0:[0-9]+]] { AMDGCN-NEXT: [[ENTRY:.*:]]
// AMDGCN-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[X]], i64 1
// AMDGCN-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[Y]], i64 2
// AMDGCN-NEXT: [[TMP2:%.*]] = fmul contract float [[TMP0]], [[TMP1]]
@@ -21,11 +22,10 @@
// AMDGCN-NEXT: [[TMP12:%.*]] = fmul contract float [[TMP9]], [[TMP4]]
// AMDGCN-NEXT: [[TMP13:%.*]] = fmul contract float [[TMP0]], [[TMP7]]
// AMDGCN-NEXT: [[TMP14:%.*]] = fsub contract float [[TMP12]], [[TMP13]]
-// AMDGCN-NEXT: [[TMP15:%.*]] = insertelement <4 x float> <float poison,
float poison, float poison, float 0.000000e+00>, float [[TMP6]], i64 0
-// AMDGCN-NEXT: [[TMP16:%.*]] = insertelement <4 x float> [[TMP15]], float
[[TMP11]], i64 1
-// AMDGCN-NEXT: [[TMP17:%.*]] = insertelement <4 x float> [[TMP16]], float
[[TMP14]], i64 2
-// AMDGCN-NEXT: ret <4 x float> [[TMP17]]
+// AMDGCN-NEXT: [[TMP15:%.*]] = insertelement <4 x float> <float poison,
+// float poison, float poison, float 0.000000e+00>, float [[TMP6]], i64 0
+// AMDGCN-NEXT: [[TMP16:%.*]] = insertelement <4 x float> [[TMP15]], float
+// [[TMP11]], i64 1 AMDGCN-NEXT: [[TMP17:%.*]] = insertelement <4 x float>
+// [[TMP16]], float [[TMP14]], i64 2 AMDGCN-NEXT: ret <4 x float> [[TMP17]]
//
-float4 test_float4(float4 x, float4 y) {
- return cross(x, y);
-}
+float4 test_float4(float4 x, float4 y) { return cross(x, y); }
diff --git a/libclc/test/integer/add_sat.cl b/libclc/test/integer/add_sat.cl
index 4c3009095..4f876ae58 100644
--- a/libclc/test/integer/add_sat.cl
+++ b/libclc/test/integer/add_sat.cl
@@ -1,14 +1,13 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 6
-// REQUIRES: AMDGCN
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// UTC_ARGS: --version 6 REQUIRES: AMDGCN
-// RUN: %clang -target %libclc_target -O2 -emit-llvm -S -o - %s | FileCheck %s
--check-prefix=%check_prefix
+// RUN: %clang -target %libclc_target -O2 -emit-llvm -S -o - %s | FileCheck %s
+// --check-prefix=%check_prefix
// AMDGCN-LABEL: define hidden noundef signext i8 @test_char(
-// AMDGCN-SAME: i8 noundef signext [[X:%.*]], i8 noundef signext [[Y:%.*]])
local_unnamed_addr #[[ATTR0:[0-9]+]] {
-// AMDGCN-NEXT: [[ENTRY:.*:]]
-// AMDGCN-NEXT: [[TMP0:%.*]] = tail call noundef i8 @llvm.sadd.sat.i8(i8
[[X]], i8 [[Y]])
-// AMDGCN-NEXT: ret i8 [[TMP0]]
+// AMDGCN-SAME: i8 noundef signext [[X:%.*]], i8 noundef signext [[Y:%.*]])
+// local_unnamed_addr #[[ATTR0:[0-9]+]] { AMDGCN-NEXT: [[ENTRY:.*:]]
+// AMDGCN-NEXT: [[TMP0:%.*]] = tail call noundef i8 @llvm.sadd.sat.i8(i8
+// [[X]], i8 [[Y]]) AMDGCN-NEXT: ret i8 [[TMP0]]
//
-char test_char(char x, char y) {
- return add_sat(x, y);
-}
+char test_char(char x, char y) { return add_sat(x, y); }
diff --git a/libclc/test/integer/sub_sat.cl b/libclc/test/integer/sub_sat.cl
index 6573afae4..e5a17aaf6 100644
--- a/libclc/test/integer/sub_sat.cl
+++ b/libclc/test/integer/sub_sat.cl
@@ -1,44 +1,37 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 6
-// REQUIRES: AMDGCN
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// UTC_ARGS: --version 6 REQUIRES: AMDGCN
-// RUN: %clang -target %libclc_target -O2 -emit-llvm -S -o - %s | FileCheck %s
--check-prefix=%check_prefix
+// RUN: %clang -target %libclc_target -O2 -emit-llvm -S -o - %s | FileCheck %s
+// --check-prefix=%check_prefix
// AMDGCN-LABEL: define hidden noundef signext i8 @test_char(
-// AMDGCN-SAME: i8 noundef signext [[X:%.*]], i8 noundef signext [[Y:%.*]])
local_unnamed_addr #[[ATTR0:[0-9]+]] {
-// AMDGCN-NEXT: [[ENTRY:.*:]]
-// AMDGCN-NEXT: [[TMP0:%.*]] = tail call noundef i8 @llvm.ssub.sat.i8(i8
[[X]], i8 [[Y]])
-// AMDGCN-NEXT: ret i8 [[TMP0]]
+// AMDGCN-SAME: i8 noundef signext [[X:%.*]], i8 noundef signext [[Y:%.*]])
+// local_unnamed_addr #[[ATTR0:[0-9]+]] { AMDGCN-NEXT: [[ENTRY:.*:]]
+// AMDGCN-NEXT: [[TMP0:%.*]] = tail call noundef i8 @llvm.ssub.sat.i8(i8
+// [[X]], i8 [[Y]]) AMDGCN-NEXT: ret i8 [[TMP0]]
//
-char test_char(char x, char y) {
- return sub_sat(x, y);
-}
+char test_char(char x, char y) { return sub_sat(x, y); }
// AMDGCN-LABEL: define hidden noundef zeroext i8 @test_uchar(
-// AMDGCN-SAME: i8 noundef zeroext [[X:%.*]], i8 noundef zeroext [[Y:%.*]])
local_unnamed_addr #[[ATTR0]] {
-// AMDGCN-NEXT: [[ENTRY:.*:]]
-// AMDGCN-NEXT: [[TMP0:%.*]] = tail call noundef i8 @llvm.usub.sat.i8(i8
[[X]], i8 [[Y]])
+// AMDGCN-SAME: i8 noundef zeroext [[X:%.*]], i8 noundef zeroext [[Y:%.*]])
+// local_unnamed_addr #[[ATTR0]] { AMDGCN-NEXT: [[ENTRY:.*:]] AMDGCN-NEXT:
+// [[TMP0:%.*]] = tail call noundef i8 @llvm.usub.sat.i8(i8 [[X]], i8 [[Y]])
// AMDGCN-NEXT: ret i8 [[TMP0]]
//
-uchar test_uchar(uchar x, uchar y) {
- return sub_sat(x, y);
-}
+uchar test_uchar(uchar x, uchar y) { return sub_sat(x, y); }
// AMDGCN-LABEL: define hidden noundef i64 @test_long(
-// AMDGCN-SAME: i64 noundef [[X:%.*]], i64 noundef [[Y:%.*]])
local_unnamed_addr #[[ATTR0]] {
-// AMDGCN-NEXT: [[ENTRY:.*:]]
-// AMDGCN-NEXT: [[TMP0:%.*]] = tail call noundef i64 @llvm.ssub.sat.i64(i64
[[X]], i64 [[Y]])
-// AMDGCN-NEXT: ret i64 [[TMP0]]
+// AMDGCN-SAME: i64 noundef [[X:%.*]], i64 noundef [[Y:%.*]])
local_unnamed_addr
+// #[[ATTR0]] { AMDGCN-NEXT: [[ENTRY:.*:]] AMDGCN-NEXT: [[TMP0:%.*]] = tail
+// call noundef i64 @llvm.ssub.sat.i64(i64 [[X]], i64 [[Y]]) AMDGCN-NEXT:
ret
+// i64 [[TMP0]]
//
-long test_long(long x, long y) {
- return sub_sat(x, y);
-}
+long test_long(long x, long y) { return sub_sat(x, y); }
// AMDGCN-LABEL: define hidden noundef i64 @test_ulong(
-// AMDGCN-SAME: i64 noundef [[X:%.*]], i64 noundef [[Y:%.*]])
local_unnamed_addr #[[ATTR0]] {
-// AMDGCN-NEXT: [[ENTRY:.*:]]
-// AMDGCN-NEXT: [[TMP0:%.*]] = tail call noundef i64 @llvm.usub.sat.i64(i64
[[X]], i64 [[Y]])
-// AMDGCN-NEXT: ret i64 [[TMP0]]
+// AMDGCN-SAME: i64 noundef [[X:%.*]], i64 noundef [[Y:%.*]])
local_unnamed_addr
+// #[[ATTR0]] { AMDGCN-NEXT: [[ENTRY:.*:]] AMDGCN-NEXT: [[TMP0:%.*]] = tail
+// call noundef i64 @llvm.usub.sat.i64(i64 [[X]], i64 [[Y]]) AMDGCN-NEXT:
ret
+// i64 [[TMP0]]
//
-ulong test_ulong(ulong x, ulong y) {
- return sub_sat(x, y);
-}
+ulong test_ulong(ulong x, ulong y) { return sub_sat(x, y); }
diff --git a/libclc/test/math/cos.cl b/libclc/test/math/cos.cl
index 311024d71..a7ff26ad4 100644
--- a/libclc/test/math/cos.cl
+++ b/libclc/test/math/cos.cl
@@ -1,32 +1,31 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 6
-// REQUIRES: AMDGCN
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// UTC_ARGS: --version 6 REQUIRES: AMDGCN
-// RUN: %clang -target %libclc_target -O2 -emit-llvm -S -o - %s | FileCheck %s
--check-prefix=%check_prefix
+// RUN: %clang -target %libclc_target -O2 -emit-llvm -S -o - %s | FileCheck %s
+// --check-prefix=%check_prefix
// AMDGCN-LABEL: define hidden float @test_float(
// AMDGCN-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
// AMDGCN-NEXT: [[ENTRY:.*:]]
// AMDGCN-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
// AMDGCN-NEXT: [[TMP1:%.*]] = fcmp une float [[TMP0]], +inf
-// AMDGCN-NEXT: [[TMP2:%.*]] = select contract i1 [[TMP1]], float [[TMP0]],
float +qnan
-// AMDGCN-NEXT: [[TMP3:%.*]] = fcmp ult float [[TMP2]], 1.310720e+05
-// AMDGCN-NEXT: br i1 [[TMP3]], label %[[BB108:.*]], label %[[BB4:.*]]
-// AMDGCN: [[BB4]]:
-// AMDGCN-NEXT: [[TMP5:%.*]] = tail call { float, i32 }
@llvm.frexp.f32.i32(float [[TMP2]])
-// AMDGCN-NEXT: [[TMP6:%.*]] = extractvalue { float, i32 } [[TMP5]], 1
-// AMDGCN-NEXT: [[TMP7:%.*]] = extractvalue { float, i32 } [[TMP5]], 0
-// AMDGCN-NEXT: [[TMP8:%.*]] = fmul contract float [[TMP7]], f0x4B800000
-// AMDGCN-NEXT: [[TMP9:%.*]] = fptoui float [[TMP8]] to i32
-// AMDGCN-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// AMDGCN-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4266746795
-// AMDGCN-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
-// AMDGCN-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP11]], 32
-// AMDGCN-NEXT: [[TMP14:%.*]] = mul nuw nsw i64 [[TMP10]], 1011060801
-// AMDGCN-NEXT: [[TMP15:%.*]] = add nuw nsw i64 [[TMP13]], [[TMP14]]
-// AMDGCN-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i32
-// AMDGCN-NEXT: [[TMP17:%.*]] = lshr i64 [[TMP15]], 32
-// AMDGCN-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP10]], 3680671129
-// AMDGCN-NEXT: [[TMP19:%.*]] = add nuw i64 [[TMP17]], [[TMP18]]
+// AMDGCN-NEXT: [[TMP2:%.*]] = select contract i1 [[TMP1]], float [[TMP0]],
+// float +qnan AMDGCN-NEXT: [[TMP3:%.*]] = fcmp ult float
+// [[TMP2]], 1.310720e+05 AMDGCN-NEXT: br i1 [[TMP3]], label %[[BB108:.*]],
+// label %[[BB4:.*]] AMDGCN: [[BB4]]: AMDGCN-NEXT: [[TMP5:%.*]] = tail
+// call { float, i32 } @llvm.frexp.f32.i32(float [[TMP2]]) AMDGCN-NEXT:
+// [[TMP6:%.*]] = extractvalue { float, i32 } [[TMP5]], 1 AMDGCN-NEXT:
+// [[TMP7:%.*]] = extractvalue { float, i32 } [[TMP5]], 0 AMDGCN-NEXT:
+// [[TMP8:%.*]] = fmul contract float [[TMP7]], f0x4B800000 AMDGCN-NEXT:
+// [[TMP9:%.*]] = fptoui float [[TMP8]] to i32 AMDGCN-NEXT: [[TMP10:%.*]] =
+// zext i32 [[TMP9]] to i64 AMDGCN-NEXT: [[TMP11:%.*]] = mul nuw i64
+// [[TMP10]], 4266746795 AMDGCN-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to
+// i32 AMDGCN-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP11]], 32 AMDGCN-NEXT:
+// [[TMP14:%.*]] = mul nuw nsw i64 [[TMP10]], 1011060801 AMDGCN-NEXT:
+// [[TMP15:%.*]] = add nuw nsw i64 [[TMP13]], [[TMP14]] AMDGCN-NEXT:
+// [[TMP16:%.*]] = trunc i64 [[TMP15]] to i32 AMDGCN-NEXT: [[TMP17:%.*]] =
+// lshr i64 [[TMP15]], 32 AMDGCN-NEXT: [[TMP18:%.*]] = mul nuw i64
[[TMP10]],
+// 3680671129 AMDGCN-NEXT: [[TMP19:%.*]] = add nuw i64 [[TMP17]], [[TMP18]]
// AMDGCN-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32
// AMDGCN-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP19]], 32
// AMDGCN-NEXT: [[TMP22:%.*]] = mul nuw i64 [[TMP10]], 4113882560
@@ -48,63 +47,67 @@
// AMDGCN-NEXT: [[TMP38:%.*]] = trunc nuw i64 [[TMP37]] to i32
// AMDGCN-NEXT: [[TMP39:%.*]] = add nsw i32 [[TMP6]], 6
// AMDGCN-NEXT: [[TMP40:%.*]] = icmp ugt i32 [[TMP39]], 63
-// AMDGCN-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], i32 [[TMP32]], i32
[[TMP38]]
-// AMDGCN-NEXT: [[TMP42:%.*]] = select i1 [[TMP40]], i32 [[TMP28]], i32
[[TMP36]]
-// AMDGCN-NEXT: [[TMP43:%.*]] = select i1 [[TMP40]], i32 [[TMP24]], i32
[[TMP32]]
-// AMDGCN-NEXT: [[TMP44:%.*]] = select i1 [[TMP40]], i32 [[TMP20]], i32
[[TMP28]]
-// AMDGCN-NEXT: [[TMP45:%.*]] = select i1 [[TMP40]], i32 [[TMP16]], i32
[[TMP24]]
-// AMDGCN-NEXT: [[TMP46:%.*]] = select i1 [[TMP40]], i32 [[TMP12]], i32
[[TMP20]]
-// AMDGCN-NEXT: [[TMP47:%.*]] = select i1 [[TMP40]], i32 -64, i32 0
-// AMDGCN-NEXT: [[TMP48:%.*]] = add i32 [[TMP47]], [[TMP39]]
-// AMDGCN-NEXT: [[TMP49:%.*]] = icmp ugt i32 [[TMP48]], 31
-// AMDGCN-NEXT: [[TMP50:%.*]] = select i1 [[TMP49]], i32 [[TMP42]], i32
[[TMP41]]
-// AMDGCN-NEXT: [[TMP51:%.*]] = select i1 [[TMP49]], i32 [[TMP43]], i32
[[TMP42]]
-// AMDGCN-NEXT: [[TMP52:%.*]] = select i1 [[TMP49]], i32 [[TMP44]], i32
[[TMP43]]
-// AMDGCN-NEXT: [[TMP53:%.*]] = select i1 [[TMP49]], i32 [[TMP45]], i32
[[TMP44]]
-// AMDGCN-NEXT: [[TMP54:%.*]] = select i1 [[TMP49]], i32 [[TMP46]], i32
[[TMP45]]
-// AMDGCN-NEXT: [[TMP55:%.*]] = select i1 [[TMP49]], i32 -32, i32 0
-// AMDGCN-NEXT: [[TMP56:%.*]] = add i32 [[TMP55]], [[TMP48]]
-// AMDGCN-NEXT: [[TMP57:%.*]] = icmp ugt i32 [[TMP56]], 31
-// AMDGCN-NEXT: [[TMP58:%.*]] = select i1 [[TMP57]], i32 [[TMP51]], i32
[[TMP50]]
-// AMDGCN-NEXT: [[TMP59:%.*]] = select i1 [[TMP57]], i32 [[TMP52]], i32
[[TMP51]]
-// AMDGCN-NEXT: [[TMP60:%.*]] = select i1 [[TMP57]], i32 [[TMP53]], i32
[[TMP52]]
-// AMDGCN-NEXT: [[TMP61:%.*]] = select i1 [[TMP57]], i32 [[TMP54]], i32
[[TMP53]]
-// AMDGCN-NEXT: [[TMP62:%.*]] = select i1 [[TMP57]], i32 -32, i32 0
-// AMDGCN-NEXT: [[TMP63:%.*]] = add i32 [[TMP62]], [[TMP56]]
-// AMDGCN-NEXT: [[TMP64:%.*]] = icmp eq i32 [[TMP63]], 0
+// AMDGCN-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], i32 [[TMP32]], i32
+// [[TMP38]] AMDGCN-NEXT: [[TMP42:%.*]] = select i1 [[TMP40]], i32
[[TMP28]],
+// i32 [[TMP36]] AMDGCN-NEXT: [[TMP43:%.*]] = select i1 [[TMP40]], i32
+// [[TMP24]], i32 [[TMP32]] AMDGCN-NEXT: [[TMP44:%.*]] = select i1
[[TMP40]],
+// i32 [[TMP20]], i32 [[TMP28]] AMDGCN-NEXT: [[TMP45:%.*]] = select i1
+// [[TMP40]], i32 [[TMP16]], i32 [[TMP24]] AMDGCN-NEXT: [[TMP46:%.*]] =
+// select i1 [[TMP40]], i32 [[TMP12]], i32 [[TMP20]] AMDGCN-NEXT: [[TMP47:%.*]]
+// = select i1 [[TMP40]], i32 -64, i32 0 AMDGCN-NEXT: [[TMP48:%.*]] = add
i32
+// [[TMP47]], [[TMP39]] AMDGCN-NEXT: [[TMP49:%.*]] = icmp ugt i32 [[TMP48]],
+// 31 AMDGCN-NEXT: [[TMP50:%.*]] = select i1 [[TMP49]], i32 [[TMP42]], i32
+// [[TMP41]] AMDGCN-NEXT: [[TMP51:%.*]] = select i1 [[TMP49]], i32
[[TMP43]],
+// i32 [[TMP42]] AMDGCN-NEXT: [[TMP52:%.*]] = select i1 [[TMP49]], i32
+// [[TMP44]], i32 [[TMP43]] AMDGCN-NEXT: [[TMP53:%.*]] = select i1
[[TMP49]],
+// i32 [[TMP45]], i32 [[TMP44]] AMDGCN-NEXT: [[TMP54:%.*]] = select i1
+// [[TMP49]], i32 [[TMP46]], i32 [[TMP45]] AMDGCN-NEXT: [[TMP55:%.*]] =
+// select i1 [[TMP49]], i32 -32, i32 0 AMDGCN-NEXT: [[TMP56:%.*]] = add i32
+// [[TMP55]], [[TMP48]] AMDGCN-NEXT: [[TMP57:%.*]] = icmp ugt i32 [[TMP56]],
+// 31 AMDGCN-NEXT: [[TMP58:%.*]] = select i1 [[TMP57]], i32 [[TMP51]], i32
+// [[TMP50]] AMDGCN-NEXT: [[TMP59:%.*]] = select i1 [[TMP57]], i32
[[TMP52]],
+// i32 [[TMP51]] AMDGCN-NEXT: [[TMP60:%.*]] = select i1 [[TMP57]], i32
+// [[TMP53]], i32 [[TMP52]] AMDGCN-NEXT: [[TMP61:%.*]] = select i1
[[TMP57]],
+// i32 [[TMP54]], i32 [[TMP53]] AMDGCN-NEXT: [[TMP62:%.*]] = select i1
+// [[TMP57]], i32 -32, i32 0 AMDGCN-NEXT: [[TMP63:%.*]] = add i32 [[TMP62]],
+// [[TMP56]] AMDGCN-NEXT: [[TMP64:%.*]] = icmp eq i32 [[TMP63]], 0
// AMDGCN-NEXT: [[TMP65:%.*]] = sub i32 32, [[TMP63]]
-// AMDGCN-NEXT: [[TMP66:%.*]] = tail call i32 @llvm.fshr.i32(i32 [[TMP58]],
i32 [[TMP59]], i32 [[TMP65]])
-// AMDGCN-NEXT: [[TMP67:%.*]] = tail call i32 @llvm.fshr.i32(i32 [[TMP59]],
i32 [[TMP60]], i32 [[TMP65]])
-// AMDGCN-NEXT: [[TMP68:%.*]] = tail call i32 @llvm.fshr.i32(i32 [[TMP60]],
i32 [[TMP61]], i32 [[TMP65]])
-// AMDGCN-NEXT: [[TMP69:%.*]] = select i1 [[TMP64]], i32 [[TMP58]], i32
[[TMP66]]
-// AMDGCN-NEXT: [[TMP70:%.*]] = select i1 [[TMP64]], i32 [[TMP59]], i32
[[TMP67]]
-// AMDGCN-NEXT: [[TMP71:%.*]] = select i1 [[TMP64]], i32 [[TMP60]], i32
[[TMP68]]
-// AMDGCN-NEXT: [[TMP72:%.*]] = lshr i32 [[TMP69]], 29
-// AMDGCN-NEXT: [[TMP73:%.*]] = tail call i32 @llvm.fshl.i32(i32 [[TMP69]],
i32 [[TMP70]], i32 2)
-// AMDGCN-NEXT: [[TMP74:%.*]] = tail call i32 @llvm.fshl.i32(i32 [[TMP70]],
i32 [[TMP71]], i32 2)
-// AMDGCN-NEXT: [[TMP75:%.*]] = tail call i32 @llvm.fshl.i32(i32 [[TMP71]],
i32 [[TMP61]], i32 2)
-// AMDGCN-NEXT: [[TMP76:%.*]] = and i32 [[TMP72]], 1
-// AMDGCN-NEXT: [[TMP77:%.*]] = sub nsw i32 0, [[TMP76]]
+// AMDGCN-NEXT: [[TMP66:%.*]] = tail call i32 @llvm.fshr.i32(i32 [[TMP58]],
+// i32 [[TMP59]], i32 [[TMP65]]) AMDGCN-NEXT: [[TMP67:%.*]] = tail call i32
+// @llvm.fshr.i32(i32 [[TMP59]], i32 [[TMP60]], i32 [[TMP65]]) AMDGCN-NEXT:
+// [[TMP68:%.*]] = tail call i32 @llvm.fshr.i32(i32 [[TMP60]], i32 [[TMP61]],
+// i32 [[TMP65]]) AMDGCN-NEXT: [[TMP69:%.*]] = select i1 [[TMP64]], i32
+// [[TMP58]], i32 [[TMP66]] AMDGCN-NEXT: [[TMP70:%.*]] = select i1
[[TMP64]],
+// i32 [[TMP59]], i32 [[TMP67]] AMDGCN-NEXT: [[TMP71:%.*]] = select i1
+// [[TMP64]], i32 [[TMP60]], i32 [[TMP68]] AMDGCN-NEXT: [[TMP72:%.*]] = lshr
+// i32 [[TMP69]], 29 AMDGCN-NEXT: [[TMP73:%.*]] = tail call i32
+// @llvm.fshl.i32(i32 [[TMP69]], i32 [[TMP70]], i32 2) AMDGCN-NEXT:
+// [[TMP74:%.*]] = tail call i32 @llvm.fshl.i32(i32 [[TMP70]], i32 [[TMP71]],
+// i32 2) AMDGCN-NEXT: [[TMP75:%.*]] = tail call i32 @llvm.fshl.i32(i32
+// [[TMP71]], i32 [[TMP61]], i32 2) AMDGCN-NEXT: [[TMP76:%.*]] = and i32
+// [[TMP72]], 1 AMDGCN-NEXT: [[TMP77:%.*]] = sub nsw i32 0, [[TMP76]]
// AMDGCN-NEXT: [[TMP78:%.*]] = shl i32 [[TMP72]], 31
// AMDGCN-NEXT: [[TMP79:%.*]] = xor i32 [[TMP73]], [[TMP77]]
// AMDGCN-NEXT: [[TMP80:%.*]] = xor i32 [[TMP74]], [[TMP77]]
// AMDGCN-NEXT: [[TMP81:%.*]] = xor i32 [[TMP75]], [[TMP77]]
-// AMDGCN-NEXT: [[TMP82:%.*]] = tail call range(i32 0, 33) i32
@llvm.ctlz.i32(i32 [[TMP79]], i1 false)
-// AMDGCN-NEXT: [[DOTNEG_I_I_I_I:%.*]] = xor i32 [[TMP82]], -1
-// AMDGCN-NEXT: [[TMP83:%.*]] = sub nsw i32 31, [[TMP82]]
-// AMDGCN-NEXT: [[TMP84:%.*]] = tail call i32 @llvm.fshr.i32(i32 [[TMP79]],
i32 [[TMP80]], i32 [[TMP83]])
-// AMDGCN-NEXT: [[TMP85:%.*]] = tail call i32 @llvm.fshr.i32(i32 [[TMP80]],
i32 [[TMP81]], i32 [[TMP83]])
+// AMDGCN-NEXT: [[TMP82:%.*]] = tail call range(i32 0, 33) i32
+// @llvm.ctlz.i32(i32 [[TMP79]], i1 false) AMDGCN-NEXT: [[DOTNEG_I_I_I_I:%.*]]
=
+// xor i32 [[TMP82]], -1 AMDGCN-NEXT: [[TMP83:%.*]] = sub nsw i32 31,
+// [[TMP82]] AMDGCN-NEXT: [[TMP84:%.*]] = tail call i32 @llvm.fshr.i32(i32
+// [[TMP79]], i32 [[TMP80]], i32 [[TMP83]]) AMDGCN-NEXT: [[TMP85:%.*]] =
tail
+// call i32 @llvm.fshr.i32(i32 [[TMP80]], i32 [[TMP81]], i32 [[TMP83]])
// AMDGCN-NEXT: [[TMP86:%.*]] = lshr i32 [[TMP84]], 9
// AMDGCN-NEXT: [[TMP87:%.*]] = shl nuw nsw i32 [[TMP82]], 23
// AMDGCN-NEXT: [[REASS_SUB:%.*]] = sub nsw i32 [[TMP86]], [[TMP87]]
// AMDGCN-NEXT: [[TMP88:%.*]] = add nsw i32 [[REASS_SUB]], 1056964608
// AMDGCN-NEXT: [[TMP89:%.*]] = or i32 [[TMP88]], [[TMP78]]
// AMDGCN-NEXT: [[TMP90:%.*]] = bitcast i32 [[TMP89]] to float
-// AMDGCN-NEXT: [[TMP91:%.*]] = tail call i32 @llvm.fshl.i32(i32 [[TMP84]],
i32 [[TMP85]], i32 23)
-// AMDGCN-NEXT: [[TMP92:%.*]] = tail call range(i32 0, 33) i32
@llvm.ctlz.i32(i32 [[TMP91]], i1 false)
-// AMDGCN-NEXT: [[TMP93:%.*]] = xor i32 [[TMP92]], -1
-// AMDGCN-NEXT: [[TMP94:%.*]] = tail call i32 @llvm.fshr.i32(i32 [[TMP91]],
i32 [[TMP85]], i32 [[TMP93]])
-// AMDGCN-NEXT: [[DOTNEG3_I_I_I_I:%.*]] = sub nuw nsw i32
[[DOTNEG_I_I_I_I]], [[TMP92]]
+// AMDGCN-NEXT: [[TMP91:%.*]] = tail call i32 @llvm.fshl.i32(i32 [[TMP84]],
+// i32 [[TMP85]], i32 23) AMDGCN-NEXT: [[TMP92:%.*]] = tail call range(i32
0,
+// 33) i32 @llvm.ctlz.i32(i32 [[TMP91]], i1 false) AMDGCN-NEXT:
[[TMP93:%.*]]
+// = xor i32 [[TMP92]], -1 AMDGCN-NEXT: [[TMP94:%.*]] = tail call i32
+// @llvm.fshr.i32(i32 [[TMP91]], i32 [[TMP85]], i32 [[TMP93]]) AMDGCN-NEXT:
+// [[DOTNEG3_I_I_I_I:%.*]] = sub nuw nsw i32 [[DOTNEG_I_I_I_I]], [[TMP92]]
// AMDGCN-NEXT: [[TMP95:%.*]] = lshr i32 [[TMP94]], 9
// AMDGCN-NEXT: [[DOTNEG4_I_I_I_I:%.*]] = shl nsw i32 [[DOTNEG3_I_I_I_I]],
23
// AMDGCN-NEXT: [[TMP96:%.*]] = add nsw i32 [[DOTNEG4_I_I_I_I]], 864026624
@@ -113,44 +116,56 @@
// AMDGCN-NEXT: [[TMP99:%.*]] = bitcast i32 [[TMP98]] to float
// AMDGCN-NEXT: [[TMP100:%.*]] = fmul float [[TMP90]], f0x3FC90FDA
// AMDGCN-NEXT: [[TMP101:%.*]] = fneg contract float [[TMP100]]
-// AMDGCN-NEXT: [[TMP102:%.*]] = tail call contract noundef float
@llvm.fma.f32(float [[TMP90]], float f0x3FC90FDA, float [[TMP101]])
-// AMDGCN-NEXT: [[TMP103:%.*]] = tail call contract noundef float
@llvm.fma.f32(float [[TMP90]], float f0x33A22168, float [[TMP102]])
-// AMDGCN-NEXT: [[TMP104:%.*]] = tail call contract noundef float
@llvm.fma.f32(float [[TMP99]], float f0x3FC90FDA, float [[TMP103]])
+// AMDGCN-NEXT: [[TMP102:%.*]] = tail call contract noundef float
+// @llvm.fma.f32(float [[TMP90]], float f0x3FC90FDA, float [[TMP101]])
+// AMDGCN-NEXT: [[TMP103:%.*]] = tail call contract noundef float
+// @llvm.fma.f32(float [[TMP90]], float f0x33A22168, float [[TMP102]])
+// AMDGCN-NEXT: [[TMP104:%.*]] = tail call contract noundef float
+// @llvm.fma.f32(float [[TMP99]], float f0x3FC90FDA, float [[TMP103]])
// AMDGCN-NEXT: [[TMP105:%.*]] = fadd float [[TMP100]], [[TMP104]]
// AMDGCN-NEXT: [[TMP106:%.*]] = lshr i32 [[TMP69]], 30
// AMDGCN-NEXT: [[TMP107:%.*]] = add nuw nsw i32 [[TMP76]], [[TMP106]]
// AMDGCN-NEXT: br label %[[_Z3COSF_EXIT:.*]]
// AMDGCN: [[BB108]]:
// AMDGCN-NEXT: [[TMP109:%.*]] = fmul float [[TMP2]], f0x3F22F983
-// AMDGCN-NEXT: [[TMP110:%.*]] = tail call contract noundef float
@llvm.rint.f32(float [[TMP109]])
-// AMDGCN-NEXT: [[TMP111:%.*]] = tail call contract noundef float
@llvm.fma.f32(float [[TMP110]], float f0xBFC90FDA, float [[TMP2]])
-// AMDGCN-NEXT: [[TMP112:%.*]] = tail call contract noundef float
@llvm.fma.f32(float [[TMP110]], float f0xB3A22168, float [[TMP111]])
-// AMDGCN-NEXT: [[TMP113:%.*]] = tail call contract noundef float
@llvm.fma.f32(float [[TMP110]], float f0xA7C234C4, float [[TMP112]])
+// AMDGCN-NEXT: [[TMP110:%.*]] = tail call contract noundef float
+// @llvm.rint.f32(float [[TMP109]]) AMDGCN-NEXT: [[TMP111:%.*]] = tail call
+// contract noundef float @llvm.fma.f32(float [[TMP110]], float f0xBFC90FDA,
+// float [[TMP2]]) AMDGCN-NEXT: [[TMP112:%.*]] = tail call contract noundef
+// float @llvm.fma.f32(float [[TMP110]], float f0xB3A22168, float [[TMP111]])
+// AMDGCN-NEXT: [[TMP113:%.*]] = tail call contract noundef float
+// @llvm.fma.f32(float [[TMP110]], float f0xA7C234C4, float [[TMP112]])
// AMDGCN-NEXT: [[TMP114:%.*]] = fptosi float [[TMP110]] to i32
// AMDGCN-NEXT: br label %[[_Z3COSF_EXIT]]
// AMDGCN: [[_Z3COSF_EXIT]]:
-// AMDGCN-NEXT: [[DOTSINK_I_I_I_I:%.*]] = phi float [ [[TMP113]],
%[[BB108]] ], [ [[TMP105]], %[[BB4]] ]
-// AMDGCN-NEXT: [[TMP115:%.*]] = phi i32 [ [[TMP114]], %[[BB108]] ], [
[[TMP107]], %[[BB4]] ]
-// AMDGCN-NEXT: [[TMP116:%.*]] = fmul float [[DOTSINK_I_I_I_I]],
[[DOTSINK_I_I_I_I]]
-// AMDGCN-NEXT: [[TMP117:%.*]] = tail call noundef float
@llvm.fmuladd.f32(float [[TMP116]], float f0xB94C1982, float f0x3C0881C4)
-// AMDGCN-NEXT: [[TMP118:%.*]] = tail call noundef float
@llvm.fmuladd.f32(float [[TMP116]], float [[TMP117]], float f0xBE2AAA9D)
+// AMDGCN-NEXT: [[DOTSINK_I_I_I_I:%.*]] = phi float [ [[TMP113]], %[[BB108]]
+// ], [ [[TMP105]], %[[BB4]] ] AMDGCN-NEXT: [[TMP115:%.*]] = phi i32 [
+// [[TMP114]], %[[BB108]] ], [ [[TMP107]], %[[BB4]] ] AMDGCN-NEXT:
+// [[TMP116:%.*]] = fmul float [[DOTSINK_I_I_I_I]], [[DOTSINK_I_I_I_I]]
+// AMDGCN-NEXT: [[TMP117:%.*]] = tail call noundef float
+// @llvm.fmuladd.f32(float [[TMP116]], float f0xB94C1982, float f0x3C0881C4)
+// AMDGCN-NEXT: [[TMP118:%.*]] = tail call noundef float
+// @llvm.fmuladd.f32(float [[TMP116]], float [[TMP117]], float f0xBE2AAA9D)
// AMDGCN-NEXT: [[TMP119:%.*]] = fmul float [[TMP116]], [[TMP118]]
-// AMDGCN-NEXT: [[TMP120:%.*]] = tail call noundef float
@llvm.fmuladd.f32(float [[DOTSINK_I_I_I_I]], float [[TMP119]], float
[[DOTSINK_I_I_I_I]])
-// AMDGCN-NEXT: [[TMP121:%.*]] = tail call noundef float
@llvm.fmuladd.f32(float [[TMP116]], float f0x37D75334, float f0xBAB64F3B)
-// AMDGCN-NEXT: [[TMP122:%.*]] = tail call noundef float
@llvm.fmuladd.f32(float [[TMP116]], float [[TMP121]], float f0x3D2AABF7)
-// AMDGCN-NEXT: [[TMP123:%.*]] = tail call noundef float
@llvm.fmuladd.f32(float [[TMP116]], float [[TMP122]], float f0xBF000004)
-// AMDGCN-NEXT: [[TMP124:%.*]] = tail call noundef float
@llvm.fmuladd.f32(float [[TMP116]], float [[TMP123]], float 1.000000e+00)
+// AMDGCN-NEXT: [[TMP120:%.*]] = tail call noundef float
+// @llvm.fmuladd.f32(float [[DOTSINK_I_I_I_I]], float [[TMP119]], float
+// [[DOTSINK_I_I_I_I]]) AMDGCN-NEXT: [[TMP121:%.*]] = tail call noundef
float
+// @llvm.fmuladd.f32(float [[TMP116]], float f0x37D75334, float f0xBAB64F3B)
+// AMDGCN-NEXT: [[TMP122:%.*]] = tail call noundef float
+// @llvm.fmuladd.f32(float [[TMP116]], float [[TMP121]], float f0x3D2AABF7)
+// AMDGCN-NEXT: [[TMP123:%.*]] = tail call noundef float
+// @llvm.fmuladd.f32(float [[TMP116]], float [[TMP122]], float f0xBF000004)
+// AMDGCN-NEXT: [[TMP124:%.*]] = tail call noundef float
+// @llvm.fmuladd.f32(float [[TMP116]], float [[TMP123]], float 1.000000e+00)
// AMDGCN-NEXT: [[TMP125:%.*]] = and i32 [[TMP115]], 1
// AMDGCN-NEXT: [[TMP126:%.*]] = icmp eq i32 [[TMP125]], 0
// AMDGCN-NEXT: [[TMP127:%.*]] = shl i32 [[TMP115]], 30
// AMDGCN-NEXT: [[TMP128:%.*]] = and i32 [[TMP127]], -2147483648
// AMDGCN-NEXT: [[TMP129:%.*]] = fneg contract float [[TMP120]]
-// AMDGCN-NEXT: [[TMP130:%.*]] = select contract i1 [[TMP126]], float
[[TMP124]], float [[TMP129]]
-// AMDGCN-NEXT: [[TMP131:%.*]] = bitcast float [[TMP130]] to i32
-// AMDGCN-NEXT: [[TMP132:%.*]] = xor i32 [[TMP128]], [[TMP131]]
-// AMDGCN-NEXT: [[TMP133:%.*]] = bitcast i32 [[TMP132]] to float
+// AMDGCN-NEXT: [[TMP130:%.*]] = select contract i1 [[TMP126]], float
+// [[TMP124]], float [[TMP129]] AMDGCN-NEXT: [[TMP131:%.*]] = bitcast float
+// [[TMP130]] to i32 AMDGCN-NEXT: [[TMP132:%.*]] = xor i32 [[TMP128]],
+// [[TMP131]] AMDGCN-NEXT: [[TMP133:%.*]] = bitcast i32 [[TMP132]] to float
// AMDGCN-NEXT: ret float [[TMP133]]
//
-float test_float(float x) {
- return cos(x);
-}
+float test_float(float x) { return cos(x); }
diff --git a/libclc/test/math/fabs.cl b/libclc/test/math/fabs.cl
index 8b2e34ad5..284be4a71 100644
--- a/libclc/test/math/fabs.cl
+++ b/libclc/test/math/fabs.cl
@@ -1,14 +1,13 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 6
-// REQUIRES: AMDGCN
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// UTC_ARGS: --version 6 REQUIRES: AMDGCN
-// RUN: %clang -target %libclc_target -O2 -emit-llvm -S -o - %s | FileCheck %s
--check-prefix=%check_prefix
+// RUN: %clang -target %libclc_target -O2 -emit-llvm -S -o - %s | FileCheck %s
+// --check-prefix=%check_prefix
// AMDGCN-LABEL: define hidden noundef float @test_float(
// AMDGCN-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
// AMDGCN-NEXT: [[ENTRY:.*:]]
-// AMDGCN-NEXT: [[CALL:%.*]] = tail call fastcc float @llvm.fabs.f32(float
noundef [[X]]) #[[ATTR2:[0-9]+]]
-// AMDGCN-NEXT: ret float [[CALL]]
+// AMDGCN-NEXT: [[CALL:%.*]] = tail call fastcc float @llvm.fabs.f32(float
+// noundef [[X]]) #[[ATTR2:[0-9]+]] AMDGCN-NEXT: ret float [[CALL]]
//
-float test_float(float x) {
- return fabs(x);
-}
+float test_float(float x) { return fabs(x); }
diff --git a/libclc/test/math/rsqrt.cl b/libclc/test/math/rsqrt.cl
index f36e6a01e..14cfc2829 100644
--- a/libclc/test/math/rsqrt.cl
+++ b/libclc/test/math/rsqrt.cl
@@ -1,42 +1,39 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 6
-// REQUIRES: AMDGCN
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// UTC_ARGS: --version 6 REQUIRES: AMDGCN
-// RUN: %clang -target %libclc_target -O2 -emit-llvm -S -o - %s | FileCheck %s
--check-prefix=%check_prefix
+// RUN: %clang -target %libclc_target -O2 -emit-llvm -S -o - %s | FileCheck %s
+// --check-prefix=%check_prefix
#pragma OPENCL EXTENSION cl_khr_fp16 : enable
// AMDGCN-LABEL: define hidden noundef half @test_half(
// AMDGCN-SAME: half noundef [[X:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
// AMDGCN-NEXT: [[ENTRY:.*:]]
-// AMDGCN-NEXT: [[TMP0:%.*]] = tail call contract half @llvm.sqrt.f16(half
[[X]]), !fpmath [[META13:![0-9]+]]
-// AMDGCN-NEXT: [[TMP1:%.*]] = fdiv contract half 1.000000e+00, [[TMP0]],
!fpmath [[META14:![0-9]+]]
-// AMDGCN-NEXT: ret half [[TMP1]]
+// AMDGCN-NEXT: [[TMP0:%.*]] = tail call contract half @llvm.sqrt.f16(half
+// [[X]]), !fpmath [[META13:![0-9]+]] AMDGCN-NEXT: [[TMP1:%.*]] = fdiv
+// contract half 1.000000e+00, [[TMP0]], !fpmath [[META14:![0-9]+]]
AMDGCN-NEXT:
+// ret half [[TMP1]]
//
-half test_half(half x) {
- return rsqrt(x);
-}
+half test_half(half x) { return rsqrt(x); }
// AMDGCN-LABEL: define hidden noundef float @test_float(
// AMDGCN-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AMDGCN-NEXT: [[ENTRY:.*:]]
-// AMDGCN-NEXT: [[TMP0:%.*]] = tail call contract float
@llvm.sqrt.f32(float [[X]]), !fpmath [[META15:![0-9]+]]
-// AMDGCN-NEXT: [[TMP1:%.*]] = fdiv contract float 1.000000e+00, [[TMP0]],
!fpmath [[META16:![0-9]+]]
+// AMDGCN-NEXT: [[TMP0:%.*]] = tail call contract float @llvm.sqrt.f32(float
+// [[X]]), !fpmath [[META15:![0-9]+]] AMDGCN-NEXT: [[TMP1:%.*]] = fdiv
+// contract float 1.000000e+00, [[TMP0]], !fpmath [[META16:![0-9]+]]
// AMDGCN-NEXT: ret float [[TMP1]]
//
-float test_float(float x) {
- return rsqrt(x);
-}
+float test_float(float x) { return rsqrt(x); }
// AMDGCN-LABEL: define hidden noundef double @test_double(
// AMDGCN-SAME: double noundef [[X:%.*]]) local_unnamed_addr #[[ATTR0]] {
// AMDGCN-NEXT: [[ENTRY:.*:]]
-// AMDGCN-NEXT: [[TMP0:%.*]] = tail call contract double
@llvm.sqrt.f64(double [[X]])
-// AMDGCN-NEXT: [[TMP1:%.*]] = fdiv contract double 1.000000e+00, [[TMP0]]
-// AMDGCN-NEXT: ret double [[TMP1]]
+// AMDGCN-NEXT: [[TMP0:%.*]] = tail call contract double
+// @llvm.sqrt.f64(double [[X]]) AMDGCN-NEXT: [[TMP1:%.*]] = fdiv contract
+// double 1.000000e+00, [[TMP0]] AMDGCN-NEXT: ret double [[TMP1]]
//
-double test_double(double x) {
- return rsqrt(x);
-}
+double test_double(double x) { return rsqrt(x); }
//.
// AMDGCN: [[META13]] = !{float 1.500000e+00}
// AMDGCN: [[META14]] = !{float 1.000000e+00}
diff --git a/libclc/test/misc/as_type.cl b/libclc/test/misc/as_type.cl
index d5c41b151..78d827454 100644
--- a/libclc/test/misc/as_type.cl
+++ b/libclc/test/misc/as_type.cl
@@ -1,14 +1,13 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 6
-// REQUIRES: AMDGCN
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// UTC_ARGS: --version 6 REQUIRES: AMDGCN
-// RUN: %clang -target %libclc_target -O2 -emit-llvm -S -o - %s | FileCheck %s
--check-prefix=%check_prefix
+// RUN: %clang -target %libclc_target -O2 -emit-llvm -S -o - %s | FileCheck %s
+// --check-prefix=%check_prefix
// AMDGCN-LABEL: define hidden noundef <4 x i32> @test_float4_as_int4(
-// AMDGCN-SAME: <4 x float> noundef [[X:%.*]]) local_unnamed_addr
#[[ATTR0:[0-9]+]] {
-// AMDGCN-NEXT: [[ENTRY:.*:]]
-// AMDGCN-NEXT: [[ASTYPE:%.*]] = bitcast <4 x float> [[X]] to <4 x i32>
-// AMDGCN-NEXT: ret <4 x i32> [[ASTYPE]]
+// AMDGCN-SAME: <4 x float> noundef [[X:%.*]]) local_unnamed_addr
+// #[[ATTR0:[0-9]+]] { AMDGCN-NEXT: [[ENTRY:.*:]] AMDGCN-NEXT: [[ASTYPE:%.*]]
=
+// bitcast <4 x float> [[X]] to <4 x i32> AMDGCN-NEXT: ret <4 x i32>
+// [[ASTYPE]]
//
-int4 test_float4_as_int4(float4 x) {
- return as_int4(x);
-}
+int4 test_float4_as_int4(float4 x) { return as_int4(x); }
diff --git a/libclc/test/work-item/get_group_id.cl
b/libclc/test/work-item/get_group_id.cl
index 57e3d6878..11203ed58 100644
--- a/libclc/test/work-item/get_group_id.cl
+++ b/libclc/test/work-item/get_group_id.cl
@@ -1,7 +1,8 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 6
-// REQUIRES: AMDGCN
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// UTC_ARGS: --version 6 REQUIRES: AMDGCN
-// RUN: %clang -target %libclc_target -O2 -emit-llvm -S -o - %s | FileCheck %s
--check-prefix=%check_prefix
+// RUN: %clang -target %libclc_target -O2 -emit-llvm -S -o - %s | FileCheck %s
+// --check-prefix=%check_prefix
// AMDGCN-LABEL: define hidden range(i64 0, 4294967296) i64 @test(
// AMDGCN-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] {
@@ -10,6 +11,4 @@
// AMDGCN-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// AMDGCN-NEXT: ret i64 [[TMP1]]
//
-size_t test() {
- return get_group_id(0);
-}
+size_t test() { return get_group_id(0); }
``````````
</details>
https://github.com/llvm/llvm-project/pull/197151
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