https://github.com/quic-garvgupt updated https://github.com/llvm/llvm-project/pull/197673
>From 379da754c677787b29a58e287f922ea74db5140d Mon Sep 17 00:00:00 2001 From: Garvit Gupta <[email protected]> Date: Thu, 14 May 2026 02:39:07 -0700 Subject: [PATCH] [RISCV] Add assembler and disassembler support for Xqccmt extension Xqccmt is Qualcomm's vendor extension providing compressed (16-bit) jump table instructions, equivalent to (and mutually exclusive with) the standard Zcmt extension. Two instructions are added: - qc.cm.jt (index 0-31): jump via table, no link register written - qc.cm.jalt (index 32-255): jump via table with link; bit 0 of the jump table entry selects the link register at runtime: 0 = ra (x1), 1 = t0 (x5) The encoding is identical to cm.jt/cm.jalt from Zcmt. Xqccmt and Zcmt are mutually exclusive and cannot be combined. Xqccmt is also incompatible with Zcd (overlapping encoding space). Spec: https://github.com/riscv/riscv-unified-db/pull/1788 --- .../Driver/print-supported-extensions-riscv.c | 1 + .../test/Preprocessor/riscv-target-features.c | 14 +++++ llvm/docs/RISCVUsage.rst | 3 ++ llvm/docs/ReleaseNotes.md | 1 + .../RISCV/Disassembler/RISCVDisassembler.cpp | 3 ++ llvm/lib/Target/RISCV/RISCVFeatures.td | 8 +++ llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 + llvm/lib/Target/RISCV/RISCVInstrInfoXqccmt.td | 51 +++++++++++++++++++ llvm/lib/TargetParser/RISCVISAInfo.cpp | 7 ++- llvm/test/CodeGen/RISCV/attributes.ll | 4 ++ llvm/test/CodeGen/RISCV/features-info.ll | 1 + llvm/test/MC/RISCV/attribute-arch.s | 3 ++ llvm/test/MC/RISCV/xqccmt-invalid.s | 13 +++++ llvm/test/MC/RISCV/xqccmt-user-csr-name.s | 29 +++++++++++ llvm/test/MC/RISCV/xqccmt-valid.s | 45 ++++++++++++++++ .../TargetParser/RISCVISAInfoTest.cpp | 6 +++ 16 files changed, 189 insertions(+), 1 deletion(-) create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoXqccmt.td create mode 100644 llvm/test/MC/RISCV/xqccmt-invalid.s create mode 100644 llvm/test/MC/RISCV/xqccmt-user-csr-name.s create mode 100644 llvm/test/MC/RISCV/xqccmt-valid.s diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 82ef3e54dab29..ebee9f3c11910 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -259,6 +259,7 @@ // CHECK-NEXT: zvzip 0.1 'Zvzip' (Vector Reordering Structured Data) // CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension) // CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) +// CHECK-NEXT: xqccmt 0.1 'Xqccmt' (Qualcomm 16-bit Table Jump) // CHECK-NEXT: xrivosvizip 0.1 'XRivosVizip' (Rivos Vector Register Zips) // CHECK-NEXT: xsfmclic 0.1 'XSfmclic' (SiFive CLIC Machine-mode CSRs) // CHECK-NEXT: xsfsclic 0.1 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 6682948869f94..4880e02dc2e74 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -101,6 +101,7 @@ // CHECK-NOT: __riscv_zcmop {{.*$}} // CHECK-NOT: __riscv_zcmp {{.*$}} // CHECK-NOT: __riscv_zcmt {{.*$}} +// CHECK-NOT: __riscv_xqccmt {{.*$}} // CHECK-NOT: __riscv_zdinx {{.*$}} // CHECK-NOT: __riscv_zfa {{.*$}} // CHECK-NOT: __riscv_zfbfmin {{.*$}} @@ -792,6 +793,19 @@ // CHECK-ZCMT-EXT: __riscv_zca 1000000{{$}} // CHECK-ZCMT-EXT: __riscv_zcmt 1000000{{$}} +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -menable-experimental-extensions \ +// RUN: -march=rv32i_xqccmt0p1 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-XQCCMT-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -menable-experimental-extensions \ +// RUN: -march=rv64i_xqccmt0p1 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-XQCCMT-EXT %s +// CHECK-XQCCMT-EXT: __riscv_c 2000000{{$}} +// CHECK-XQCCMT-EXT: __riscv_xqccmt 1000{{$}} +// CHECK-XQCCMT-EXT: __riscv_zca 1000000{{$}} +// CHECK-XQCCMT-EXT: __riscv_zicsr 2000000{{$}} + // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32izdinx1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZDINX-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 71d91f73383b5..245e80cbdf11c 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -478,6 +478,9 @@ The current vendor extensions supported are: ``Xqccmp`` LLVM implements `version 0.3 of the 16-bit Push/Pop instructions and double-moves extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.3.0>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. +``experimental-Xqccmt`` + LLVM implements `version 0.1 of the Qualcomm 16-bit Table Jump extension specification <https://github.com/riscv/riscv-unified-db/pull/1788>`__ by Qualcomm. It provides ``qc.cm.jt`` and ``qc.cm.jalt`` instructions, which are equivalent to (and mutually exclusive with) the standard ``Zcmt`` extension. ``qc.cm.jalt`` extends the standard behavior by using bit 0 of the jump table entry to select the link register at runtime: ``ra`` (x1) if bit 0 is 0, or ``t0`` (x5) if bit 0 is 1. All instructions are prefixed with ``qc.`` as described in the specification. + ``Xqci`` LLVM implements `version 0.13 of the Qualcomm uC extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32. diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 582793db6d4be..7b9ee32659b73 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -204,6 +204,7 @@ Makes programs 10x faster by doing Special New Thing. * Adds experimental assembler support for the 'Zvvmm` (RISC-V Integer Matrix Multiply-Accumulate) extension. * Adds experimental assembler support for the 'Zvvfmm` (RISC-V Floating-Point Matrix Multiply-Accumulate) extension. * Adds support for 'Ziccid' (Instruction/Data Coherence and Consistency) extension. +* Adds experimental assembler and disassembler support for the `Xqccmt` (Qualcomm 16-bit Table Jump) vendor extension. ### Changes to the WebAssembly Backend diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 30a5d65a901d3..c1ba344f6edaf 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -579,6 +579,9 @@ static constexpr DecoderListEntry DecoderList16[]{ {DecoderTableXqccmp16, {RISCV::FeatureVendorXqccmp}, "Xqccmp (Qualcomm 16-bit Push/Pop & Double Move Instructions)"}, + {DecoderTableXqccmt16, + {RISCV::FeatureVendorXqccmt}, + "Xqccmt (Qualcomm 16-bit Table Jump Instructions)"}, {DecoderTableXwchc16, {RISCV::FeatureVendorXwchc}, "WCH QingKe XW"}, // Standard Extensions // DecoderTableZicfiss16 must be checked before DecoderTable16. diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 199ac77bef72f..82d67c6e646a1 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1535,6 +1535,14 @@ def HasVendorXqccmp AssemblerPredicate<(all_of FeatureVendorXqccmp), "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)">; +def FeatureVendorXqccmt + : RISCVExperimentalExtension<0, 1, "Qualcomm 16-bit Table Jump", + [FeatureStdExtZca, FeatureStdExtZicsr]>; +def HasVendorXqccmt + : Predicate<"Subtarget->hasVendorXqccmt()">, + AssemblerPredicate<(all_of FeatureVendorXqccmt), + "'Xqccmt' (Qualcomm 16-bit Table Jump)">; + def FeatureVendorXqcia : RISCVExtension<0, 7, "Qualcomm uC Arithmetic Extension">; def HasVendorXqcia diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 541bf302bf8e5..a535c02e86114 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -2385,6 +2385,7 @@ include "RISCVInstrInfoXCV.td" include "RISCVInstrInfoXwch.td" include "RISCVInstrInfoXqci.td" include "RISCVInstrInfoXqccmp.td" +include "RISCVInstrInfoXqccmt.td" include "RISCVInstrInfoXMips.td" include "RISCVInstrInfoXRivos.td" include "RISCVInstrInfoXAndes.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqccmt.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqccmt.td new file mode 100644 index 0000000000000..1ff23e2dddd13 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqccmt.td @@ -0,0 +1,51 @@ +//===-- RISCVInstrInfoXqccmt.td ----------------------------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes Qualcomm's Xqccmt extension. +// +// Xqccmt is broadly equivalent to (and incompatible with) Zcmt except the +// following change: +// +// - qc.cm.jalt uses bit 0 of the jump table entry as metadata to select the +// link register: bit 0 = 0 saves the return address in ra (x1), bit 0 = 1 +// saves it in t0 (x5), the alternate link register. The jump target always +// has bit 0 cleared. +// +// The instruction encoding is identical to cm.jt / cm.jalt from Zcmt. +// Xqccmt and Zcmt are mutually exclusive and cannot both be enabled. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +let DecoderNamespace = "Xqccmt", Predicates = [HasVendorXqccmt], + hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { + +def QC_CM_JT : RVInst16CJ<0b101, OPC_C2, (outs), (ins uimm5:$index), + "qc.cm.jt", "$index"> { + bits<5> index; + + let Inst{12-7} = 0b000000; + let Inst{6-2} = index; +} + +// qc.cm.jalt may write to either ra (x1) or t0 (x5) at runtime, depending +// on bit 0 of the jump table entry. Both registers are listed as Defs for +// conservative correctness. +let Defs = [X1, X5] in +def QC_CM_JALT : RVInst16CJ<0b101, OPC_C2, (outs), (ins uimm8ge32:$index), + "qc.cm.jalt", "$index"> { + bits<8> index; + + let Inst{12-10} = 0b000; + let Inst{9-2} = index; +} + +} // DecoderNamespace = "Xqccmt", Predicates = [HasVendorXqccmt] diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp index 973f81d25b321..7b04b42f8d000 100644 --- a/llvm/lib/TargetParser/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -745,9 +745,11 @@ Error RISCVISAInfo::checkDependency() { bool HasZvl = MinVLen != 0; bool HasZcmp = Exts.count("zcmp") != 0; bool HasXqccmp = Exts.count("xqccmp") != 0; + bool HasZcmt = Exts.count("zcmt") != 0; + bool HasXqccmt = Exts.count("xqccmt") != 0; static constexpr StringLiteral ZcdOverlaps[] = { - {"zcmt"}, {"zcmp"}, {"xqccmp"}, {"xqciac"}, {"xqcicm"}, + {"zcmt"}, {"zcmp"}, {"xqccmp"}, {"xqccmt"}, {"xqciac"}, {"xqcicm"}, }; static constexpr StringLiteral RV32Only[] = { {"zcf"}, {"zclsd"}, {"zilsd"}, {"xwchc"}, {"xqci"}, @@ -796,6 +798,9 @@ Error RISCVISAInfo::checkDependency() { if (HasZcmp && HasXqccmp) return getIncompatibleError("zcmp", "xqccmp"); + if (HasZcmt && HasXqccmt) + return getIncompatibleError("zcmt", "xqccmt"); + return Error::success(); } diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 2c1ae20ee44c1..71dff844a6fb9 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -88,6 +88,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zcf %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCF %s ; RUN: llc -mtriple=riscv32 -mattr=+zcmp %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCMP %s ; RUN: llc -mtriple=riscv32 -mattr=+zcmt %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCMT %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqccmt %s -o - | FileCheck --check-prefixes=CHECK,RV32XQCCMT %s ; RUN: llc -mtriple=riscv32 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICSR %s ; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIFENCEI %s ; RUN: llc -mtriple=riscv32 -mattr=+zicntr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICNTR %s @@ -240,6 +241,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zcd %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCD %s ; RUN: llc -mtriple=riscv64 -mattr=+zcmp %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCMP %s ; RUN: llc -mtriple=riscv64 -mattr=+zcmt %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCMT %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-xqccmt %s -o - | FileCheck --check-prefixes=CHECK,RV64XQCCMT %s ; RUN: llc -mtriple=riscv64 -mattr=+ziccamoa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCAMOA %s ; RUN: llc -mtriple=riscv64 -mattr=+ziccamoc %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCAMOC %s ; RUN: llc -mtriple=riscv64 -mattr=+ziccid %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCID %s @@ -413,6 +415,7 @@ ; RV32ZCF: .attribute 5, "rv32i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcf1p0" ; RV32ZCMP: .attribute 5, "rv32i2p1_c2p0_zca1p0_zcmp1p0" ; RV32ZCMT: .attribute 5, "rv32i2p1_c2p0_zicsr2p0_zca1p0_zcmt1p0" +; RV32XQCCMT: .attribute 5, "rv32i2p1_c2p0_zicsr2p0_zca1p0_xqccmt0p1" ; RV32ZICSR: .attribute 5, "rv32i2p1_zicsr2p0" ; RV32ZIFENCEI: .attribute 5, "rv32i2p1_zifencei2p0" ; RV32ZICNTR: .attribute 5, "rv32i2p1_zicntr2p0_zicsr2p0" @@ -562,6 +565,7 @@ ; RV64ZCD: .attribute 5, "rv64i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0" ; RV64ZCMP: .attribute 5, "rv64i2p1_c2p0_zca1p0_zcmp1p0" ; RV64ZCMT: .attribute 5, "rv64i2p1_c2p0_zicsr2p0_zca1p0_zcmt1p0" +; RV64XQCCMT: .attribute 5, "rv64i2p1_c2p0_zicsr2p0_zca1p0_xqccmt0p1" ; RV64ZICCAMOA: .attribute 5, "rv64i2p1_ziccamoa1p0" ; RV64ZICCAMOC: .attribute 5, "rv64i2p1_ziccamoc1p0" ; RV64ZICCID: .attribute 5, "rv64i2p1_ziccid1p0_ziccif1p0" diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 96f193a2633f5..aadbabbbb92db 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -26,6 +26,7 @@ ; CHECK-NEXT: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile. ; CHECK-NEXT: experimental-smpmpmt - 'Smpmpmt' (PMP-based Memory Types Extension). ; CHECK-NEXT: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses). +; CHECK-NEXT: experimental-xqccmt - 'Xqccmt' (Qualcomm 16-bit Table Jump). ; CHECK-NEXT: experimental-xrivosvizip - 'XRivosVizip' (Rivos Vector Register Zips). ; CHECK-NEXT: experimental-xsfmclic - 'XSfmclic' (SiFive CLIC Machine-mode CSRs). ; CHECK-NEXT: experimental-xsfsclic - 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs). diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index ef5e091e7e41e..5bd0546016e3d 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -276,6 +276,9 @@ .attribute arch, "rv32izcmt1p0" # CHECK: attribute 5, "rv32i2p1_c2p0_zicsr2p0_zca1p0_zcmt1p0" +.attribute arch, "rv32i_xqccmt0p1" +# CHECK: attribute 5, "rv32i2p1_c2p0_zicsr2p0_zca1p0_xqccmt0p1" + .attribute arch, "rv64i_xsfvcp" # CHECK: attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfvcp1p0" diff --git a/llvm/test/MC/RISCV/xqccmt-invalid.s b/llvm/test/MC/RISCV/xqccmt-invalid.s new file mode 100644 index 0000000000000..75067b1f26b4f --- /dev/null +++ b/llvm/test/MC/RISCV/xqccmt-invalid.s @@ -0,0 +1,13 @@ +# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-xqccmt -M no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-ERROR %s +# RUN: not llvm-mc -triple=riscv64 -mattr=+experimental-xqccmt -M no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-ERROR %s + +# CHECK-ERROR: error: immediate must be an integer in the range [0, 31] +qc.cm.jt 32 + +# CHECK-ERROR: error: immediate must be an integer in the range [32, 255] +qc.cm.jalt 256 + +# CHECK-ERROR: error: immediate must be an integer in the range [32, 255] +qc.cm.jalt 31 diff --git a/llvm/test/MC/RISCV/xqccmt-user-csr-name.s b/llvm/test/MC/RISCV/xqccmt-user-csr-name.s new file mode 100644 index 0000000000000..d52e226a794c3 --- /dev/null +++ b/llvm/test/MC/RISCV/xqccmt-user-csr-name.s @@ -0,0 +1,29 @@ +# RUN: llvm-mc %s -triple=riscv32 -M no-aliases -mattr=+experimental-xqccmt -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqccmt < %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-xqccmt - \ +# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s +# +# RUN: llvm-mc %s -triple=riscv64 -M no-aliases -mattr=+experimental-xqccmt -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-xqccmt < %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-xqccmt - \ +# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s + +################################## +# Jump Vector Table CSR +################################## + +# jvt +# name +# CHECK-INST: csrrs t1, jvt, zero +# CHECK-ENC: encoding: [0x73,0x23,0x70,0x01] +# CHECK-INST-ALIAS: csrr t1, jvt +# uimm12 +# CHECK-INST: csrrs t2, jvt, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x01] +# CHECK-INST-ALIAS: csrr t2, jvt +# name +csrrs t1, jvt, zero +# uimm12 +csrrs t2, 0x017, zero diff --git a/llvm/test/MC/RISCV/xqccmt-valid.s b/llvm/test/MC/RISCV/xqccmt-valid.s new file mode 100644 index 0000000000000..4d00ea78bae9c --- /dev/null +++ b/llvm/test/MC/RISCV/xqccmt-valid.s @@ -0,0 +1,45 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqccmt \ +# RUN: -M no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-xqccmt < %s \ +# RUN: | llvm-objdump --mattr=-c,+experimental-xqccmt --no-print-imm-hex \ +# RUN: -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-xqccmt \ +# RUN: -M no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-xqccmt < %s \ +# RUN: | llvm-objdump --mattr=-c,+experimental-xqccmt --no-print-imm-hex \ +# RUN: -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s +# +# RUN: not llvm-mc -triple riscv32 \ +# RUN: -M no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s +# RUN: not llvm-mc -triple riscv64 \ +# RUN: -M no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s + +# qc.cm.jt +# CHECK-ASM-AND-OBJ: qc.cm.jt 1 +# CHECK-ASM: encoding: [0x06,0xa0] +# CHECK-NO-EXT: error: instruction requires the following: 'Xqccmt' (Qualcomm 16-bit Table Jump){{$}} +qc.cm.jt 1 + +# CHECK-ASM-AND-OBJ: qc.cm.jt 0 +# CHECK-ASM: encoding: [0x02,0xa0] +qc.cm.jt 0 + +# CHECK-ASM-AND-OBJ: qc.cm.jt 31 +# CHECK-ASM: encoding: [0x7e,0xa0] +qc.cm.jt 31 + +# qc.cm.jalt +# CHECK-ASM-AND-OBJ: qc.cm.jalt 32 +# CHECK-ASM: encoding: [0x82,0xa0] +# CHECK-NO-EXT: error: instruction requires the following: 'Xqccmt' (Qualcomm 16-bit Table Jump){{$}} +qc.cm.jalt 32 + +# CHECK-ASM-AND-OBJ: qc.cm.jalt 255 +# CHECK-ASM: encoding: [0xfe,0xa3] +qc.cm.jalt 255 diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index cd0dcf98f50de..2e37a3d70c9da 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -701,6 +701,11 @@ TEST(ParseArchString, RejectsConflictingExtensions) { EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), "'zcmp' and 'xqccmp' extensions are incompatible"); } + + for (StringRef Input : {"rv32i_zcmt_xqccmt0p1", "rv64i_zcmt_xqccmt0p1"}) { + EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), + "'zcmt' and 'xqccmt' extensions are incompatible"); + } } TEST(ParseArchString, MissingDepency) { @@ -1390,6 +1395,7 @@ Experimental extensions zvzip 0.1 smpmpmt 0.6 svukte 0.3 + xqccmt 0.1 xrivosvizip 0.1 xsfmclic 0.1 xsfsclic 0.1 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
