================
@@ -2314,6 +2317,33 @@ bool SPIRVInstructionSelector::selectAtomicRMW(Register
ResVReg,
return true;
}
+bool SPIRVInstructionSelector::selectInterlockedAdd(Register ResVReg,
+ SPIRVTypeInst ResType,
+ MachineInstr &I) const {
+ Register Ptr = I.getOperand(2).getReg();
+ Register Value = I.getOperand(3).getReg();
+
+ SPIRV::StorageClass::StorageClass SC = GR.getPointerStorageClass(Ptr);
+ uint32_t Scope = static_cast<uint32_t>(SC == SPIRV::StorageClass::Workgroup
+ ? SPIRV::Scope::Workgroup
+ : SPIRV::Scope::Device);
+ Register ScopeReg = buildI32Constant(Scope, I);
+
+ uint32_t MemSem = static_cast<uint32_t>(getMemSemanticsForStorageClass(SC)) |
+ static_cast<uint32_t>(SPIRV::MemorySemantics::None);
----------------
Icohedron wrote:
nit: `SPIRV::MemorySemantics::None` is 0 so computing a bitwise OR with it is a
no-op.
```suggestion
uint32_t MemSem = static_cast<uint32_t>(getMemSemanticsForStorageClass(SC));
```
https://github.com/llvm/llvm-project/pull/195742
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