================
@@ -2541,6 +2542,66 @@ bool
AArch64InstructionSelector::earlySelect(MachineInstr &I) {
I.eraseFromParent();
return true;
}
+ case TargetOpcode::G_STORE: {
+ GStore &St = cast<GStore>(I);
+ auto MMO = St.getMMO();
+ LLT PtrTy = MRI.getType(St.getPointerReg());
+
+ // Only for handling atomic store with hint.
+ // Can only handle AddressSpace 0, 64-bit pointers.
+ if (!St.isAtomic() || PtrTy != LLT::pointer(0, 64)) {
+ return false;
+ }
+
+ AArch64AtomicStoreHint Hint = TII.decodeAtomicHintFlags(MMO.getFlags());
+ if (Hint == AArch64AtomicStoreHint::HINT_NONE)
+ return false;
+
+ unsigned HintOpc;
+ unsigned StoreSize = St.getMemSizeInBits().getValue();
+ Register ValueReg = St.getValueReg();
+ switch (StoreSize) {
+ case 8:
+ HintOpc = AArch64::ATOMIC_STORE_HINT_B;
+ break;
+ case 16: {
+ Register CastReg;
+ if (mi_match(ValueReg, MRI, m_GBitcast(m_Reg(CastReg)))) {
+ auto Undef = MIB.buildInstr(TargetOpcode::IMPLICIT_DEF,
+ {&AArch64::FPR32RegClass}, {});
+ auto Ins = MIB.buildInstr(TargetOpcode::INSERT_SUBREG,
+ {&AArch64::FPR32RegClass}, {Undef, ValueReg})
+ .addImm(AArch64::hsub);
+ constrainSelectedInstRegOperands(*Undef, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*Ins, TII, TRI, RBI);
+ ValueReg = Ins.getReg(0);
+ }
+ HintOpc = AArch64::ATOMIC_STORE_HINT_H;
+ break;
+ }
+ case 32:
+ HintOpc = AArch64::ATOMIC_STORE_HINT_S;
+ break;
+ case 64:
+ HintOpc = AArch64::ATOMIC_STORE_HINT_D;
+ break;
+ default:
+ llvm_unreachable("Unexpected getMemSizeInBits() value for atomic hint.");
+ }
+
+ unsigned HintImm = Hint == AArch64AtomicStoreHint::HINT_STSHH_KEEP ? 0 : 1;
+
+ auto StrPseudo = BuildMI(MBB, I, MIMetadata(I), TII.get(HintOpc))
+ .addReg(St.getPointerReg())
+ .addReg(ValueReg)
+ .addImm((int)toCABI(St.getMMO().getSuccessOrdering()))
----------------
Lukacma wrote:
I think we shouldn't go back to using C++ ordering at this level. We should
stick with the LLVM one
```suggestion
.addImm((int)MMO.getSuccessOrdering()))
```
https://github.com/llvm/llvm-project/pull/198316
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