================
@@ -0,0 +1,154 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck
-check-prefix=GFX1250 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck
-check-prefix=GFX1250 %s
+
+declare void @llvm.amdgcn.tensor.load.async.to.lds(<4 x i32> %D0, <8 x i32>
%D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> %D4, i32 %cpol)
+declare void @llvm.amdgcn.tensor.store.async.from.lds(<4 x i32> %D0, <8 x i32>
%D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> %D4, i32 %cpol)
+
+define amdgpu_ps void @tensor_load_async_to_lds_d4(<4 x i32> inreg %D0, <8 x
i32> inreg %D1, <4 x i32> inreg %D2, <4 x i32> inreg %D3) {
+; GFX1250-LABEL: tensor_load_async_to_lds_d4:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ;
msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: tensor_load_to_lds s[0:3], s[4:11], s[12:15], s[16:19]
+; GFX1250-NEXT: s_endpgm
+ call void @llvm.amdgcn.tensor.load.async.to.lds(<4 x i32> %D0, <8 x i32>
%D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> zeroinitializer, i32 0)
+ ret void
+}
+
+define amdgpu_ps void @tensor_load_async_to_lds_d2(<4 x i32> inreg %D0, <8 x
i32> inreg %D1) {
+; GFX1250-LABEL: tensor_load_async_to_lds_d2:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ;
msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: tensor_load_to_lds s[0:3], s[4:11] th:TH_LOAD_BYPASS
scope:SCOPE_SYS
+; GFX1250-NEXT: s_endpgm
+ call void @llvm.amdgcn.tensor.load.async.to.lds(<4 x i32> %D0, <8 x i32>
%D1, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32>
zeroinitializer, i32 27)
+ ret void
+}
+
+define amdgpu_ps void @tensor_store_async_from_lds_d4(<4 x i32> inreg %D0, <8
x i32> inreg %D1, <4 x i32> inreg %D2, <4 x i32> inreg %D3) {
+; GFX1250-LABEL: tensor_store_async_from_lds_d4:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ;
msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: tensor_store_from_lds s[0:3], s[4:11], s[12:15], s[16:19]
th:TH_STORE_NT_HT scope:SCOPE_DEV
+; GFX1250-NEXT: s_endpgm
+ call void @llvm.amdgcn.tensor.store.async.from.lds(<4 x i32> %D0, <8 x i32>
%D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> zeroinitializer, i32 22)
+ ret void
+}
+
+define amdgpu_ps void @tensor_store_async_from_lds_d2(<4 x i32> inreg %D0, <8
x i32> inreg %D1) {
+; GFX1250-LABEL: tensor_store_async_from_lds_d2:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ;
msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: tensor_store_from_lds s[0:3], s[4:11]
+; GFX1250-NEXT: s_endpgm
+ call void @llvm.amdgcn.tensor.store.async.from.lds(<4 x i32> %D0, <8 x i32>
%D1, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32>
zeroinitializer, i32 0)
+ ret void
+}
+
+;=======================================================================
+; It is fine to pass 5 arguments as tensor descriptor, but the fifth one
+; will be ignored silently by the CodeGen for gfx1250, which only
+; supports D# up to 4 groups.
+;========================================================================
+
+define amdgpu_ps void @tensor_load_async_to_lds_d5(<4 x i32> inreg %D0, <8 x
i32> inreg %D1, <4 x i32> inreg %D2, <4 x i32> inreg %D3, <8 x i32> inreg %D4) {
+; GFX1250-LABEL: tensor_load_async_to_lds_d5:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ;
msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: tensor_load_to_lds s[0:3], s[4:11], s[12:15], s[16:19]
+; GFX1250-NEXT: s_endpgm
+ call void @llvm.amdgcn.tensor.load.async.to.lds(<4 x i32> %D0, <8 x i32>
%D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> %D4, i32 0)
+ ret void
+}
+
+define amdgpu_ps void @tensor_store_async_from_lds_d5(<4 x i32> inreg %D0, <8
x i32> inreg %D1, <4 x i32> inreg %D2, <4 x i32> inreg %D3, <8 x i32> inreg
%D4) {
+; GFX1250-LABEL: tensor_store_async_from_lds_d5:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ;
msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: tensor_store_from_lds s[0:3], s[4:11], s[12:15], s[16:19]
th:TH_STORE_NT_HT scope:SCOPE_DEV
+; GFX1250-NEXT: s_endpgm
+ call void @llvm.amdgcn.tensor.store.async.from.lds(<4 x i32> %D0, <8 x i32>
%D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> %D4, i32 22)
+ ret void
+}
+
+;=======================================================================
+; Async tensor load/store interleaved with asyncmark and wait_asyncmark.
+;========================================================================
+
+define amdgpu_ps void @tensor_load_async_to_lds_with_asyncmark(<4 x i32> inreg
%D0, <8 x i32> inreg %D1) {
+; GFX1250-LABEL: tensor_load_async_to_lds_with_asyncmark:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ;
msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: tensor_load_to_lds s[0:3], s[4:11]
+; GFX1250-NEXT: ; asyncmark
+; GFX1250-NEXT: ; wait_asyncmark(0)
+; GFX1250-NEXT: s_wait_tensorcnt 0x0
+; GFX1250-NEXT: s_endpgm
+ call void @llvm.amdgcn.tensor.load.async.to.lds(<4 x i32> %D0, <8 x i32>
%D1, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32>
zeroinitializer, i32 0)
+ call void @llvm.amdgcn.asyncmark()
+ call void @llvm.amdgcn.wait.asyncmark(i16 0)
+ ret void
+}
+
+define amdgpu_ps void @tensor_store_async_from_lds_with_asyncmark(<4 x i32>
inreg %D0, <8 x i32> inreg %D1) {
+; GFX1250-LABEL: tensor_store_async_from_lds_with_asyncmark:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ;
msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: tensor_store_from_lds s[0:3], s[4:11]
+; GFX1250-NEXT: ; asyncmark
+; GFX1250-NEXT: ; wait_asyncmark(0)
+; GFX1250-NEXT: s_wait_tensorcnt 0x0
+; GFX1250-NEXT: s_endpgm
+ call void @llvm.amdgcn.tensor.store.async.from.lds(<4 x i32> %D0, <8 x i32>
%D1, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32>
zeroinitializer, i32 0)
+ call void @llvm.amdgcn.asyncmark()
+ call void @llvm.amdgcn.wait.asyncmark(i16 0)
+ ret void
+}
+
+
+
+define amdgpu_ps void @tensor_load_async_to_lds_two_asyncmarks(<4 x i32> inreg
%D0a, <8 x i32> inreg %D1a,
+; GFX1250-LABEL: tensor_load_async_to_lds_two_asyncmarks:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ;
msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: tensor_load_to_lds s[0:3], s[4:11]
+; GFX1250-NEXT: ; asyncmark
+; GFX1250-NEXT: tensor_load_to_lds s[12:15], s[16:23]
+; GFX1250-NEXT: ; asyncmark
+; GFX1250-NEXT: ; wait_asyncmark(1)
+; GFX1250-NEXT: s_wait_tensorcnt 0x1
+; GFX1250-NEXT: ds_load_b32 v1, v0
+; GFX1250-NEXT: ; wait_asyncmark(0)
+; GFX1250-NEXT: s_wait_tensorcnt 0x0
+; GFX1250-NEXT: ds_load_b32 v2, v0 offset:4
+; GFX1250-NEXT: s_wait_dscnt 0x0
+; GFX1250-NEXT: v_add_nc_u32_e32 v1, v1, v2
+; GFX1250-NEXT: ds_store_b32 v0, v1
+; GFX1250-NEXT: s_endpgm
+ <4 x i32> inreg %D0b,
<8 x i32> inreg %D1b,
----------------
shiltian wrote:
there is no point of formatting IR test files, aka. wrap those arguments. this
looks really weird.
https://github.com/llvm/llvm-project/pull/200775
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