https://github.com/E00N777 updated https://github.com/llvm/llvm-project/pull/199415
>From c04a0e8310e565b1311e2b908535fabb28bf0cfc Mon Sep 17 00:00:00 2001 From: E0N777 <[email protected]> Date: Sun, 24 May 2026 20:37:10 +0800 Subject: [PATCH] [CIR][AArch64] Lower NEON vslid intrinsics --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 2 ++ clang/test/CodeGen/AArch64/neon-intrinsics.c | 26 ---------------- clang/test/CodeGen/AArch64/neon/intrinsics.c | 31 +++++++++++++++++++ 3 files changed, 33 insertions(+), 26 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index a06b76d453d48..f0384ade6cf04 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -436,6 +436,8 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr( case NEON::BI__builtin_neon_vqrshrnd_n_u64: case NEON::BI__builtin_neon_vsrid_n_s64: case NEON::BI__builtin_neon_vsrid_n_u64: + case NEON::BI__builtin_neon_vslid_n_s64: + case NEON::BI__builtin_neon_vslid_n_u64: break; } diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index c4eac89e78bc1..06fe4a7489c1d 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -14527,32 +14527,6 @@ uint64x1_t test_vqshlu_n_s64(int64x1_t a) { return vqshlu_n_s64(a, 1); } -// CHECK-LABEL: define dso_local i64 @test_vslid_n_s64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSLID_N_S64:%.*]] = bitcast i64 [[A]] to <1 x i64> -// CHECK-NEXT: [[VSLID_N_S641:%.*]] = bitcast i64 [[B]] to <1 x i64> -// CHECK-NEXT: [[VSLID_N_S642:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64> [[VSLID_N_S64]], <1 x i64> [[VSLID_N_S641]], i32 63) -// CHECK-NEXT: [[VSLID_N_S643:%.*]] = bitcast <1 x i64> [[VSLID_N_S642]] to i64 -// CHECK-NEXT: ret i64 [[VSLID_N_S643]] -// -int64_t test_vslid_n_s64(int64_t a, int64_t b) { - return (int64_t)vslid_n_s64(a, b, 63); -} - -// CHECK-LABEL: define dso_local i64 @test_vslid_n_u64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSLID_N_U64:%.*]] = bitcast i64 [[A]] to <1 x i64> -// CHECK-NEXT: [[VSLID_N_U641:%.*]] = bitcast i64 [[B]] to <1 x i64> -// CHECK-NEXT: [[VSLID_N_U642:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64> [[VSLID_N_U64]], <1 x i64> [[VSLID_N_U641]], i32 63) -// CHECK-NEXT: [[VSLID_N_U643:%.*]] = bitcast <1 x i64> [[VSLID_N_U642]] to i64 -// CHECK-NEXT: ret i64 [[VSLID_N_U643]] -// -uint64_t test_vslid_n_u64(uint64_t a, uint64_t b) { - return (uint64_t)vslid_n_u64(a, b, 63); -} - // CHECK-LABEL: define dso_local i8 @test_vqshrnh_n_s16( // CHECK-SAME: i16 noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index efa2691ef611e..716366ee6b79c 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -6437,3 +6437,34 @@ poly64x2_t test_vsriq_n_p64(poly64x2_t a, poly64x2_t b) { // LLVM: ret <2 x i64> [[VSRI_N2]] return vsriq_n_p64(a, b, 64); } + +//===------------------------------------------------------===// +// 2.1.3.1.6. Vector shift left and insert (scalar) +// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-left-and-insert +//===------------------------------------------------------===// + +// ALL-LABEL: @test_vslid_n_s64( +int64_t test_vslid_n_s64(int64_t a, int64_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsli" %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !s32i) -> !cir.vector<1 x !s64i> + +// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast i64 [[A]] to <1 x i64> +// LLVM: [[TMP1:%.*]] = bitcast i64 [[B]] to <1 x i64> +// LLVM: [[VSLID:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64> [[TMP0]], <1 x i64> [[TMP1]], i32 63) +// LLVM: [[RET:%.*]] = bitcast <1 x i64> [[VSLID]] to i64 +// LLVM: ret i64 [[RET]] + return (int64_t)vslid_n_s64(a, b, 63); +} + +// ALL-LABEL: @test_vslid_n_u64( +uint64_t test_vslid_n_u64(uint64_t a, uint64_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsli" %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !s32i) -> !cir.vector<1 x !u64i> + +// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast i64 [[A]] to <1 x i64> +// LLVM: [[TMP1:%.*]] = bitcast i64 [[B]] to <1 x i64> +// LLVM: [[VSLID:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64> [[TMP0]], <1 x i64> [[TMP1]], i32 63) +// LLVM: [[RET:%.*]] = bitcast <1 x i64> [[VSLID]] to i64 +// LLVM: ret i64 [[RET]] + return (uint64_t)vslid_n_u64(a, b, 63); +} _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
