================
@@ -349,3 +350,169 @@ define amdgpu_ps void
@tensor_load_to_lds_two_asyncmarks(<4 x i32> inreg %D0a, <
ret void
}
+
+;=======================================================================
+; Mix ASYNC_CNT and TENSOR_CNT tracked operations under a single
+; asyncmark, and verify that a wait.asyncmark drains both counters.
+;========================================================================
+
+define amdgpu_ps void @tensor_and_async_lds_with_asyncmark(<4 x i32> inreg
%D0, <8 x i32> inreg %D1, ptr addrspace(1) %src, ptr addrspace(3) %dst) {
+; GFX1250-LABEL: tensor_and_async_lds_with_asyncmark:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ;
msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: global_load_async_to_lds_b32 v2, v[0:1], off
+; GFX1250-NEXT: tensor_load_to_lds s[0:3], s[4:11]
+; GFX1250-NEXT: ; asyncmark
+; GFX1250-NEXT: ; wait_asyncmark(0)
+; GFX1250-NEXT: s_wait_asynccnt 0x0
+; GFX1250-NEXT: s_wait_tensorcnt 0x0
+; GFX1250-NEXT: s_endpgm
+ call void @llvm.amdgcn.global.load.async.to.lds.b32(ptr addrspace(1) %src,
ptr addrspace(3) %dst, i32 0, i32 0)
+ call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x
i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32
0)
+ call void @llvm.amdgcn.asyncmark()
+ call void @llvm.amdgcn.wait.asyncmark(i16 0)
+ ret void
+}
+
+;=======================================================================
+; Two diamond if/else regions, each picking either a tensor DMA or an
+; async-LDS DMA, each followed by its own asyncmark.
+;========================================================================
+
+define amdgpu_ps void @tensor_or_async_lds_diamonds(i32 inreg %cond1, i32
inreg %cond2, <4 x i32> inreg %D0, <8 x i32> inreg %D1, ptr addrspace(1) %src,
ptr addrspace(3) %dst) {
----------------
adeshcom14 wrote:
fixed
https://github.com/llvm/llvm-project/pull/200775
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