https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/196653
>From dbed69322444c8358c233a75e7168f82cbd32a44 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu <[email protected]> Date: Fri, 8 May 2026 14:42:47 -0700 Subject: [PATCH 1/3] [Driver][RISCV] Support the new `-mtune` syntax with tune feature string --- .../clang/Basic/DiagnosticDriverKinds.td | 2 + clang/include/clang/Options/Options.td | 4 ++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 43 +++++++++++++++++++ clang/lib/Driver/ToolChains/Arch/RISCV.h | 7 +++ clang/lib/Driver/ToolChains/Clang.cpp | 11 +++-- clang/test/Driver/riscv-mtune-tune-features.c | 39 +++++++++++++++++ 6 files changed, 103 insertions(+), 3 deletions(-) create mode 100644 clang/test/Driver/riscv-mtune-tune-features.c diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td b/clang/include/clang/Basic/DiagnosticDriverKinds.td index 114ee475c371f..8ffaa48d87023 100644 --- a/clang/include/clang/Basic/DiagnosticDriverKinds.td +++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td @@ -33,6 +33,8 @@ def err_drv_invalid_riscv_arch_name : Error< "invalid arch name '%0', %1">; def err_drv_invalid_riscv_cpu_name_for_target : Error< "cpu '%0' does not support rv%select{32|64}1">; +def err_drv_invalid_riscv_mtune_string : Error< + "invalid %select{-mtune|tune feature}0 string '%1': %2">; def warn_drv_invalid_arch_name_with_suggestion : Warning< "ignoring invalid /arch: argument '%0'; for %select{64|32}1-bit expected one of %2">, InGroup<UnusedCommandLineArgument>; diff --git a/clang/include/clang/Options/Options.td b/clang/include/clang/Options/Options.td index 5eeabf4c33b76..43591a98b85a0 100644 --- a/clang/include/clang/Options/Options.td +++ b/clang/include/clang/Options/Options.td @@ -5595,6 +5595,10 @@ def mrvv_vector_bits_EQ : Joined<["-"], "mrvv-vector-bits=">, Group<m_Group>, !eq(GlobalDocumentation.Program, "Flang") : "", true: " The value will be reflected in __riscv_v_fixed_vlen preprocessor define"), " (RISC-V only)")>; +def mexperimental_mtune_syntax : Flag<["-"], "mexperimental-mtune-syntax">, Group<m_Group>, + HelpText<"Enable experimental syntax for the '-mtune' flag (RISC-V only)">; +def mno_experimental_mtune_syntax : Flag<["-"], "mno-experimental-mtune-syntax">, Group<m_Group>, + HelpText<"Disable experimental syntax for the '-mtune' flag (RISC-V only)">; def munaligned_access : Flag<["-"], "munaligned-access">, Group<m_Group>, HelpText<"Allow memory accesses to be unaligned (AArch32/MIPSr6 only)">; diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp index 7fda8ea50223d..14eb441d19735 100644 --- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp +++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp @@ -169,6 +169,12 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple, Features.push_back("+unaligned-vector-mem"); } + SmallVector<std::string, 4> TuneFeatures; + if (!riscv::getRISCVTuneCPU(D, Args, &TuneFeatures)) + return; + for (const std::string &TF : TuneFeatures) + Features.push_back(Args.MakeArgString(TF)); + // Now add any that the user explicitly requested on the command line, // which may override the defaults. handleTargetFeaturesGroup(D, Triple, Args, Features, @@ -360,3 +366,40 @@ std::string riscv::getRISCVTargetCPU(const llvm::opt::ArgList &Args, return Triple.isRISCV64() ? "generic-rv64" : "generic-rv32"; } + +std::optional<StringRef> +riscv::getRISCVTuneCPU(const Driver &D, const llvm::opt::ArgList &Args, + SmallVectorImpl<std::string> *TuneFeatures) { + const Arg *MTuneArg = Args.getLastArg(options::OPT_mtune_EQ); + if (!MTuneArg) + return ""; + + StringRef MTune = MTuneArg->getValue(); + // Split the CPU name part from the tune features string. + auto [TuneCPU, TFString] = MTune.split(':'); + if (!Args.hasFlag(options::OPT_mexperimental_mtune_syntax, + options::OPT_mno_experimental_mtune_syntax, false)) { + if (!TFString.empty()) { + // Only print this diagnostics if it's used for retrieving tune features + // to avoid printing the same error message multiple times. + if (TuneFeatures) + D.Diag(diag::err_drv_invalid_riscv_mtune_string) + << 0 << MTune + << "require '-mexperimental-mtune-syntax' to use with tune feature " + "string"; + return std::nullopt; + } + return MTune; + } + + if (!TuneFeatures || TFString.empty()) + return TuneCPU; + if (auto E = llvm::RISCV::parseTuneFeatureString(TuneCPU, TFString, + *TuneFeatures)) { + D.Diag(diag::err_drv_invalid_riscv_mtune_string) + << 1 << TFString << llvm::toString(std::move(E)); + return std::nullopt; + } + + return TuneCPU; +} diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.h b/clang/lib/Driver/ToolChains/Arch/RISCV.h index 388786b9c4c1f..7cbd8b7c0a7ee 100644 --- a/clang/lib/Driver/ToolChains/Arch/RISCV.h +++ b/clang/lib/Driver/ToolChains/Arch/RISCV.h @@ -10,8 +10,10 @@ #define LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_ARCH_RISCV_H #include "clang/Driver/Driver.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" #include "llvm/Option/Option.h" +#include <optional> #include <string> #include <vector> @@ -28,6 +30,11 @@ std::string getRISCVArch(const llvm::opt::ArgList &Args, const llvm::Triple &Triple); std::string getRISCVTargetCPU(const llvm::opt::ArgList &Args, const llvm::Triple &Triple); +/// Return the tune CPU and optionally, the tune features. A std::nullopt +/// return value signals error state. +std::optional<StringRef> +getRISCVTuneCPU(const Driver &D, const llvm::opt::ArgList &Args, + SmallVectorImpl<std::string> *TuneFeatures = nullptr); } // end namespace riscv } // namespace tools } // end namespace driver diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 92b3045dceff2..730c87a9d7142 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -2040,12 +2040,17 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args, options::OPT_mno_implicit_float, true)) CmdArgs.push_back("-no-implicit-float"); - if (const Arg *A = Args.getLastArg(options::OPT_mtune_EQ)) { + auto TuneCPU = riscv::getRISCVTuneCPU(getToolChain().getDriver(), Args); + if (!TuneCPU) + return; + if (!TuneCPU->empty()) { CmdArgs.push_back("-tune-cpu"); - if (strcmp(A->getValue(), "native") == 0) + if (*TuneCPU == "native") CmdArgs.push_back(Args.MakeArgString(llvm::sys::getHostCPUName())); else - CmdArgs.push_back(A->getValue()); + // TuneCPU might or might not be the original -mtune string, so we + // have to create a new copy here. + CmdArgs.push_back(Args.MakeArgString(*TuneCPU)); } // Handle -mrvv-vector-bits=<bits> diff --git a/clang/test/Driver/riscv-mtune-tune-features.c b/clang/test/Driver/riscv-mtune-tune-features.c new file mode 100644 index 0000000000000..e31500cf9d20a --- /dev/null +++ b/clang/test/Driver/riscv-mtune-tune-features.c @@ -0,0 +1,39 @@ +// Check the advanced -mtune syntax with tune feature string + +// RUN: %clang -### --target=riscv64 -mexperimental-mtune-syntax \ +// RUN: -mtune=sifive-x390:full-vec-fp64 -c %s 2>&1 | \ +// RUN: FileCheck --check-prefix=X390 %s +// X390: "-target-feature" "-single-element-vec-fp64" +// X390: "-tune-cpu" "sifive-x390" + +// RUN: %clang -### --target=riscv64 -mexperimental-mtune-syntax \ +// RUN: -mtune=sifive-x280:single-element-vec-fp64 -c %s 2>&1 | \ +// RUN: FileCheck --check-prefix=X280 %s +// X280: "-target-feature" "+single-element-vec-fp64" +// X280: "-tune-cpu" "sifive-x280" + +// RUN: not %clang --target=riscv64 -mtune=sifive-x390:full-vec-fp64 -c %s 2>&1 | \ +// RUN: FileCheck --check-prefix=NO-EXPERIMENTAL %s +// RUN: not %clang --target=riscv64 -mexperimental-mtune-syntax \ +// RUN: -mtune=sifive-x390:full-vec-fp64 -mno-experimental-mtune-syntax -c %s 2>&1 | \ +// RUN: FileCheck --check-prefix=NO-EXPERIMENTAL %s +// NO-EXPERIMENTAL: invalid -mtune string 'sifive-x390:full-vec-fp64': +// NO-EXPERIMENTAL-SAME: require '-mexperimental-mtune-syntax' to use with tune feature string + +// RUN: not %clang --target=riscv64 -mexperimental-mtune-syntax \ +// RUN: -mtune=sifive-p470:full-vec-fp64 -c %s 2>&1 | \ +// RUN: FileCheck --check-prefix=NO-DIRECTIVE %s +// NO-DIRECTIVE: invalid tune feature string 'full-vec-fp64': +// NO-DIRECTIVE-SAME: Processor 'sifive-p470' has no configurable tuning features + +// RUN: not %clang --target=riscv64 -mexperimental-mtune-syntax \ +// RUN: -mtune=sifive-x280:full-vec-fp64,single-element-vec-fp64 -c %s 2>&1 | \ +// RUN: FileCheck --check-prefix=INVALID-DIRECTIVE %s +// INVALID-DIRECTIVE: invalid tune feature string 'full-vec-fp64,single-element-vec-fp64': +// INVALID-DIRECTIVE-SAME: Feature(s) 'single-element-vec-fp64' cannot appear in both positive and negative directives + +// RUN: not %clang --target=riscv64 -mexperimental-mtune-syntax \ +// RUN: -mtune=sifive-x280:prefer-w-inst -c %s 2>&1 | \ +// RUN: FileCheck --check-prefix=UNSUPPORTED-DIRECTIVE %s +// UNSUPPORTED-DIRECTIVE: invalid tune feature string 'prefer-w-inst': +// UNSUPPORTED-DIRECTIVE-SAME: Directive 'prefer-w-inst' is not allowed to be used with processor 'sifive-x280' >From a925f1e7963e498793963c086a32f24fcc9f3e90 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu <[email protected]> Date: Fri, 8 May 2026 15:15:03 -0700 Subject: [PATCH 2/3] fixup! Update documentation and release notes --- llvm/docs/RISCVUsage.rst | 6 +++--- llvm/docs/ReleaseNotes.md | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 2b68827e7b136..2e9b3a54b6c5c 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -644,12 +644,12 @@ Processor-Specific Tuning Feature String ======================================== Due to RISC-V's highly configurable nature, it is often desirable to share a single scheduling model across multiple similar RISC-V processors that only differ in a small number of (uArch) tuning features. An example of such tuning feature could be whether the latency of vector operations depend on VL or not. This could be extended to tuning features that are not directly connected to scheduling model but other parts of the RISC-V backend, like the cost of ``vrgather.vv`` instruction. -To that end, RISC-V LLVM supports a tuning feature string format that helps users to build a performance model by "configuring" an existing tune CPU, along with its scheduling model. For example, this string +To that end, RISC-V LLVM supports a tuning feature string format, through frontend flags like ``-mtune`` in Clang, to help users building a performance model by "configuring" an existing tune CPU, along with its scheduling model. For example, this flag :: - "sifive-x280:single-element-vec-fp64" + -mtune=sifive-x280:single-element-vec-fp64 -takes ``sifive-x280`` as the "base" tune CPU and configured it with ``single-element-vec-fp64``. This gives us a performance model that looks exactly like that of ``sifive-x280``, except some of the 64-bit vector floating point instructions now produce only a single element per cycle due to ``single-element-vec-fp64``. This string could eventually be used in places like ``-mtune`` at the frontend. +takes ``sifive-x280`` as the "base" tune CPU and configured it with ``single-element-vec-fp64``. This gives us a performance model that looks exactly like that of ``sifive-x280``, except some of the 64-bit vector floating point instructions now produce only a single element per cycle due to ``single-element-vec-fp64``. More formally speaking, each tuning feature string has the following format: diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 98f2205bc06a7..5b1fe33c23e48 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -203,6 +203,7 @@ Makes programs 10x faster by doing Special New Thing. * Support for the experimental `XRivosVisni` vendor extension has been removed. * Adds experimental assembler support for the 'Zvvmm` (RISC-V Integer Matrix Multiply-Accumulate) extension. * Adds support for 'Ziccid' (Instruction/Data Coherence and Consistency) extension. +* A new `-mtune` syntax that supports processor-specific tuning feature string is added. ### Changes to the WebAssembly Backend >From 5967e8d91291b895539352bcaaff413c6c9437e0 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu <[email protected]> Date: Mon, 8 Jun 2026 12:18:22 -0700 Subject: [PATCH 3/3] fixup! Move release note to Clang --- clang/docs/ReleaseNotes.rst | 3 +++ llvm/docs/ReleaseNotes.md | 1 - 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 2a7c315192f2d..02b561d3446a2 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -681,6 +681,9 @@ RISC-V Support - Tenstorrent Ascalon D8 was renamed to Ascalon X. Use `tt-ascalon-x` with `-mcpu` or `-mtune`. - Intrinsics were added for the 'Zvabd` (RISC-V Integer Vector Absolute Difference) extension. - Intrinsics were added for the 'Zvzip` (Reordering Structured Data in Vector Registers) extension. +- A new ``-mtune`` syntax was added to support processor-specific tuning feature string + Currently this new syntax is gated by the ``-mexperimental-mtune-syntax`` flag. + CUDA/HIP Language Changes ^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 5b1fe33c23e48..98f2205bc06a7 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -203,7 +203,6 @@ Makes programs 10x faster by doing Special New Thing. * Support for the experimental `XRivosVisni` vendor extension has been removed. * Adds experimental assembler support for the 'Zvvmm` (RISC-V Integer Matrix Multiply-Accumulate) extension. * Adds support for 'Ziccid' (Instruction/Data Coherence and Consistency) extension. -* A new `-mtune` syntax that supports processor-specific tuning feature string is added. ### Changes to the WebAssembly Backend _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
