================
@@ -1453,7 +1501,8 @@ unsigned
RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
// As the parser couldn't differentiate an VRM2/VRM4/VRM8 from an VR, coerce
// the register from VR to VRM2/VRM4/VRM8 if necessary.
- if (IsRegVR && (Kind == MCK_VRM2 || Kind == MCK_VRM4 || Kind == MCK_VRM8)) {
+ if (IsRegVR && (Kind == MCK_VRM2 || Kind == MCK_VRM2NoV0 ||
+ Kind == MCK_VRM4 || Kind == MCK_VRM8)) {
----------------
lukel97 wrote:
Same here
https://github.com/llvm/llvm-project/pull/202533
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