zatrazz wrote:
I followed the MSVC intrisinc more closely now, and checked using 19.51.36244
for ARM64:
* Intrinsics llvm.aarch64.{svc,hvc} are now i64 (i32 imm, i64, i64, i64, i64) —
a value-returning, non-variadic signature. Unused register slots are passed as
undef.
* Lowering (LowerINTRINSIC_W_CHAIN) models it as a small call: copy the
provided args into X0–X3, emit an AArch64ISD::SVC/HVC node with a caller-saved
clobber mask, and read the result from X0. undef operands are skipped, so
codegen is byte-identical to what cl emits.
* Sema limits the builtin to ≤5 arguments; CodeGen widens each arg to 64-bit
and truncates the X0 result to unsigned int (matching the MSVC prototype).
https://github.com/llvm/llvm-project/pull/202582
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