https://github.com/kieroxide updated https://github.com/llvm/llvm-project/pull/208694
>From 7c82569a370ad47a19249abf070dac2b1fddc82e Mon Sep 17 00:00:00 2001 From: Kieran Bailey <[email protected]> Date: Fri, 10 Jul 2026 10:28:38 +0000 Subject: [PATCH] [Clang][AArch64] Add ACLE _n variants for svdot_x2 intrinsics Add missing _n variants for the svdot_x2 ACLE intrinsics in arm_sve.td Add CodeGen tests in acle_sve2p1_dot.c to verify correct intrinsics are generated --- clang/include/clang/Basic/arm_sve.td | 4 ++ .../sve2p1-intrinsics/acle_sve2p1_dot.c | 55 +++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td index c084395ffd5df..9d6801f4ecc3e 100644 --- a/clang/include/clang/Basic/arm_sve.td +++ b/clang/include/clang/Basic/arm_sve.td @@ -2082,6 +2082,10 @@ def SVDOT_X2_S : SInst<"svdot[_{d}_{2}]", "ddhh", "i", MergeNone, "aarch64_sve_ def SVDOT_X2_U : SInst<"svdot[_{d}_{2}]", "ddhh", "Ui", MergeNone, "aarch64_sve_udot_x2", [VerifyRuntimeMode], []>; def SVDOT_X2_F : SInst<"svdot[_{d}_{2}]", "ddhh", "f", MergeNone, "aarch64_sve_fdot_x2", [VerifyRuntimeMode], []>; +def SVDOT_N_X2_S : SInst<"svdot[_n_{d}_{2}]", "ddhR", "i", MergeNone, "aarch64_sve_sdot_x2", [VerifyRuntimeMode], []>; +def SVDOT_N_X2_U : SInst<"svdot[_n_{d}_{2}]", "ddhR", "Ui", MergeNone, "aarch64_sve_udot_x2", [VerifyRuntimeMode], []>; +def SVDOT_N_X2_F : SInst<"svdot[_n_{d}_{2}]", "ddhR", "f", MergeNone, "aarch64_sve_fdot_x2", [VerifyRuntimeMode], []>; + def SVDOT_LANE_X2_S : SInst<"svdot_lane[_{d}_{2}]", "ddhhi", "i", MergeNone, "aarch64_sve_sdot_lane_x2", [VerifyRuntimeMode], [ImmCheck<3, ImmCheck0_3>]>; def SVDOT_LANE_X2_U : SInst<"svdot_lane[_{d}_{2}]", "ddhhi", "Ui", MergeNone, "aarch64_sve_udot_lane_x2", [VerifyRuntimeMode], [ImmCheck<3, ImmCheck0_3>]>; def SVDOT_LANE_X2_F : SInst<"svdot_lane[_{d}_{2}]", "ddhhi", "f", MergeNone, "aarch64_sve_fdot_lane_x2", [VerifyRuntimeMode], [ImmCheck<3, ImmCheck0_3>]>; diff --git a/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c b/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c index 704a245ed1460..b93f72e476c8d 100644 --- a/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c +++ b/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c @@ -72,7 +72,62 @@ svfloat32_t test_svdot_f32_x2(svfloat32_t op1, svfloat16_t op2, svfloat16_t op3) return SVE_ACLE_FUNC(svdot,_f32_f16,)(op1, op2, op3); } +// CHECK-LABEL: @test_svdot_n_s32_x2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP3:%.*]], i64 0 +// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[DOTSPLAT]]) +// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z19test_svdot_n_s32_x2u11__SVInt32_tu11__SVInt16_ts( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP3:%.*]], i64 0 +// CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[DOTSPLAT]]) +// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] +// +svint32_t test_svdot_n_s32_x2(svint32_t op1, svint16_t op2, int16_t op3) ATTR +{ + return SVE_ACLE_FUNC(svdot,_n_s32_s16,)(op1, op2, op3); +} +// CHECK-LABEL: @test_svdot_n_u32_x2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP3:%.*]], i64 0 +// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[DOTSPLAT]]) +// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z19test_svdot_n_u32_x2u12__SVUint32_tu12__SVUint16_tt( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP3:%.*]], i64 0 +// CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i16> [[DOTSPLAT]]) +// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] +// +svuint32_t test_svdot_n_u32_x2(svuint32_t op1, svuint16_t op2, uint16_t op3) ATTR +{ + return SVE_ACLE_FUNC(svdot,_n_u32_u16,)(op1, op2, op3); +} + +// CHECK-LABEL: @test_svdot_n_f32_x2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x half> poison, half [[OP3:%.*]], i64 0 +// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x half> [[DOTSPLATINSERT]], <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[DOTSPLAT]]) +// CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z19test_svdot_n_f32_x2u13__SVFloat32_tu13__SVFloat16_tDh( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x half> poison, half [[OP3:%.*]], i64 0 +// CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x half> [[DOTSPLATINSERT]], <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[DOTSPLAT]]) +// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]] +// +svfloat32_t test_svdot_n_f32_x2(svfloat32_t op1, svfloat16_t op2, float16_t op3) ATTR +{ + return SVE_ACLE_FUNC(svdot,_n_f32_f16,)(op1, op2, op3); +} // CHECK-LABEL: @test_svdot_lane_s32_x2( // CHECK-NEXT: entry: _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
