https://github.com/jacquesguan created https://github.com/llvm/llvm-project/pull/211490
None >From 6286fe8dc0e2de2cfdc21cf0d05b537057ca925d Mon Sep 17 00:00:00 2001 From: Jianjian GUAN <[email protected]> Date: Wed, 22 Jul 2026 14:47:23 +0800 Subject: [PATCH] [CIR][RISCV] Support XAndesPerf builtins --- clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp | 20 +++++++-- .../RISCV/riscv-xandesperf-rv32.c | 43 +++++++++++++++++++ .../RISCV/riscv-xandesperf-rv64.c | 43 +++++++++++++++++++ 3 files changed, 102 insertions(+), 4 deletions(-) create mode 100644 clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xandesperf-rv32.c create mode 100644 clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xandesperf-rv64.c diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp index 25e714a612147..82c35de648581 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp @@ -266,13 +266,25 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) { } // XAndesPerf case RISCV::BI__builtin_riscv_nds_ffb_32: - case RISCV::BI__builtin_riscv_nds_ffb_64: + case RISCV::BI__builtin_riscv_nds_ffb_64: { + intrinsicName = "riscv.nds.ffb"; + break; + } case RISCV::BI__builtin_riscv_nds_ffzmism_32: - case RISCV::BI__builtin_riscv_nds_ffzmism_64: + case RISCV::BI__builtin_riscv_nds_ffzmism_64: { + intrinsicName = "riscv.nds.ffzmism"; + break; + } case RISCV::BI__builtin_riscv_nds_ffmism_32: - case RISCV::BI__builtin_riscv_nds_ffmism_64: + case RISCV::BI__builtin_riscv_nds_ffmism_64: { + intrinsicName = "riscv.nds.ffmism"; + break; + } case RISCV::BI__builtin_riscv_nds_flmism_32: - case RISCV::BI__builtin_riscv_nds_flmism_64: + case RISCV::BI__builtin_riscv_nds_flmism_64: { + intrinsicName = "riscv.nds.flmism"; + break; + } // XAndesBFHCvt case RISCV::BI__builtin_riscv_nds_fcvt_s_bf16: case RISCV::BI__builtin_riscv_nds_fcvt_bf16_s: { diff --git a/clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xandesperf-rv32.c b/clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xandesperf-rv32.c new file mode 100644 index 0000000000000..6f25b8655c0b2 --- /dev/null +++ b/clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xandesperf-rv32.c @@ -0,0 +1,43 @@ +// RUN: %clang_cc1 -triple riscv32 -target-feature +xandesperf -fclangir -emit-cir %s -o - | FileCheck %s --check-prefix=CIR +// RUN: %clang_cc1 -triple riscv32 -target-feature +xandesperf -fclangir -emit-llvm %s -o - | FileCheck %s --check-prefix=LLVM +// RUN: %clang_cc1 -triple riscv32 -target-feature +xandesperf -emit-llvm %s -o - | FileCheck %s --check-prefix=LLVM + +// CIR-LABEL: cir.func{{.*}} @test_ffb( +// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.nds.ffb" {{%.*}}, {{%.*}} : (!u32i, !u32i) -> !s32i +// CIR: cir.return +// LLVM-LABEL: @test_ffb( +// LLVM: call i32 @llvm.riscv.nds.ffb.i32(i32 {{%.*}}, i32 {{%.*}}) +// LLVM: ret i32 +int test_ffb(unsigned int a, unsigned int b) { + return __builtin_riscv_nds_ffb_32(a, b); +} + +// CIR-LABEL: cir.func{{.*}} @test_ffzmism( +// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.nds.ffzmism" {{%.*}}, {{%.*}} : (!u32i, !u32i) -> !s32i +// CIR: cir.return +// LLVM-LABEL: @test_ffzmism( +// LLVM: call i32 @llvm.riscv.nds.ffzmism.i32(i32 {{%.*}}, i32 {{%.*}}) +// LLVM: ret i32 +int test_ffzmism(unsigned int a, unsigned int b) { + return __builtin_riscv_nds_ffzmism_32(a, b); +} + +// CIR-LABEL: cir.func{{.*}} @test_ffmism( +// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.nds.ffmism" {{%.*}}, {{%.*}} : (!u32i, !u32i) -> !s32i +// CIR: cir.return +// LLVM-LABEL: @test_ffmism( +// LLVM: call i32 @llvm.riscv.nds.ffmism.i32(i32 {{%.*}}, i32 {{%.*}}) +// LLVM: ret i32 +int test_ffmism(unsigned int a, unsigned int b) { + return __builtin_riscv_nds_ffmism_32(a, b); +} + +// CIR-LABEL: cir.func{{.*}} @test_flmism( +// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.nds.flmism" {{%.*}}, {{%.*}} : (!u32i, !u32i) -> !s32i +// CIR: cir.return +// LLVM-LABEL: @test_flmism( +// LLVM: call i32 @llvm.riscv.nds.flmism.i32(i32 {{%.*}}, i32 {{%.*}}) +// LLVM: ret i32 +int test_flmism(unsigned int a, unsigned int b) { + return __builtin_riscv_nds_flmism_32(a, b); +} diff --git a/clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xandesperf-rv64.c b/clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xandesperf-rv64.c new file mode 100644 index 0000000000000..1aa66bc05d28f --- /dev/null +++ b/clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xandesperf-rv64.c @@ -0,0 +1,43 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +xandesperf -fclangir -emit-cir %s -o - | FileCheck %s --check-prefix=CIR +// RUN: %clang_cc1 -triple riscv64 -target-feature +xandesperf -fclangir -emit-llvm %s -o - | FileCheck %s --check-prefix=LLVM +// RUN: %clang_cc1 -triple riscv64 -target-feature +xandesperf -emit-llvm %s -o - | FileCheck %s --check-prefix=LLVM + +// CIR-LABEL: cir.func{{.*}} @test_ffb( +// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.nds.ffb" {{%.*}}, {{%.*}} : (!u64i, !u64i) -> !s64i +// CIR: cir.return +// LLVM-LABEL: @test_ffb( +// LLVM: call i64 @llvm.riscv.nds.ffb.i64(i64 {{%.*}}, i64 {{%.*}}) +// LLVM: ret i64 +long long test_ffb(unsigned long long a, unsigned long long b) { + return __builtin_riscv_nds_ffb_64(a, b); +} + +// CIR-LABEL: cir.func{{.*}} @test_ffzmism( +// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.nds.ffzmism" {{%.*}}, {{%.*}} : (!u64i, !u64i) -> !s64i +// CIR: cir.return +// LLVM-LABEL: @test_ffzmism( +// LLVM: call i64 @llvm.riscv.nds.ffzmism.i64(i64 {{%.*}}, i64 {{%.*}}) +// LLVM: ret i64 +long long test_ffzmism(unsigned long long a, unsigned long long b) { + return __builtin_riscv_nds_ffzmism_64(a, b); +} + +// CIR-LABEL: cir.func{{.*}} @test_ffmism( +// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.nds.ffmism" {{%.*}}, {{%.*}} : (!u64i, !u64i) -> !s64i +// CIR: cir.return +// LLVM-LABEL: @test_ffmism( +// LLVM: call i64 @llvm.riscv.nds.ffmism.i64(i64 {{%.*}}, i64 {{%.*}}) +// LLVM: ret i64 +long long test_ffmism(unsigned long long a, unsigned long long b) { + return __builtin_riscv_nds_ffmism_64(a, b); +} + +// CIR-LABEL: cir.func{{.*}} @test_flmism( +// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.nds.flmism" {{%.*}}, {{%.*}} : (!u64i, !u64i) -> !s64i +// CIR: cir.return +// LLVM-LABEL: @test_flmism( +// LLVM: call i64 @llvm.riscv.nds.flmism.i64(i64 {{%.*}}, i64 {{%.*}}) +// LLVM: ret i64 +long long test_flmism(unsigned long long a, unsigned long long b) { + return __builtin_riscv_nds_flmism_64(a, b); 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