Author: Pengcheng Wang Date: 2026-07-30T14:50:25+08:00 New Revision: 23a22244b099a9950a5f265460e392bc44beb3b4
URL: https://github.com/llvm/llvm-project/commit/23a22244b099a9950a5f265460e392bc44beb3b4 DIFF: https://github.com/llvm/llvm-project/commit/23a22244b099a9950a5f265460e392bc44beb3b4.diff LOG: [RISCV][MC] Support experimental Zilx extension This adds the MC support for `Zilx` (Indexed Integer Load Instructions) extension. Doc: https://github.com/riscv/riscv-zilx Reviewers: topperc, tclin914, kito-cheng Pull Request: https://github.com/llvm/llvm-project/pull/209419 Added: llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td llvm/test/MC/RISCV/zilx-invalid.s llvm/test/MC/RISCV/zilx-valid-rv32.s llvm/test/MC/RISCV/zilx-valid-rv64.s Modified: clang/test/Driver/print-supported-extensions-riscv.c clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.md llvm/lib/Target/RISCV/RISCVFeatures.td llvm/lib/Target/RISCV/RISCVInstrInfo.td llvm/test/CodeGen/RISCV/attributes.ll llvm/test/CodeGen/RISCV/features-info.ll llvm/unittests/TargetParser/RISCVISAInfoTest.cpp Removed: ################################################################################ diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index a9af276367817..fa0e6802bcefa 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -249,6 +249,7 @@ // CHECK-NEXT: zibi 0.1 'Zibi' (Branch with Immediate) // CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad) // CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack) +// CHECK-NEXT: zilx 0.1 'Zilx' (Indexed Integer Load Instructions) // CHECK-NEXT: zvabd 0.7 'Zvabd' (Vector Absolute Difference) // CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements) // CHECK-NEXT: zvdot4a8i 0.1 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 28031814da16a..bf9689d7462aa 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -129,6 +129,7 @@ // CHECK-NOT: __riscv_zihintpause {{.*$}} // CHECK-NOT: __riscv_zihpm {{.*$}} // CHECK-NOT: __riscv_zilsd {{.*$}} +// CHECK-NOT: __riscv_zilx {{.*$}} // CHECK-NOT: __riscv_zimop {{.*$}} // CHECK-NOT: __riscv_zk {{.*$}} // CHECK-NOT: __riscv_zkn {{.*$}} diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index fae34e793e6ca..b11ef40489d18 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -383,6 +383,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zvqwbdota8i``, ``experimental-zvqwbdota16i``, ``experimental-zvfqwbdota8f``, ``experimental-zvfwbdota16bf``, ``experimental-zvfbdota32f`` LLVM implements the `0.2 draft specification <https://github.com/aswaterman/riscv-misc/blob/main/isa/ldot-bdot/ldot-bdot.adoc>`__. +``experimental-zilx`` + LLVM implements the `0.1 draft specification <https://github.com/riscv/riscv-zilx>`__. + To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`. Vendor Extensions diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 3a88da50ff8b3..b9ee0425d06f7 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -89,6 +89,8 @@ Makes programs 10x faster by doing Special New Thing. ### Changes to the RISC-V Backend +* Adds experimental assembler support for the `Zilx` (Indexed Integer Load) extension. + ### Changes to the WebAssembly Backend ### Changes to the Windows Target diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 03d28b8448ba4..a6e9839bc22a7 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -204,6 +204,13 @@ def FeatureZilsdWordAlign : SubtargetFeature<"zilsd-word-align", "AllowZilsdWordAlign", "true", "Allow 4-byte alignment for Zilsd LD/SD instructions">; +def FeatureStdExtZilx + : RISCVExperimentalExtension<0, 1, "Indexed Integer Load Instructions">; +def HasStdExtZilx + : Predicate<"Subtarget->hasStdExtZilx()">, + AssemblerPredicate<(all_of FeatureStdExtZilx), + "'Zilx' (Indexed Integer Load Instructions)">; + // Multiply Extensions def FeatureStdExtZmmul diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index ca506b8013212..5a4ceba81931c 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -2370,6 +2370,7 @@ include "RISCVInstrInfoZicbo.td" include "RISCVInstrInfoZicond.td" include "RISCVInstrInfoZilsd.td" include "RISCVInstrInfoZibi.td" +include "RISCVInstrInfoZilx.td" // Scalar FP include "RISCVInstrInfoF.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td new file mode 100644 index 0000000000000..1db547a77daa7 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td @@ -0,0 +1,95 @@ +//===-- RISCVInstrInfoZilx.td - 'Zilx' instructions --------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// This file describes the RISC-V instructions for 'Zilx' (Indexed Integer +/// Load). +/// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction class templates +//===----------------------------------------------------------------------===// + +// Zilx indexed loads reuse the AMO major opcode. The addressing mode is +// selected by funct5 (inst[31:27]) and the access width/signedness reuses the +// base integer load funct3. rs1 is the index operand, rs2 is the base operand, +// and the aq and rl bits are always 0. The base register is written in +// parentheses to distinguish it from the index register. +let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in +class ZilxLoad<bits<5> funct5, bits<3> funct3, string opcodestr> + : RVInstRAtomic<funct5, /*aq=*/0, /*rl=*/0, funct3, OPC_AMO, + (outs GPR:$rd), (ins GPRMemZeroOffset:$rs2, GPR:$rs1), + opcodestr, "$rd, $rs2, $rs1">; + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +let Predicates = [HasStdExtZilx] in { +// Unscaled indexed loads: address = base + index. Byte loads are not provided +// in the unscaled mode. +def LXH : ZilxLoad<0b10010, 0b001, "lxh">, + Sched<[WriteLDH, ReadMemBase, ReadMemBase]>; +def LXW : ZilxLoad<0b10010, 0b010, "lxw">, + Sched<[WriteLDW, ReadMemBase, ReadMemBase]>; +def LXHU : ZilxLoad<0b10010, 0b101, "lxhu">, + Sched<[WriteLDH, ReadMemBase, ReadMemBase]>; + +// Scaled indexed loads: address = base + (index << log2(access-size)). Byte +// loads are provided only in scaled form (the byte scale factor is 1). +def LXSB : ZilxLoad<0b11010, 0b000, "lxsb">, + Sched<[WriteLDB, ReadMemBase, ReadMemBase]>; +def LXSH : ZilxLoad<0b11010, 0b001, "lxsh">, + Sched<[WriteLDH, ReadMemBase, ReadMemBase]>; +def LXSW : ZilxLoad<0b11010, 0b010, "lxsw">, + Sched<[WriteLDW, ReadMemBase, ReadMemBase]>; +def LXSBU : ZilxLoad<0b11010, 0b100, "lxsbu">, + Sched<[WriteLDB, ReadMemBase, ReadMemBase]>; +def LXSHU : ZilxLoad<0b11010, 0b101, "lxshu">, + Sched<[WriteLDH, ReadMemBase, ReadMemBase]>; + +let append Predicates = [IsRV64] in { +// Unscaled indexed loads (RV64-only widths). +def LXD : ZilxLoad<0b10010, 0b011, "lxd">, + Sched<[WriteLDD, ReadMemBase, ReadMemBase]>; +def LXWU : ZilxLoad<0b10010, 0b110, "lxwu">, + Sched<[WriteLDW, ReadMemBase, ReadMemBase]>; + +// Scaled indexed loads (RV64-only widths). +def LXSD : ZilxLoad<0b11010, 0b011, "lxsd">, + Sched<[WriteLDD, ReadMemBase, ReadMemBase]>; +def LXSWU : ZilxLoad<0b11010, 0b110, "lxswu">, + Sched<[WriteLDW, ReadMemBase, ReadMemBase]>; + +// Scaled indexed loads with a zero-extended 32-bit index (RV64-only): +// address = base + (zext32(index) << log2(access-size)). +def LXSUWB : ZilxLoad<0b11110, 0b000, "lxsuwb">, + Sched<[WriteLDB, ReadMemBase, ReadMemBase]>; +def LXSUWH : ZilxLoad<0b11110, 0b001, "lxsuwh">, + Sched<[WriteLDH, ReadMemBase, ReadMemBase]>; +def LXSUWW : ZilxLoad<0b11110, 0b010, "lxsuww">, + Sched<[WriteLDW, ReadMemBase, ReadMemBase]>; +def LXSUWD : ZilxLoad<0b11110, 0b011, "lxsuwd">, + Sched<[WriteLDD, ReadMemBase, ReadMemBase]>; +def LXSUWBU : ZilxLoad<0b11110, 0b100, "lxsuwbu">, + Sched<[WriteLDB, ReadMemBase, ReadMemBase]>; +def LXSUWHU : ZilxLoad<0b11110, 0b101, "lxsuwhu">, + Sched<[WriteLDH, ReadMemBase, ReadMemBase]>; +def LXSUWWU : ZilxLoad<0b11110, 0b110, "lxsuwwu">, + Sched<[WriteLDW, ReadMemBase, ReadMemBase]>; +} // append Predicates = [IsRV64] + +} // Predicates = [HasStdExtZilx] + +// `lxb`/`lxbu` are assembler pseudoinstructions for the scaled byte loads. +// They are parse-only aliases (EmitPriority 0) so the disassembler still prints +// the underlying `lxsb`/`lxsbu`. +let Predicates = [HasStdExtZilx] in { +def : InstAlias<"lxb $rd, $rs2, $rs1", (LXSB GPR:$rd, GPRMemZeroOffset:$rs2, GPR:$rs1), 0>; +def : InstAlias<"lxbu $rd, $rs2, $rs1", (LXSBU GPR:$rd, GPRMemZeroOffset:$rs2, GPR:$rs1), 0>; +} diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 26ffd8bb4ec89..566786526dc7c 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -152,6 +152,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+ssctr %s -o - | FileCheck --check-prefix=RV32SSCTR %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-p %s -o - | FileCheck --check-prefix=RV32P %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zibi %s -o - | FileCheck --check-prefix=RV32ZIBI %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zilx %s -o - | FileCheck --check-prefix=RV32ZILX %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvqwbdota8i %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVQWBDOTA8I %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvqwbdota16i %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVQWBDOTA16I %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfwbdota16bf %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFWBDOTA16BF %s @@ -320,6 +321,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-p %s -o - | FileCheck --check-prefix=RV64P %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-y %s -o - | FileCheck --check-prefix=RV64Y %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zibi %s -o - | FileCheck --check-prefix=RV64ZIBI %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zilx %s -o - | FileCheck --check-prefix=RV64ZILX %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvqwbdota8i %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVQWBDOTA8I %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvqwbdota16i %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVQWBDOTA16I %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfwbdota16bf %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFWBDOTA16BF %s @@ -457,6 +459,7 @@ ; RV32ZVABD: .attribute 5, "rv32i2p1_zicsr2p0_zvabd0p7_zve32x1p0_zvl32b1p0" ; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0" ; RV32ZILSD: .attribute 5, "rv32i2p1_zilsd1p0" +; RV32ZILX: .attribute 5, "rv32i2p1_zilx0p1" ; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop1p0" ; RV32ZCLSD: .attribute 5, "rv32i2p1_c2p0_zilsd1p0_zca1p0_zclsd1p0" ; RV32ZCMOP: .attribute 5, "rv32i2p1_c2p0_zca1p0_zcmop1p0" @@ -621,6 +624,7 @@ ; RV64ZVFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0" ; RV64ZVABD: .attribute 5, "rv64i2p1_zicsr2p0_zvabd0p7_zve32x1p0_zvl32b1p0" ; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0" +; RV64ZILX: .attribute 5, "rv64i2p1_zilx0p1" ; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop1p0" ; RV64ZCMOP: .attribute 5, "rv64i2p1_c2p0_zca1p0_zcmop1p0" ; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0" diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index a6ac7487a816e..679af65c8ee31 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -33,6 +33,7 @@ ; CHECK-NEXT: experimental-zibi - 'Zibi' (Branch with Immediate). ; CHECK-NEXT: experimental-zicfilp - 'Zicfilp' (Landing pad). ; CHECK-NEXT: experimental-zicfiss - 'Zicfiss' (Shadow stack). +; CHECK-NEXT: experimental-zilx - 'Zilx' (Indexed Integer Load Instructions). ; CHECK-NEXT: experimental-zvabd - 'Zvabd' (Vector Absolute Difference). ; CHECK-NEXT: experimental-zvbc32e - 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements). ; CHECK-NEXT: experimental-zvdot4a8i - 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers). diff --git a/llvm/test/MC/RISCV/zilx-invalid.s b/llvm/test/MC/RISCV/zilx-invalid.s new file mode 100644 index 0000000000000..03a528c6c86f2 --- /dev/null +++ b/llvm/test/MC/RISCV/zilx-invalid.s @@ -0,0 +1,40 @@ +# RUN: not llvm-mc -triple=riscv32 --mattr=+experimental-zilx %s 2>&1 \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ERROR,CHECK-RV32-ERROR +# RUN: not llvm-mc -triple=riscv64 --mattr=+experimental-zilx %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +# The base register must be written in parentheses; the bare three-register +# syntax is not accepted. +# CHECK-ERROR: :[[@LINE+1]]:9: error: expected '(' or optional integer offset +lxh a0, a1, a2 + +# Only a zero offset may precede the parenthesized base register. +# CHECK-ERROR: :[[@LINE+1]]:10: error: expected '(' after optional integer offset +lxh a0, 1, a2 + +# The base operand must be a register. +# CHECK-ERROR: :[[@LINE+1]]:10: error: expected register +lxh a0, (1), a2 + +# CHECK-ERROR: :[[@LINE+1]]:9: error: expected '(' or optional integer offset +lxh a0, a1 + +# Doubleword and unsigned-word forms are RV64-only. +# CHECK-RV32-ERROR: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +lxd a0, (a1), a2 + +# CHECK-RV32-ERROR: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +lxwu a0, (a1), a2 + +# CHECK-RV32-ERROR: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +lxsd a0, (a1), a2 + +# CHECK-RV32-ERROR: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +lxswu a0, (a1), a2 + +# The scaled unsigned-word-index loads are RV64-only. +# CHECK-RV32-ERROR: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +lxsuwb a0, (a1), a2 + +# CHECK-RV32-ERROR: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +lxsuwwu a0, (a1), a2 diff --git a/llvm/test/MC/RISCV/zilx-valid-rv32.s b/llvm/test/MC/RISCV/zilx-valid-rv32.s new file mode 100644 index 0000000000000..ce60fafa5cdaa --- /dev/null +++ b/llvm/test/MC/RISCV/zilx-valid-rv32.s @@ -0,0 +1,63 @@ +# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-zilx %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zilx %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-zilx --no-print-imm-hex - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST + +# Unscaled indexed loads. + +lxh a0, (a1), a2 +# CHECK-INST: lxh a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x15,0xb6,0x90] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} + +lxw a0, (a1), a2 +# CHECK-INST: lxw a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x25,0xb6,0x90] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} + +lxhu a0, (a1), a2 +# CHECK-INST: lxhu a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x55,0xb6,0x90] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} + +# Scaled indexed loads. + +lxsb a0, (a1), a2 +# CHECK-INST: lxsb a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x05,0xb6,0xd0] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} + +lxsh a0, (a1), a2 +# CHECK-INST: lxsh a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x15,0xb6,0xd0] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} + +lxsw a0, (a1), a2 +# CHECK-INST: lxsw a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x25,0xb6,0xd0] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} + +lxsbu a0, (a1), a2 +# CHECK-INST: lxsbu a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x45,0xb6,0xd0] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} + +lxshu a0, (a1), a2 +# CHECK-INST: lxshu a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x55,0xb6,0xd0] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} + +# `lxb` and `lxbu` are assembler pseudoinstructions for `lxsb` and `lxsbu`. + +lxb a0, (a1), a2 +# CHECK-INST: lxsb a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x05,0xb6,0xd0] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} + +lxbu a0, (a1), a2 +# CHECK-INST: lxsbu a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x45,0xb6,0xd0] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} diff --git a/llvm/test/MC/RISCV/zilx-valid-rv64.s b/llvm/test/MC/RISCV/zilx-valid-rv64.s new file mode 100644 index 0000000000000..d27e7969f503f --- /dev/null +++ b/llvm/test/MC/RISCV/zilx-valid-rv64.s @@ -0,0 +1,68 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zilx %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zilx %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-zilx --no-print-imm-hex - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST + +# Unscaled indexed loads (RV64-only widths). + +lxd a0, (a1), a2 +# CHECK-INST: lxd a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x35,0xb6,0x90] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} + +lxwu a0, (a1), a2 +# CHECK-INST: lxwu a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x65,0xb6,0x90] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} + +# Scaled indexed loads (RV64-only widths). + +lxsd a0, (a1), a2 +# CHECK-INST: lxsd a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x35,0xb6,0xd0] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} + +lxswu a0, (a1), a2 +# CHECK-INST: lxswu a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x65,0xb6,0xd0] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} + +# Scaled indexed loads with a zero-extended 32-bit index (RV64-only). + +lxsuwb a0, (a1), a2 +# CHECK-INST: lxsuwb a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x05,0xb6,0xf0] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} + +lxsuwh a0, (a1), a2 +# CHECK-INST: lxsuwh a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x15,0xb6,0xf0] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} + +lxsuww a0, (a1), a2 +# CHECK-INST: lxsuww a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x25,0xb6,0xf0] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} + +lxsuwd a0, (a1), a2 +# CHECK-INST: lxsuwd a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x35,0xb6,0xf0] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} + +lxsuwbu a0, (a1), a2 +# CHECK-INST: lxsuwbu a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x45,0xb6,0xf0] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} + +lxsuwhu a0, (a1), a2 +# CHECK-INST: lxsuwhu a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x55,0xb6,0xf0] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} + +lxsuwwu a0, (a1), a2 +# CHECK-INST: lxsuwwu a0, (a1), a2 +# CHECK-ENCODING: [0x2f,0x65,0xb6,0xf0] +# CHECK-ERROR: instruction requires the following: 'Zilx' (Indexed Integer Load Instructions){{$}} diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index cdc2fcea37fcb..449f27fad3f54 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1618,6 +1618,7 @@ Experimental extensions zibi 0.1 zicfilp 1.0 This is a long dummy description zicfiss 1.0 + zilx 0.1 zvabd 0.7 zvbc32e 0.7 zvdot4a8i 0.1 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
