================
@@ -133,10 +133,16 @@ void RISCVInstPrinter::printCSRSystemRegister(const
MCInst *MI, unsigned OpNo,
raw_ostream &O) {
unsigned Imm = MI->getOperand(OpNo).getImm();
auto Range = RISCVSysReg::lookupSysRegByEncoding(Imm);
+ bool PreferFeatureSpecific = llvm::any_of(Range, [&](const auto &Reg) {
----------------
zeyi2 wrote:
Hi lenary, sorry for the late reply. I did some digging into the specification
history.
First, a correction to my earlier comment:
> And I found that it exposed an encoding collision with the SiFive CLIC CSRs
> sf.mscratchcsw.
I mistakenly referred to `sf.mscratchcsw` while the conflicting one is actually
`sf.mscratchcswl`. Really sorry for the confusion.
I also dived into the commits of ACLIC repo, and the history suggests that
there was no direct rename from `mscratchcswl` to `mspcs`. The old CLIC
scratch-swap CSR was removed when the specification moved to the [CLIC-on-AIA
design](https://github.com/riscv/riscv-fast-interrupt/pull/464). It was
subsequently redesigned in [this
PR](https://github.com/riscv/riscv-fast-interrupt/pull/547), which removes the
dependence on interrupt levels and ["works independent of any other CLIC
extensions"](https://github.com/riscv/riscv-fast-interrupt/commit/98031e824c59bcab2fde086d3693872b68fe181a).
So starting from here, the new stack-pointer swap no longer uses [`pil == 0 /
mil ==
0`](https://github.com/riscv/riscv-fast-interrupt/blob/faa80cf62e8349e5619c1776009cbdd5d5a010c1/src/clic.adoc?plain=1#L1193-L1217)
to determine whether a swap was required.
The new CSR was initially named `msp`. Its address was later moved from `0x348`
to `0x349` in [PR
#695](https://github.com/riscv/riscv-fast-interrupt/pull/695/files), and [PR
#784](https://github.com/riscv/riscv-fast-interrupt/pull/784/files) then
renamed it from `msp` to `mspcs` without changing its behavior.
The current ACLIC design stores the alternative stack pointer in the
independent `mspcs` CSR and uses the
[`mcspspush`](https://github.com/riscv/riscv-fast-interrupt/blob/6164eca8c8c9138e519ea3b8510655b2b5bb76d0/src/aclic.adoc?plain=1#L1457-L1465)
and
[`mcspspop`](https://github.com/riscv/riscv-fast-interrupt/blob/6164eca8c8c9138e519ea3b8510655b2b5bb76d0/src/aclic.adoc?plain=1#L1494-L1508)
instructions.
Therefore, although `sf.mscratchcswl` and `mspcs` share the same CSR encoding,
IMO they appear to represent different architectural mechanisms rather than two
names for the same CSR.
https://github.com/llvm/llvm-project/pull/211712
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