https://github.com/AmrDeveloper updated https://github.com/llvm/llvm-project/pull/216395
>From d1a99e7b50c1b2f3a2923d6e786108f3093e2639 Mon Sep 17 00:00:00 2001 From: Amr Hesham <[email protected]> Date: Fri, 14 Aug 2026 22:06:46 +0200 Subject: [PATCH] [CIR][NFC] Remove unnecessary casts in LowerToLLVM --- .../CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp index 4210b64a4c418..3b1aa25712622 100644 --- a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp +++ b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp @@ -682,7 +682,7 @@ mlir::Value CIRAttrToValue::visitCirAttr(cir::FPAttr fltAttr) { /// ConstComplexAttr visitor. mlir::Value CIRAttrToValue::visitCirAttr(cir::ConstComplexAttr complexAttr) { - auto complexType = mlir::cast<cir::ComplexType>(complexAttr.getType()); + cir::ComplexType complexType = complexAttr.getType(); mlir::Type complexElemTy = complexType.getElementType(); mlir::Type complexElemLLVMTy = converter->convertType(complexElemTy); @@ -1069,7 +1069,7 @@ class GlobalInitAttrRewriter { llvm::APInt val = attr.getValue(); auto destTy = mlir::cast<mlir::IntegerType>(llvmType); if (val.getBitWidth() != destTy.getWidth()) { - auto cirIntTy = mlir::cast<cir::IntType>(attr.getType()); + cir::IntTypeInterface cirIntTy = attr.getType(); val = cirIntTy.isSigned() ? val.sext(destTy.getWidth()) : val.zext(destTy.getWidth()); } @@ -4816,7 +4816,7 @@ mlir::LogicalResult CIRToLLVMVecCreateOpLowering::matchAndRewrite( mlir::ConversionPatternRewriter &rewriter) const { // Start with an 'undef' value for the vector. Then 'insertelement' for // each of the vector elements. - const auto vecTy = mlir::cast<cir::VectorType>(op.getType()); + const cir::VectorType vecTy = op.getType(); const mlir::Type llvmTy = typeConverter->convertType(vecTy); const mlir::Location loc = op.getLoc(); mlir::Value result = mlir::LLVM::PoisonOp::create(rewriter, loc, llvmTy); @@ -4862,9 +4862,8 @@ mlir::LogicalResult CIRToLLVMVecCmpOpLowering::matchAndRewrite( adaptor.getLhs(), adaptor.getRhs()); } else if (mlir::isa<cir::FPTypeInterface>(elementType)) { if (cir::FenvAttr fenv = op.getFenvAttr()) { - auto i1VecTy = mlir::VectorType::get( - mlir::cast<cir::VectorType>(op.getLhs().getType()).getSize(), - rewriter.getI1Type()); + auto i1VecTy = mlir::VectorType::get(op.getLhs().getType().getSize(), + rewriter.getI1Type()); bitResult = createConstrainedFCmpCall(rewriter, op.getLoc(), adaptor.getLhs(), adaptor.getRhs(), op.getKind(), fenv, i1VecTy) @@ -4881,8 +4880,7 @@ mlir::LogicalResult CIRToLLVMVecCmpOpLowering::matchAndRewrite( // LLVM IR vector comparison returns a vector of i1. This one-bit vector // must be sign-extended to the correct result type, unless a vector of i1 is // the type we need. - if (cast<cir::IntType>(cast<cir::VectorType>(op.getType()).getElementType()) - .getWidth() > 1) + if (cast<cir::IntType>(op.getType().getElementType()).getWidth() > 1) rewriter.replaceOpWithNewOp<mlir::LLVM::SExtOp>( op, typeConverter->convertType(op.getType()), bitResult); else @@ -4975,9 +4973,8 @@ mlir::LogicalResult CIRToLLVMVecShuffleDynamicOpLowering::matchAndRewrite( mlir::Type llvmIndexVecType = getTypeConverter()->convertType(op.getIndices().getType()); mlir::Type llvmIndexType = getTypeConverter()->convertType( - elementTypeIfVector(op.getIndices().getType())); - uint64_t numElements = - mlir::cast<cir::VectorType>(op.getVec().getType()).getSize(); + op.getIndices().getType().getElementType()); + uint64_t numElements = op.getVec().getType().getSize(); uint64_t maskBits = llvm::NextPowerOf2(numElements - 1) - 1; mlir::Value maskValue = mlir::LLVM::ConstantOp::create( _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
