Author: Andrzej Warzyński Date: 2026-08-17T10:46:52+01:00 New Revision: cfd277e2eff7ee8b9740481c0ded3caa4c5b1d7d
URL: https://github.com/llvm/llvm-project/commit/cfd277e2eff7ee8b9740481c0ded3caa4c5b1d7d DIFF: https://github.com/llvm/llvm-project/commit/cfd277e2eff7ee8b9740481c0ded3caa4c5b1d7d.diff LOG: [clang][CIR][AArch64] Add lowering for conversion intrinsics (#211609) This PR adds lowering for intrinsic from the following groups: * https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions It continues the work started in #190961, #193273, #199990 and #209252. This PR implements the remaining conversions truncating to zero: * vcvts_s32_f32 * vcvts_s64_f32 * vcvts_u32_f32 * vcvts_u64_f32 The corresponding tests are moved from: * clang/test/CodeGen/AArch64/ to: * clang/test/CodeGen/AArch64/neon/ The lowering follows the existing implementation in CodeGen/TargetBuiltins/ARM.cpp Added: Modified: clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c clang/test/CodeGen/AArch64/neon/intrinsics.c Removed: ################################################################################ diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index 838d5af867c8d..932ac936e98a1 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -447,6 +447,10 @@ emitCommonNeonSISDBuiltinExpr(CIRGenFunction &cgf, case NEON::BI__builtin_neon_vcvtd_n_f64_u64: case NEON::BI__builtin_neon_vcvtd_n_s64_f64: case NEON::BI__builtin_neon_vcvtd_n_u64_f64: + case NEON::BI__builtin_neon_vcvts_s32_f32: + case NEON::BI__builtin_neon_vcvts_s64_f32: + case NEON::BI__builtin_neon_vcvts_u32_f32: + case NEON::BI__builtin_neon_vcvts_u64_f32: case NEON::BI__builtin_neon_vaddlv_s32: case NEON::BI__builtin_neon_vaddlv_u32: case NEON::BI__builtin_neon_vaddlvq_s32: diff --git a/clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c b/clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c index 5a59f80cb0363..a128227cbe5d1 100644 --- a/clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c @@ -335,44 +335,3 @@ uint64_t test_vcvtps_u64_f32(float32_t a) { uint32_t test_vcvtpd_u32_f64(float64_t a) { return (uint32_t)vcvtpd_u32_f64(a); } - -// CHECK-LABEL: define {{[^@]+}}@test_vcvts_s32_f32 -// CHECK-SAME: (float noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VCVTS_S32_F32_I:%.*]] = call i32 @llvm.fptosi.sat.i32.f32(float [[A]]) -// CHECK-NEXT: ret i32 [[VCVTS_S32_F32_I]] -// -int32_t test_vcvts_s32_f32(float32_t a) { - return (int32_t)vcvts_s32_f32(a); -} - -// CHECK-LABEL: define {{[^@]+}}@test_vcvts_s64_f32 -// CHECK-SAME: (float noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VCVTS_S64_F32_I:%.*]] = call i64 @llvm.fptosi.sat.i64.f32(float [[A]]) -// CHECK-NEXT: ret i64 [[VCVTS_S64_F32_I]] -// -int64_t test_vcvts_s64_f32(float32_t a) { - return (int64_t)vcvts_s64_f32(a); -} - -// CHECK-LABEL: define {{[^@]+}}@test_vcvts_u32_f32 -// CHECK-SAME: (float noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VCVTS_U32_F32_I:%.*]] = call i32 @llvm.fptoui.sat.i32.f32(float [[A]]) -// CHECK-NEXT: ret i32 [[VCVTS_U32_F32_I]] -// -uint32_t test_vcvts_u32_f32(float32_t a) { - return (uint32_t)vcvts_u32_f32(a); -} - -// CHECK-LABEL: define {{[^@]+}}@test_vcvts_u64_f32 -// CHECK-SAME: (float noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VCVTS_U64_F32_I:%.*]] = call i64 @llvm.fptoui.sat.i64.f32(float [[A]]) -// CHECK-NEXT: ret i64 [[VCVTS_U64_F32_I]] -// -uint64_t test_vcvts_u64_f32(float32_t a) { - return (uint64_t)vcvts_u64_f32(a); -} - diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index 465d775926851..8bd34b3f052d2 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -4634,6 +4634,50 @@ uint64_t test_vcvtd_u64_f64(float64_t a) { return (uint64_t)vcvtd_u64_f64(a); } +// LLVM-LABEL: @test_vcvts_s32_f32 +// CIR-LABEL: @vcvts_s32_f32 +int32_t test_vcvts_s32_f32(float32_t a) { +// CIR: cir.call_llvm_intrinsic "fptosi.sat" + +// LLVM-SAME: float {{.*}} [[A:%.*]]) +// LLVM: [[VCVTS_S32_F32_I:%.*]] = call i32 @llvm.fptosi.sat.i32.f32(float [[A]]) +// LLVM: ret i32 [[VCVTS_S32_F32_I]] + return (int32_t)vcvts_s32_f32(a); +} + +// LLVM-LABEL: @test_vcvts_s64_f32 +// CIR-LABEL: @vcvts_s64_f32 +int64_t test_vcvts_s64_f32(float32_t a) { +// CIR: cir.call_llvm_intrinsic "fptosi.sat" + +// LLVM-SAME: float {{.*}} [[A:%.*]]) +// LLVM: [[VCVTS_S64_F32_I:%.*]] = call i64 @llvm.fptosi.sat.i64.f32(float [[A]]) +// LLVM: ret i64 [[VCVTS_S64_F32_I]] + return (int64_t)vcvts_s64_f32(a); +} + +// LLVM-LABEL: @test_vcvts_u32_f32 +// CIR-LABEL: @vcvts_u32_f32 +uint32_t test_vcvts_u32_f32(float32_t a) { +// CIR: cir.call_llvm_intrinsic "fptoui.sat + +// LLVM-SAME: float {{.*}} [[A:%.*]]) +// LLVM: [[VCVTS_U32_F32_I:%.*]] = call i32 @llvm.fptoui.sat.i32.f32(float [[A]]) +// LLVM: ret i32 [[VCVTS_U32_F32_I]] + return (uint32_t)vcvts_u32_f32(a); +} + +// LLVM-LABEL: @test_vcvts_u64_f32 +// CIR-LABEL: @vcvts_u64_f32 +uint64_t test_vcvts_u64_f32(float32_t a) { +// CIR: cir.call_llvm_intrinsic "fptoui.sat + +// LLVM-SAME: float {{.*}} [[A:%.*]]) +// LLVM: [[VCVTS_U64_F32_I:%.*]] = call i64 @llvm.fptoui.sat.i64.f32(float [[A]]) +// LLVM: ret i64 [[VCVTS_U64_F32_I]] + return (uint64_t)vcvts_u64_f32(a); +} + //===------------------------------------------------------===// // 2.1.3.2.3 Vector shift right and accumulate // https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-right-and-accumulate _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
