https://github.com/E00N777 created https://github.com/llvm/llvm-project/pull/217198
### summary part of : https://github.com/llvm/llvm-project/issues/185382 Lower all intrinsics in https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#set-vector-lane Assisted by : DeepSeek V4 Pro Max >From 2e4ac2835f3f7ba9074f7a0832641a1da5cebea3 Mon Sep 17 00:00:00 2001 From: E00N777 <[email protected]> Date: Wed, 19 Aug 2026 08:46:34 +0800 Subject: [PATCH] [CIR][AArch64] Lower NEON set vector lane intrinsics --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 10 +- .../CodeGen/AArch64/bf16-getset-intrinsics.c | 18 - .../fp8-intrinsics/acle_neon_fp8_untyped.c | 25 +- clang/test/CodeGen/AArch64/neon-vget.c | 195 ---------- clang/test/CodeGen/AArch64/neon/getset.c | 333 ++++++++++++++++++ clang/test/CodeGen/AArch64/poly64.c | 20 -- 6 files changed, 339 insertions(+), 262 deletions(-) delete mode 100644 clang/test/CodeGen/AArch64/neon-vget.c diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index 9a50acece4d2c..7cb7e809c0759 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -2543,6 +2543,10 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, } case NEON::BI__builtin_neon_vtstd_s64: case NEON::BI__builtin_neon_vtstd_u64: + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AArch64 builtin call: ") + + getContext().BuiltinInfo.getName(builtinID)); + return mlir::Value{}; case NEON::BI__builtin_neon_vset_lane_i8: case NEON::BI__builtin_neon_vset_lane_i16: case NEON::BI__builtin_neon_vset_lane_i32: @@ -2559,11 +2563,7 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, case NEON::BI__builtin_neon_vset_lane_mf8: case NEON::BI__builtin_neon_vsetq_lane_mf8: case NEON::BI__builtin_neon_vsetq_lane_f64: - cgm.errorNYI(expr->getSourceRange(), - std::string("unimplemented AArch64 builtin call: ") + - getContext().BuiltinInfo.getName(builtinID)); - return mlir::Value{}; - + return cir::VecInsertOp::create(builder, loc, ops[1], ops[0], ops[2]); case NEON::BI__builtin_neon_vget_lane_i8: case NEON::BI__builtin_neon_vdupb_lane_i8: case NEON::BI__builtin_neon_vgetq_lane_i8: diff --git a/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c b/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c index a0ea29cff0a08..2367e1698bc5d 100644 --- a/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c +++ b/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c @@ -22,21 +22,3 @@ bfloat16x4_t test_vcreate_bf16(uint64_t a) { bfloat16x8_t test_vcombine_bf16(bfloat16x4_t low, bfloat16x4_t high) { return vcombine_bf16(low, high); } - -// CHECK-LABEL: @test_vset_lane_bf16( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VSET_LANE:%.*]] = insertelement <4 x bfloat> [[V:%.*]], bfloat [[A:%.*]], i32 1 -// CHECK-NEXT: ret <4 x bfloat> [[VSET_LANE]] -// -bfloat16x4_t test_vset_lane_bf16(bfloat16_t a, bfloat16x4_t v) { - return vset_lane_bf16(a, v, 1); -} - -// CHECK-LABEL: @test_vsetq_lane_bf16( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VSET_LANE:%.*]] = insertelement <8 x bfloat> [[V:%.*]], bfloat [[A:%.*]], i32 7 -// CHECK-NEXT: ret <8 x bfloat> [[VSET_LANE]] -// -bfloat16x8_t test_vsetq_lane_bf16(bfloat16_t a, bfloat16x8_t v) { - return vsetq_lane_bf16(a, v, 7); -} diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c index 3842c7a7f2bc8..35782fdbe4ffe 100644 --- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c +++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c @@ -5,31 +5,8 @@ // REQUIRES: aarch64-registered-target -// CHECK-LABEL: define dso_local <8 x i8> @test_vset_lane_mf8( -// CHECK-SAME: <1 x i8> [[A:%.*]], <8 x i8> [[B:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i8> [[A]] to i8 -// CHECK-NEXT: [[VSET_LANE:%.*]] = insertelement <8 x i8> [[B]], i8 [[TMP0]], i32 7 -// CHECK-NEXT: ret <8 x i8> [[VSET_LANE]] -// -mfloat8x8_t test_vset_lane_mf8(mfloat8_t a, mfloat8x8_t b) { - return vset_lane_mf8(a, b, 7); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vsetq_lane_mf8( -// CHECK-SAME: <1 x i8> [[A:%.*]], <16 x i8> [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i8> [[A]] to i8 -// CHECK-NEXT: [[VSET_LANE:%.*]] = insertelement <16 x i8> [[B]], i8 [[TMP0]], i32 15 -// CHECK-NEXT: ret <16 x i8> [[VSET_LANE]] -// -mfloat8x16_t test_vsetq_lane_mf8(mfloat8_t a, mfloat8x16_t b) { - return vsetq_lane_mf8(a, b, 15); -} - - // CHECK-LABEL: define dso_local <8 x i8> @test_vcreate_mf8( -// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-SAME: i64 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A]] to <8 x i8> // CHECK-NEXT: ret <8 x i8> [[TMP0]] diff --git a/clang/test/CodeGen/AArch64/neon-vget.c b/clang/test/CodeGen/AArch64/neon-vget.c deleted file mode 100644 index 9d5c5e61a2dcd..0000000000000 --- a/clang/test/CodeGen/AArch64/neon-vget.c +++ /dev/null @@ -1,195 +0,0 @@ -// RUN: %clang_cc1 -triple arm64-apple-darwin -target-feature +neon -flax-vector-conversions=none \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s \ -// RUN: | opt -S -passes=mem2reg | FileCheck %s - -// REQUIRES: aarch64-registered-target || arm-registered-target - -#include <arm_neon.h> - -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_u8(i8 noundef %a, <8 x i8> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i8> %b, i8 %a, i32 7 -// CHECK: ret <8 x i8> [[VSET_LANE]] -uint8x8_t test_vset_lane_u8(uint8_t a, uint8x8_t b) { - return vset_lane_u8(a, b, 7); -} - -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vset_lane_u16(i16 noundef %a, <4 x i16> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i16> %b, i16 %a, i32 3 -// CHECK: ret <4 x i16> [[VSET_LANE]] -uint16x4_t test_vset_lane_u16(uint16_t a, uint16x4_t b) { - return vset_lane_u16(a, b, 3); -} - -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vset_lane_u32(i32 noundef %a, <2 x i32> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i32> %b, i32 %a, i32 1 -// CHECK: ret <2 x i32> [[VSET_LANE]] -uint32x2_t test_vset_lane_u32(uint32_t a, uint32x2_t b) { - return vset_lane_u32(a, b, 1); -} - -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_s8(i8 noundef %a, <8 x i8> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i8> %b, i8 %a, i32 7 -// CHECK: ret <8 x i8> [[VSET_LANE]] -int8x8_t test_vset_lane_s8(int8_t a, int8x8_t b) { - return vset_lane_s8(a, b, 7); -} - -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vset_lane_s16(i16 noundef %a, <4 x i16> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i16> %b, i16 %a, i32 3 -// CHECK: ret <4 x i16> [[VSET_LANE]] -int16x4_t test_vset_lane_s16(int16_t a, int16x4_t b) { - return vset_lane_s16(a, b, 3); -} - -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vset_lane_s32(i32 noundef %a, <2 x i32> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i32> %b, i32 %a, i32 1 -// CHECK: ret <2 x i32> [[VSET_LANE]] -int32x2_t test_vset_lane_s32(int32_t a, int32x2_t b) { - return vset_lane_s32(a, b, 1); -} - -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_p8(i8 noundef %a, <8 x i8> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i8> %b, i8 %a, i32 7 -// CHECK: ret <8 x i8> [[VSET_LANE]] -poly8x8_t test_vset_lane_p8(poly8_t a, poly8x8_t b) { - return vset_lane_p8(a, b, 7); -} - -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vset_lane_p16(i16 noundef %a, <4 x i16> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i16> %b, i16 %a, i32 3 -// CHECK: ret <4 x i16> [[VSET_LANE]] -poly16x4_t test_vset_lane_p16(poly16_t a, poly16x4_t b) { - return vset_lane_p16(a, b, 3); -} - -// CHECK-LABEL: define{{.*}} <2 x float> @test_vset_lane_f32(float noundef %a, <2 x float> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x float> %b, float %a, i32 1 -// CHECK: ret <2 x float> [[VSET_LANE]] -float32x2_t test_vset_lane_f32(float32_t a, float32x2_t b) { - return vset_lane_f32(a, b, 1); -} - -// CHECK-LABEL: define{{.*}} <4 x half> @test_vset_lane_f16(ptr noundef %a, <4 x half> noundef %b) #0 { -// CHECK: [[__REINT_246:%.*]] = alloca half, align 2 -// CHECK: [[__REINT1_246:%.*]] = alloca <4 x half>, align 8 -// CHECK: [[__REINT2_246:%.*]] = alloca <4 x i16>, align 8 -// CHECK: [[TMP0:%.*]] = load half, ptr %a, align 2 -// CHECK: store half [[TMP0]], ptr [[__REINT_246]], align 2 -// CHECK: store <4 x half> %b, ptr [[__REINT1_246]], align 8 -// CHECK: [[TMP2:%.*]] = load i16, ptr [[__REINT_246]], align 2 -// CHECK: [[TMP4:%.*]] = load <4 x i16>, ptr [[__REINT1_246]], align 8 -// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i16> [[TMP4]], i16 [[TMP2]], i32 3 -// CHECK: store <4 x i16> [[VSET_LANE]], ptr [[__REINT2_246]], align 8 -// CHECK: [[TMP8:%.*]] = load <4 x half>, ptr [[__REINT2_246]], align 8 -// CHECK: ret <4 x half> [[TMP8]] -float16x4_t test_vset_lane_f16(float16_t *a, float16x4_t b) { - return vset_lane_f16(*a, b, 3); -} - -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsetq_lane_u8(i8 noundef %a, <16 x i8> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <16 x i8> %b, i8 %a, i32 15 -// CHECK: ret <16 x i8> [[VSET_LANE]] -uint8x16_t test_vsetq_lane_u8(uint8_t a, uint8x16_t b) { - return vsetq_lane_u8(a, b, 15); -} - -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vsetq_lane_u16(i16 noundef %a, <8 x i16> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> %b, i16 %a, i32 7 -// CHECK: ret <8 x i16> [[VSET_LANE]] -uint16x8_t test_vsetq_lane_u16(uint16_t a, uint16x8_t b) { - return vsetq_lane_u16(a, b, 7); -} - -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vsetq_lane_u32(i32 noundef %a, <4 x i32> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i32> %b, i32 %a, i32 3 -// CHECK: ret <4 x i32> [[VSET_LANE]] -uint32x4_t test_vsetq_lane_u32(uint32_t a, uint32x4_t b) { - return vsetq_lane_u32(a, b, 3); -} - -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsetq_lane_s8(i8 noundef %a, <16 x i8> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <16 x i8> %b, i8 %a, i32 15 -// CHECK: ret <16 x i8> [[VSET_LANE]] -int8x16_t test_vsetq_lane_s8(int8_t a, int8x16_t b) { - return vsetq_lane_s8(a, b, 15); -} - -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vsetq_lane_s16(i16 noundef %a, <8 x i16> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> %b, i16 %a, i32 7 -// CHECK: ret <8 x i16> [[VSET_LANE]] -int16x8_t test_vsetq_lane_s16(int16_t a, int16x8_t b) { - return vsetq_lane_s16(a, b, 7); -} - -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vsetq_lane_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i32> %b, i32 %a, i32 3 -// CHECK: ret <4 x i32> [[VSET_LANE]] -int32x4_t test_vsetq_lane_s32(int32_t a, int32x4_t b) { - return vsetq_lane_s32(a, b, 3); -} - -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsetq_lane_p8(i8 noundef %a, <16 x i8> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <16 x i8> %b, i8 %a, i32 15 -// CHECK: ret <16 x i8> [[VSET_LANE]] -poly8x16_t test_vsetq_lane_p8(poly8_t a, poly8x16_t b) { - return vsetq_lane_p8(a, b, 15); -} - -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vsetq_lane_p16(i16 noundef %a, <8 x i16> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> %b, i16 %a, i32 7 -// CHECK: ret <8 x i16> [[VSET_LANE]] -poly16x8_t test_vsetq_lane_p16(poly16_t a, poly16x8_t b) { - return vsetq_lane_p16(a, b, 7); -} - -// CHECK-LABEL: define{{.*}} <4 x float> @test_vsetq_lane_f32(float noundef %a, <4 x float> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x float> %b, float %a, i32 3 -// CHECK: ret <4 x float> [[VSET_LANE]] -float32x4_t test_vsetq_lane_f32(float32_t a, float32x4_t b) { - return vsetq_lane_f32(a, b, 3); -} - -// CHECK-LABEL: define{{.*}} <8 x half> @test_vsetq_lane_f16(ptr noundef %a, <8 x half> noundef %b) #0 { -// CHECK: [[__REINT_248:%.*]] = alloca half, align 2 -// CHECK: [[__REINT1_248:%.*]] = alloca <8 x half>, align 16 -// CHECK: [[__REINT2_248:%.*]] = alloca <8 x i16>, align 16 -// CHECK: [[TMP0:%.*]] = load half, ptr %a, align 2 -// CHECK: store half [[TMP0]], ptr [[__REINT_248]], align 2 -// CHECK: store <8 x half> %b, ptr [[__REINT1_248]], align 16 -// CHECK: [[TMP2:%.*]] = load i16, ptr [[__REINT_248]], align 2 -// CHECK: [[TMP4:%.*]] = load <8 x i16>, ptr [[__REINT1_248]], align 16 -// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> [[TMP4]], i16 [[TMP2]], i32 7 -// CHECK: store <8 x i16> [[VSET_LANE]], ptr [[__REINT2_248]], align 16 -// CHECK: [[TMP8:%.*]] = load <8 x half>, ptr [[__REINT2_248]], align 16 -// CHECK: ret <8 x half> [[TMP8]] -float16x8_t test_vsetq_lane_f16(float16_t *a, float16x8_t b) { - return vsetq_lane_f16(*a, b, 7); -} - -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vset_lane_s64(i64 noundef %a, <1 x i64> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <1 x i64> %b, i64 %a, i32 0 -// CHECK: ret <1 x i64> [[VSET_LANE]] -int64x1_t test_vset_lane_s64(int64_t a, int64x1_t b) { - return vset_lane_s64(a, b, 0); -} - -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vset_lane_u64(i64 noundef %a, <1 x i64> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <1 x i64> %b, i64 %a, i32 0 -// CHECK: ret <1 x i64> [[VSET_LANE]] -uint64x1_t test_vset_lane_u64(uint64_t a, uint64x1_t b) { - return vset_lane_u64(a, b, 0); -} - -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsetq_lane_s64(i64 noundef %a, <2 x i64> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i64> %b, i64 %a, i32 1 -// CHECK: ret <2 x i64> [[VSET_LANE]] -int64x2_t test_vsetq_lane_s64(int64_t a, int64x2_t b) { - return vsetq_lane_s64(a, b, 1); -} - -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsetq_lane_u64(i64 noundef %a, <2 x i64> noundef %b) #0 { -// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i64> %b, i64 %a, i32 1 -// CHECK: ret <2 x i64> [[VSET_LANE]] -uint64x2_t test_vsetq_lane_u64(uint64_t a, uint64x2_t b) { - return vsetq_lane_u64(a, b, 1); -} diff --git a/clang/test/CodeGen/AArch64/neon/getset.c b/clang/test/CodeGen/AArch64/neon/getset.c index 6368de7665f26..e0c645b83458e 100644 --- a/clang/test/CodeGen/AArch64/neon/getset.c +++ b/clang/test/CodeGen/AArch64/neon/getset.c @@ -11,6 +11,8 @@ // * clang/test/CodeGen/AArch64/neon-vget.c // * clang/test/CodeGen/AArch64/neon-scalar-copy.c // * clang/test/CodeGen/AArch64/poly64.c +// * clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c +// * clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c // The main difference is the use of RUN lines that enable ClangIR lowering; // therefore only builtins currently supported by ClangIR are tested here. //============================================================================= @@ -590,3 +592,334 @@ mfloat8_t test_vdupb_laneq_mf8(mfloat8x16_t a) { // LLVM: [[VDUPQ_LANE:%.*]] = extractelement <16 x i8> [[A]], i32 15 return vdupb_laneq_mf8(a, 15); } + +//===------------------------------------------------------===// +// 2.1.9.13 Set vector lane +// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#set-vector-lane +//===------------------------------------------------------===// + +// ALL-LABEL: @test_vset_lane_s8( +int8x8_t test_vset_lane_s8(int8_t a, int8x8_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s8i> + +// LLVM-SAME: i8 {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <8 x i8> [[B]], i8 [[A]], i32 7 +// LLVM: ret <8 x i8> [[VSET_LANE]] + return vset_lane_s8(a, b, 7); +} + +// ALL-LABEL: @test_vset_lane_s16( +int16x4_t test_vset_lane_s16(int16_t a, int16x4_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s16i> + +// LLVM-SAME: i16 {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <4 x i16> [[B]], i16 [[A]], i32 3 +// LLVM: ret <4 x i16> [[VSET_LANE]] + return vset_lane_s16(a, b, 3); +} + +// ALL-LABEL: @test_vset_lane_s32( +int32x2_t test_vset_lane_s32(int32_t a, int32x2_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s32i> + +// LLVM-SAME: i32 {{.*}}[[A:%.*]], <2 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <2 x i32> [[B]], i32 [[A]], i32 1 +// LLVM: ret <2 x i32> [[VSET_LANE]] + return vset_lane_s32(a, b, 1); +} + +// ALL-LABEL: @test_vset_lane_s64( +int64x1_t test_vset_lane_s64(int64_t a, int64x1_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x !s64i> + +// LLVM-SAME: i64 {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <1 x i64> [[B]], i64 [[A]], i32 0 +// LLVM: ret <1 x i64> [[VSET_LANE]] + return vset_lane_s64(a, b, 0); +} + +// ALL-LABEL: @test_vset_lane_u8( +uint8x8_t test_vset_lane_u8(uint8_t a, uint8x8_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s8i> + +// LLVM-SAME: i8 {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <8 x i8> [[B]], i8 [[A]], i32 7 +// LLVM: ret <8 x i8> [[VSET_LANE]] + return vset_lane_u8(a, b, 7); +} + +// ALL-LABEL: @test_vset_lane_u16( +uint16x4_t test_vset_lane_u16(uint16_t a, uint16x4_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s16i> + +// LLVM-SAME: i16 {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <4 x i16> [[B]], i16 [[A]], i32 3 +// LLVM: ret <4 x i16> [[VSET_LANE]] + return vset_lane_u16(a, b, 3); +} + +// ALL-LABEL: @test_vset_lane_u32( +uint32x2_t test_vset_lane_u32(uint32_t a, uint32x2_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s32i> + +// LLVM-SAME: i32 {{.*}}[[A:%.*]], <2 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <2 x i32> [[B]], i32 [[A]], i32 1 +// LLVM: ret <2 x i32> [[VSET_LANE]] + return vset_lane_u32(a, b, 1); +} + +// ALL-LABEL: @test_vset_lane_p8( +poly8x8_t test_vset_lane_p8(poly8_t a, poly8x8_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s8i> + +// LLVM-SAME: i8 {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <8 x i8> [[B]], i8 [[A]], i32 7 +// LLVM: ret <8 x i8> [[VSET_LANE]] + return vset_lane_p8(a, b, 7); +} + +// ALL-LABEL: @test_vset_lane_p16( +poly16x4_t test_vset_lane_p16(poly16_t a, poly16x4_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s16i> + +// LLVM-SAME: i16 {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <4 x i16> [[B]], i16 [[A]], i32 3 +// LLVM: ret <4 x i16> [[VSET_LANE]] + return vset_lane_p16(a, b, 3); +} + +// ALL-LABEL: @test_vset_lane_u64( +uint64x1_t test_vset_lane_u64(uint64_t a, uint64x1_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x !s64i> + +// LLVM-SAME: i64 {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <1 x i64> [[B]], i64 [[A]], i32 0 +// LLVM: ret <1 x i64> [[VSET_LANE]] + return vset_lane_u64(a, b, 0); +} + +// ALL-LABEL: @test_vset_lane_p64( +poly64x1_t test_vset_lane_p64(poly64_t a, poly64x1_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x !s64i> + +// LLVM-SAME: i64 {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <1 x i64> [[B]], i64 [[A]], i32 0 +// LLVM: ret <1 x i64> [[VSET_LANE]] + return vset_lane_p64(a, b, 0); +} + +// ALL-LABEL: @test_vset_lane_f32( +float32x2_t test_vset_lane_f32(float32_t a, float32x2_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !cir.float> + +// LLVM-SAME: float {{.*}}[[A:%.*]], <2 x float> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <2 x float> [[B]], float [[A]], i32 1 +// LLVM: ret <2 x float> [[VSET_LANE]] + return vset_lane_f32(a, b, 1); +} + +// ALL-LABEL: @test_vset_lane_f64( +float64x1_t test_vset_lane_f64(float64_t a, float64x1_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x !cir.double> + +// LLVM-SAME: double {{.*}}[[A:%.*]], <1 x double> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <1 x double> [[B]], double [[A]], i32 0 +// LLVM: ret <1 x double> [[VSET_LANE]] + return vset_lane_f64(a, b, 0); +} + +// ALL-LABEL: @test_vset_lane_f16( +float16x4_t test_vset_lane_f16(float16_t a, float16x4_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s16i> + +// LLVM-SAME: half {{.*}}[[A:%.*]], <4 x half> {{.*}}[[B:%.*]]) +// LLVM: [[BITCAST_B:%.*]] = bitcast <4 x half> [[B]] to <4 x i16> +// LLVM: [[BITCAST_A:%.*]] = bitcast half [[A]] to i16 +// LLVM: [[VSET_LANE:%.*]] = insertelement <4 x i16> [[BITCAST_B]], i16 [[BITCAST_A]], i32 3 +// LLVM: [[BITCAST_RES:%.*]] = bitcast <4 x i16> [[VSET_LANE]] to <4 x half> +// LLVM: ret <4 x half> [[BITCAST_RES]] + return vset_lane_f16(a, b, 3); +} + +// ALL-LABEL: @test_vset_lane_bf16( +bfloat16x4_t test_vset_lane_bf16(bfloat16_t a, bfloat16x4_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !cir.bf16> + +// LLVM-SAME: bfloat {{.*}}[[A:%.*]], <4 x bfloat> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <4 x bfloat> [[B]], bfloat [[A]], i32 1 +// LLVM: ret <4 x bfloat> [[VSET_LANE]] + return vset_lane_bf16(a, b, 1); +} + +// ALL-LABEL: @test_vset_lane_mf8( +mfloat8x8_t test_vset_lane_mf8(mfloat8_t a, mfloat8x8_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !u8i> + +// LLVM-SAME: {{.*}}<8 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <8 x i8> [[B]], i8 {{.*}}, i32 7 +// LLVM: ret <8 x i8> [[VSET_LANE]] + return vset_lane_mf8(a, b, 7); +} + +// ALL-LABEL: @test_vsetq_lane_s8( +int8x16_t test_vsetq_lane_s8(int8_t a, int8x16_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x !s8i> + +// LLVM-SAME: i8 {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <16 x i8> [[B]], i8 [[A]], i32 15 +// LLVM: ret <16 x i8> [[VSET_LANE]] + return vsetq_lane_s8(a, b, 15); +} + +// ALL-LABEL: @test_vsetq_lane_s16( +int16x8_t test_vsetq_lane_s16(int16_t a, int16x8_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s16i> + +// LLVM-SAME: i16 {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <8 x i16> [[B]], i16 [[A]], i32 7 +// LLVM: ret <8 x i16> [[VSET_LANE]] + return vsetq_lane_s16(a, b, 7); +} + +// ALL-LABEL: @test_vsetq_lane_s32( +int32x4_t test_vsetq_lane_s32(int32_t a, int32x4_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s32i> + +// LLVM-SAME: i32 {{.*}}[[A:%.*]], <4 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <4 x i32> [[B]], i32 [[A]], i32 3 +// LLVM: ret <4 x i32> [[VSET_LANE]] + return vsetq_lane_s32(a, b, 3); +} + +// ALL-LABEL: @test_vsetq_lane_s64( +int64x2_t test_vsetq_lane_s64(int64_t a, int64x2_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s64i> + +// LLVM-SAME: i64 {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <2 x i64> [[B]], i64 [[A]], i32 1 +// LLVM: ret <2 x i64> [[VSET_LANE]] + return vsetq_lane_s64(a, b, 1); +} + +// ALL-LABEL: @test_vsetq_lane_u8( +uint8x16_t test_vsetq_lane_u8(uint8_t a, uint8x16_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x !s8i> + +// LLVM-SAME: i8 {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <16 x i8> [[B]], i8 [[A]], i32 15 +// LLVM: ret <16 x i8> [[VSET_LANE]] + return vsetq_lane_u8(a, b, 15); +} + +// ALL-LABEL: @test_vsetq_lane_u16( +uint16x8_t test_vsetq_lane_u16(uint16_t a, uint16x8_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s16i> + +// LLVM-SAME: i16 {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <8 x i16> [[B]], i16 [[A]], i32 7 +// LLVM: ret <8 x i16> [[VSET_LANE]] + return vsetq_lane_u16(a, b, 7); +} + +// ALL-LABEL: @test_vsetq_lane_u32( +uint32x4_t test_vsetq_lane_u32(uint32_t a, uint32x4_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s32i> + +// LLVM-SAME: i32 {{.*}}[[A:%.*]], <4 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <4 x i32> [[B]], i32 [[A]], i32 3 +// LLVM: ret <4 x i32> [[VSET_LANE]] + return vsetq_lane_u32(a, b, 3); +} + +// ALL-LABEL: @test_vsetq_lane_p8( +poly8x16_t test_vsetq_lane_p8(poly8_t a, poly8x16_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x !s8i> + +// LLVM-SAME: i8 {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <16 x i8> [[B]], i8 [[A]], i32 15 +// LLVM: ret <16 x i8> [[VSET_LANE]] + return vsetq_lane_p8(a, b, 15); +} + +// ALL-LABEL: @test_vsetq_lane_p16( +poly16x8_t test_vsetq_lane_p16(poly16_t a, poly16x8_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s16i> + +// LLVM-SAME: i16 {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <8 x i16> [[B]], i16 [[A]], i32 7 +// LLVM: ret <8 x i16> [[VSET_LANE]] + return vsetq_lane_p16(a, b, 7); +} + +// ALL-LABEL: @test_vsetq_lane_u64( +uint64x2_t test_vsetq_lane_u64(uint64_t a, uint64x2_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s64i> + +// LLVM-SAME: i64 {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <2 x i64> [[B]], i64 [[A]], i32 1 +// LLVM: ret <2 x i64> [[VSET_LANE]] + return vsetq_lane_u64(a, b, 1); +} + +// ALL-LABEL: @test_vsetq_lane_p64( +poly64x2_t test_vsetq_lane_p64(poly64_t a, poly64x2_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s64i> + +// LLVM-SAME: i64 {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <2 x i64> [[B]], i64 [[A]], i32 1 +// LLVM: ret <2 x i64> [[VSET_LANE]] + return vsetq_lane_p64(a, b, 1); +} + +// ALL-LABEL: @test_vsetq_lane_f32( +float32x4_t test_vsetq_lane_f32(float32_t a, float32x4_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !cir.float> + +// LLVM-SAME: float {{.*}}[[A:%.*]], <4 x float> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <4 x float> [[B]], float [[A]], i32 3 +// LLVM: ret <4 x float> [[VSET_LANE]] + return vsetq_lane_f32(a, b, 3); +} + +// ALL-LABEL: @test_vsetq_lane_f64( +float64x2_t test_vsetq_lane_f64(float64_t a, float64x2_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !cir.double> + +// LLVM-SAME: double {{.*}}[[A:%.*]], <2 x double> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <2 x double> [[B]], double [[A]], i32 1 +// LLVM: ret <2 x double> [[VSET_LANE]] + return vsetq_lane_f64(a, b, 1); +} + +// ALL-LABEL: @test_vsetq_lane_f16( +float16x8_t test_vsetq_lane_f16(float16_t a, float16x8_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s16i> + +// LLVM-SAME: half {{.*}}[[A:%.*]], <8 x half> {{.*}}[[B:%.*]]) +// LLVM: [[BITCAST_B:%.*]] = bitcast <8 x half> [[B]] to <8 x i16> +// LLVM: [[BITCAST_A:%.*]] = bitcast half [[A]] to i16 +// LLVM: [[VSET_LANE:%.*]] = insertelement <8 x i16> [[BITCAST_B]], i16 [[BITCAST_A]], i32 7 +// LLVM: [[BITCAST_RES:%.*]] = bitcast <8 x i16> [[VSET_LANE]] to <8 x half> +// LLVM: ret <8 x half> [[BITCAST_RES]] + return vsetq_lane_f16(a, b, 7); +} + +// ALL-LABEL: @test_vsetq_lane_bf16( +bfloat16x8_t test_vsetq_lane_bf16(bfloat16_t a, bfloat16x8_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !cir.bf16> + +// LLVM-SAME: bfloat {{.*}}[[A:%.*]], <8 x bfloat> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <8 x bfloat> [[B]], bfloat [[A]], i32 7 +// LLVM: ret <8 x bfloat> [[VSET_LANE]] + return vsetq_lane_bf16(a, b, 7); +} + +// ALL-LABEL: @test_vsetq_lane_mf8( +mfloat8x16_t test_vsetq_lane_mf8(mfloat8_t a, mfloat8x16_t b) { +// CIR: cir.vec.insert %{{.*}}, %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x !u8i> + +// LLVM-SAME: {{.*}}<16 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[VSET_LANE:%.*]] = insertelement <16 x i8> [[B]], i8 {{.*}}, i32 15 +// LLVM: ret <16 x i8> [[VSET_LANE]] + return vsetq_lane_mf8(a, b, 15); +} diff --git a/clang/test/CodeGen/AArch64/poly64.c b/clang/test/CodeGen/AArch64/poly64.c index 36409a97d32f1..aa2459afd4289 100644 --- a/clang/test/CodeGen/AArch64/poly64.c +++ b/clang/test/CodeGen/AArch64/poly64.c @@ -61,26 +61,6 @@ uint64x2_t test_vtstq_p64(poly64x2_t a, poly64x2_t b) { return vtstq_p64(a, b); } -// CHECK-LABEL: define dso_local <1 x i64> @test_vset_lane_p64( -// CHECK-SAME: i64 noundef [[A:%.*]], <1 x i64> noundef [[V:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSET_LANE:%.*]] = insertelement <1 x i64> [[V]], i64 [[A]], i32 0 -// CHECK-NEXT: ret <1 x i64> [[VSET_LANE]] -// -poly64x1_t test_vset_lane_p64(poly64_t a, poly64x1_t v) { - return vset_lane_p64(a, v, 0); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vsetq_lane_p64( -// CHECK-SAME: i64 noundef [[A:%.*]], <2 x i64> noundef [[V:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSET_LANE:%.*]] = insertelement <2 x i64> [[V]], i64 [[A]], i32 1 -// CHECK-NEXT: ret <2 x i64> [[VSET_LANE]] -// -poly64x2_t test_vsetq_lane_p64(poly64_t a, poly64x2_t v) { - return vsetq_lane_p64(a, v, 1); -} - // CHECK-LABEL: define dso_local <1 x i64> @test_vcopy_lane_p64( // CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
