https://github.com/AmrDeveloper updated https://github.com/llvm/llvm-project/pull/217012
>From a5098a9eb23b9f995f3292e23c6bb11bd293e7b6 Mon Sep 17 00:00:00 2001 From: Amr Hesham <[email protected]> Date: Tue, 18 Aug 2026 13:55:17 +0200 Subject: [PATCH] [CIR] Support vector of boolean in cir.not op --- .../CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp | 15 +++++++++++++-- clang/test/CIR/CodeGen/vector-bool.cpp | 19 +++++++++++++++++++ 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp index 28d265f70616d..578b328b622ee 100644 --- a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp +++ b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp @@ -3243,7 +3243,7 @@ mlir::LogicalResult CIRToLLVMNotOpLowering::matchAndRewrite( mlir::Value minusOne; if (isVector) { const uint64_t numElements = - mlir::dyn_cast<cir::VectorType>(op.getType()).getSize(); + mlir::cast<cir::VectorType>(op.getType()).getSize(); SmallVector<int32_t> values(numElements, -1); mlir::DenseIntElementsAttr denseVec = rewriter.getI32VectorAttr(values); minusOne = @@ -3255,11 +3255,22 @@ mlir::LogicalResult CIRToLLVMNotOpLowering::matchAndRewrite( minusOne); return mlir::success(); } + if (mlir::isa<cir::BoolType>(elementType)) { - auto one = mlir::LLVM::ConstantOp::create(rewriter, loc, llvmType, 1); + mlir::Value one; + if (isVector) { + const uint64_t numElements = + mlir::cast<cir::VectorType>(op.getType()).getSize(); + SmallVector<bool> values(numElements, true); + mlir::DenseIntElementsAttr denseVec = rewriter.getBoolVectorAttr(values); + one = mlir::LLVM::ConstantOp::create(rewriter, loc, llvmType, denseVec); + } else { + one = mlir::LLVM::ConstantOp::create(rewriter, loc, llvmType, 1); + } rewriter.replaceOpWithNewOp<mlir::LLVM::XOrOp>(op, adaptor.getInput(), one); return mlir::success(); } + return op.emitError() << "Unsupported type for bitwise NOT"; } diff --git a/clang/test/CIR/CodeGen/vector-bool.cpp b/clang/test/CIR/CodeGen/vector-bool.cpp index 4e6f95902b81e..d2294e6dc383e 100644 --- a/clang/test/CIR/CodeGen/vector-bool.cpp +++ b/clang/test/CIR/CodeGen/vector-bool.cpp @@ -233,3 +233,22 @@ void vec_bool_bitwise_operators() { // SHARED: %[[XOR:.*]] = xor <8 x i1> %[[TMP_A_VEC]], %[[TMP_B_VEC]] // SHARED: %[[XOR_I8:.*]] = bitcast <8 x i1> %[[XOR]] to i8 // SHARED: store i8 %[[XOR_I8]], ptr %[[XOR_ADDR]], align 1 + +void vec_bool_not_op() { + v8b a; + v8b b = ~a; +} + +// CIR: %[[A_ADDR:.*]] = cir.alloca "a" {{.*}} : !cir.ptr<!cir.vector<8 x !cir.bool>> +// CIR: %[[B_ADDR:.*]] = cir.alloca "b" {{.*}} init : !cir.ptr<!cir.vector<8 x !cir.bool>> +// CIR: %[[TMP_A:.*]] = cir.load {{.*}} %[[A_ADDR]] : !cir.ptr<!cir.vector<8 x !cir.bool>>, !cir.vector<8 x !cir.bool> +// CIR: %[[RESULT:.*]] = cir.not %[[TMP_A]] : !cir.vector<8 x !cir.bool> +// CIR: cir.store {{.*}} %[[RESULT]], %[[B_ADDR]] : !cir.vector<8 x !cir.bool>, !cir.ptr<!cir.vector<8 x !cir.bool>> + +// SHARED: %[[A_ADDR:.*]] = alloca i8, align 1 +// SHARED: %[[B_ADDR:.*]] = alloca i8, align 1 +// SHARED: %[[TMP_A:.*]] = load i8, ptr %[[A_ADDR]], align 1 +// SHARED: %[[TMP_A_VEC:.*]] = bitcast i8 %[[TMP_A:.*]] to <8 x i1> +// SHARED: %[[RESULT:.*]] = xor <8 x i1> %[[TMP_A_VEC]], splat (i1 true) +// SHARED: %[[RESULT_I8:.*]] = bitcast <8 x i1> %[[RESULT]] to i8 +// SHARED: store i8 %[[RESULT_I8]], ptr %[[B_ADDR]], align 1 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
