Author: Chirag Patel Date: 2026-08-19T12:47:47Z New Revision: 98205aa1932e475704a4e0da76ce013c3fcc34bd
URL: https://github.com/llvm/llvm-project/commit/98205aa1932e475704a4e0da76ce013c3fcc34bd DIFF: https://github.com/llvm/llvm-project/commit/98205aa1932e475704a4e0da76ce013c3fcc34bd.diff LOG: [X86][Clang] VectorExprEvaluator::VisitCallExpr / InterpretBuiltin - allow SSE/AVX FP2INT conversion intrinsics to be used in constexpr (#214611) Adds constexpr support for below builtins, _mm_cvtss_si32 _mm_cvt_ss2si _mm_cvtss_si64 _mm_cvtps_pi32 _mm_cvt_ps2pi _mm_cvttss_si32 _mm_cvtt_ss2si _mm_cvttss_si64 _mm_cvttps_pi32 _mm_cvtt_ps2pi _mm_cvtps_pi16 _mm_cvtps_pi8 _mm_cvtpd_epi32 _mm_cvtsd_si32 _mm_cvttpd_epi32 _mm_cvttsd_si32 _mm_cvtpd_pi32 _mm_cvttpd_pi32 _mm_cvtsd_si64 _mm_cvttsd_si64 _mm_cvtps_epi32 _mm_cvttps_epi32 _mm256_cvtpd_epi32 _mm256_cvttpd_epi32 _mm256_cvtps_epi32 _mm256_cvttps_epi32 Assisted by Gemini. P.S. the current implementation only allows EXACT/INBOUNDS and FINITE conversions - any special case (DENORMAL/INF/NAN/etc.) or loss of precision aren't allowed in constexpr for now as per request in issue. Fixes #169374 Added: Modified: clang/include/clang/Basic/BuiltinsX86.td clang/include/clang/Basic/BuiltinsX86_64.td clang/lib/AST/ByteCode/InterpBuiltin.cpp clang/lib/AST/ExprConstant.cpp clang/lib/Headers/avxintrin.h clang/lib/Headers/emmintrin.h clang/lib/Headers/xmmintrin.h clang/test/CodeGen/X86/avx-builtins.c clang/test/CodeGen/X86/mmx-builtins.c clang/test/CodeGen/X86/sse-builtins.c clang/test/CodeGen/X86/sse2-builtins.c Removed: ################################################################################ diff --git a/clang/include/clang/Basic/BuiltinsX86.td b/clang/include/clang/Basic/BuiltinsX86.td index 9b7abefb75049..04f93db3aa0b0 100644 --- a/clang/include/clang/Basic/BuiltinsX86.td +++ b/clang/include/clang/Basic/BuiltinsX86.td @@ -129,7 +129,7 @@ let Features = "sse", Header = "xmmintrin.h", Attributes = [NoThrow, RequireDecl def _mm_getcsr : X86LibBuiltin<"unsigned int()">; } -let Features = "sse", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "sse", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<128>] in { def cvtss2si : X86Builtin<"int(_Vector<4, float>)">; def cvttss2si : X86Builtin<"int(_Vector<4, float>)">; } @@ -179,7 +179,7 @@ let Features = "avx512f", Attributes = [NoThrow, Const, Constexpr, RequiredVecto def cvtsd2ss_round_mask : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<2, double>, _Vector<4, float>, unsigned char, _Constant int)">; } -let Features = "sse2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "sse2", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<128>] in { def cvtpd2dq : X86Builtin<"_Vector<4, int>(_Vector<2, double>)">; def cvttpd2dq : X86Builtin<"_Vector<4, int>(_Vector<2, double>)">; def cvtsd2si : X86Builtin<"int(_Vector<2, double>)">; @@ -475,6 +475,9 @@ let Features = "avx", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in def dpps256 : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Vector<8, float>, _Constant char)">; def cmppd256 : X86Builtin<"_Vector<4, double>(_Vector<4, double>, _Vector<4, double>, _Constant char)">; def cmpps256 : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Vector<8, float>, _Constant char)">; +} + +let Features = "avx", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<256>] in { def cvtps2dq256 : X86Builtin<"_Vector<8, int>(_Vector<8, float>)">; def cvttpd2dq256 : X86Builtin<"_Vector<4, int>(_Vector<4, double>)">; def cvtpd2dq256 : X86Builtin<"_Vector<4, int>(_Vector<4, double>)">; diff --git a/clang/include/clang/Basic/BuiltinsX86_64.td b/clang/include/clang/Basic/BuiltinsX86_64.td index 0a98b3049df34..cf76d9a257614 100644 --- a/clang/include/clang/Basic/BuiltinsX86_64.td +++ b/clang/include/clang/Basic/BuiltinsX86_64.td @@ -42,12 +42,12 @@ let Attributes = [NoThrow] in { def writeeflags_u64 : X86Builtin<"void(unsigned long long int)">; } -let Features = "sse", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "sse", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<128>] in { def cvtss2si64 : X86Builtin<"long long int(_Vector<4, float>)">; def cvttss2si64 : X86Builtin<"long long int(_Vector<4, float>)">; } -let Features = "sse2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "sse2", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<128>] in { def cvtsd2si64 : X86Builtin<"long long int(_Vector<2, double>)">; def cvttsd2si64 : X86Builtin<"long long int(_Vector<2, double>)">; } diff --git a/clang/lib/AST/ByteCode/InterpBuiltin.cpp b/clang/lib/AST/ByteCode/InterpBuiltin.cpp index 54b2b4bb1b16d..17a0983059bc7 100644 --- a/clang/lib/AST/ByteCode/InterpBuiltin.cpp +++ b/clang/lib/AST/ByteCode/InterpBuiltin.cpp @@ -4671,6 +4671,67 @@ static bool interp__builtin_ia32_bmac(InterpState &S, CodePtr OpPC, return true; } +static bool interp_builtin_ia32_cvt_scalar_to_int(InterpState &S, CodePtr OpPC, + const CallExpr *E) { + Pointer SrcVecPtr = S.Stk.pop<Pointer>(); + const Floating &FloatElem = SrcVecPtr.elem<Floating>(0); + + unsigned BitWidth = S.getASTContext().getIntWidth(E->getType()); + bool IsUnsigned = E->getType()->isUnsignedIntegerType(); + + llvm::APSInt IntResult(BitWidth, IsUnsigned); + bool IsExact = false; + // We only allow exact conversions so rounding mode does not matter for cvt* + // and cvtt* builtins + FloatElem.getAPFloat().convertToInteger( + IntResult, llvm::APFloat::rmTowardZero, &IsExact); + if (!IsExact) + return false; + + pushInteger(S, IntResult, E->getType()); + return true; +} + +static bool interp_builtin_ia32_cvt_vector_to_int(InterpState &S, CodePtr OpPC, + const CallExpr *E) { + Pointer SrcVecPtr = S.Stk.pop<Pointer>(); + const Pointer &Dst = S.Stk.peek<Pointer>(); + + unsigned NumSrcElems = SrcVecPtr.getNumElems(); + unsigned NumDstElems = Dst.getNumElems(); + + if (NumSrcElems > NumDstElems) + return false; + + QualType ElemType = Dst.getFieldDesc()->getElemQualType(); + unsigned BitWidth = S.getASTContext().getIntWidth(ElemType); + bool IsUnsigned = ElemType->isUnsignedIntegerType(); + + PrimType ElemT = *S.getContext().classify(ElemType); + for (unsigned I = 0; I != NumSrcElems; ++I) { + const Floating &FloatElem = SrcVecPtr.elem<Floating>(I); + llvm::APSInt IntResult(BitWidth, IsUnsigned); + + bool IsExact = false; + // We only allow exact conversions so rounding mode does not matter for + // cvt* and cvtt* builtins + FloatElem.getAPFloat().convertToInteger( + IntResult, llvm::APFloat::rmTowardZero, &IsExact); + if (!IsExact) + return false; + INT_TYPE_SWITCH_NO_BOOL( + ElemT, { Dst.elem<T>(I) = T::from(IntResult.getZExtValue()); }); + } + + // Zero out remaining elements if the destination has more elements + // (e.g., cvtpd2dq converting 2 doubles(_m128d) to 2 ints stored in _m128i). + for (unsigned I = NumSrcElems; I != NumDstElems; ++I) + INT_TYPE_SWITCH_NO_BOOL(ElemT, { Dst.elem<T>(I) = T::from(0); }); + + Dst.initializeAllElements(); + return true; +} + bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const CallExpr *Call, uint32_t BuiltinID) { const ASTContext &ASTCtx = S.getASTContext(); @@ -6777,6 +6838,24 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const CallExpr *Call, case X86::BI__builtin_ia32_vpdpbusds256: case X86::BI__builtin_ia32_vpdpbusds512: return interp__builtin_ia32_vpdp(S, OpPC, Call, true); + case X86::BI__builtin_ia32_cvtss2si: + case X86::BI__builtin_ia32_cvtsd2si: + case X86::BI__builtin_ia32_cvttss2si: + case X86::BI__builtin_ia32_cvttsd2si: + case X86::BI__builtin_ia32_cvtss2si64: + case X86::BI__builtin_ia32_cvtsd2si64: + case X86::BI__builtin_ia32_cvttss2si64: + case X86::BI__builtin_ia32_cvttsd2si64: + return interp_builtin_ia32_cvt_scalar_to_int(S, OpPC, Call); + case X86::BI__builtin_ia32_cvtpd2dq: + case X86::BI__builtin_ia32_cvttpd2dq: + case X86::BI__builtin_ia32_cvtps2dq: + case X86::BI__builtin_ia32_cvtpd2dq256: + case X86::BI__builtin_ia32_cvtps2dq256: + case X86::BI__builtin_ia32_cvttps2dq: + case X86::BI__builtin_ia32_cvttpd2dq256: + case X86::BI__builtin_ia32_cvttps2dq256: + return interp_builtin_ia32_cvt_vector_to_int(S, OpPC, Call); default: S.FFDiag(S.Current->getLocation(OpPC), diag::note_invalid_subexpr_in_const_expr) diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp index ddcef9e7bfc6f..7aff17100d4ff 100644 --- a/clang/lib/AST/ExprConstant.cpp +++ b/clang/lib/AST/ExprConstant.cpp @@ -15267,6 +15267,45 @@ bool VectorExprEvaluator::VisitCallExpr(const CallExpr *E) { case X86::BI__builtin_ia32_vpdpbusds256: case X86::BI__builtin_ia32_vpdpbusds512: return EvalVectorDotProduct(true); + case X86::BI__builtin_ia32_cvtpd2dq: + case X86::BI__builtin_ia32_cvtps2dq: + case X86::BI__builtin_ia32_cvttpd2dq: + case X86::BI__builtin_ia32_cvttps2dq: + case X86::BI__builtin_ia32_cvtpd2dq256: + case X86::BI__builtin_ia32_cvtps2dq256: + case X86::BI__builtin_ia32_cvttpd2dq256: + case X86::BI__builtin_ia32_cvttps2dq256: { + APValue SrcVec; + if (!EvaluateAsRValue(Info, E->getArg(0), SrcVec) || !SrcVec.isVector()) + return false; + + const auto *VT = E->getType()->castAs<VectorType>(); + QualType EltTy = VT->getElementType(); + bool isUnsigned = EltTy->isUnsignedIntegerType(); + unsigned BitWidth = Info.Ctx.getIntWidth(EltTy); + + unsigned NumSrcElems = SrcVec.getVectorLength(); + unsigned NumDstElems = VT->getNumElements(); + + SmallVector<APValue, 8> ResultElts; + for (unsigned i = 0; i != NumDstElems; ++i) { + if (i < NumSrcElems) { + llvm::APFloat FloatElem = SrcVec.getVectorElt(i).getFloat(); + llvm::APSInt IntResult(BitWidth, isUnsigned); + bool IsExact = false; + // We only allow exact conversions so rounding mode does not matter for + // cvt* and cvtt* builtins + FloatElem.convertToInteger(IntResult, llvm::APFloat::rmTowardZero, + &IsExact); + if (!IsExact) + return false; + ResultElts.push_back(APValue(IntResult)); + } else + // Pad remaining lanes with zero + ResultElts.push_back(APValue(llvm::APSInt(BitWidth, isUnsigned))); + } + return Success(ResultElts, E); + } } } @@ -18689,6 +18728,34 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E, return Success(APValue(RetMask), E); } + case X86::BI__builtin_ia32_cvtss2si: + case X86::BI__builtin_ia32_cvtsd2si: + case X86::BI__builtin_ia32_cvttss2si: + case X86::BI__builtin_ia32_cvttsd2si: + case X86::BI__builtin_ia32_cvtss2si64: + case X86::BI__builtin_ia32_cvtsd2si64: + case X86::BI__builtin_ia32_cvttss2si64: + case X86::BI__builtin_ia32_cvttsd2si64: { + APValue ArgVal; + if (!EvaluateAsRValue(Info, E->getArg(0), ArgVal)) + return false; + + assert(ArgVal.isVector() && "Expected a vector argument"); + llvm::APFloat FloatElem = ArgVal.getVectorElt(0).getFloat(); + unsigned BitWidth = Info.Ctx.getIntWidth(E->getType()); + bool isUnsigned = E->getType()->isUnsignedIntegerType(); + + llvm::APSInt IntResult(BitWidth, isUnsigned); + bool IsExact = false; + // We only allow exact conversions so rounding mode does not matter for cvt* + // and cvtt* builtins + FloatElem.convertToInteger(IntResult, llvm::APFloat::rmTowardZero, + &IsExact); + if (!IsExact) + return false; + + return Success(IntResult, E); + } case X86::BI__builtin_ia32_vpshufbitqmb128_mask: case X86::BI__builtin_ia32_vpshufbitqmb256_mask: case X86::BI__builtin_ia32_vpshufbitqmb512_mask: { diff --git a/clang/lib/Headers/avxintrin.h b/clang/lib/Headers/avxintrin.h index fbd20e58329a3..372ece7a04298 100644 --- a/clang/lib/Headers/avxintrin.h +++ b/clang/lib/Headers/avxintrin.h @@ -2200,10 +2200,9 @@ _mm256_cvtpd_ps(__m256d __a) { /// \param __a /// A 256-bit vector of [8 x float]. /// \returns A 256-bit integer vector containing the converted values. -static __inline __m256i __DEFAULT_FN_ATTRS -_mm256_cvtps_epi32(__m256 __a) -{ - return (__m256i)__builtin_ia32_cvtps2dq256((__v8sf) __a); +static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm256_cvtps_epi32(__m256 __a) { + return (__m256i)__builtin_ia32_cvtps2dq256((__v8sf)__a); } /// Converts a 128-bit vector of [4 x float] into a 256-bit vector of [4 @@ -2236,10 +2235,9 @@ _mm256_cvtps_pd(__m128 __a) { /// \param __a /// A 256-bit vector of [4 x double]. /// \returns A 128-bit integer vector containing the converted values. -static __inline __m128i __DEFAULT_FN_ATTRS -_mm256_cvttpd_epi32(__m256d __a) -{ - return (__m128i)__builtin_ia32_cvttpd2dq256((__v4df) __a); +static __inline __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm256_cvttpd_epi32(__m256d __a) { + return (__m128i)__builtin_ia32_cvttpd2dq256((__v4df)__a); } /// Converts a 256-bit vector of [4 x double] into a 128-bit vector of @@ -2256,10 +2254,9 @@ _mm256_cvttpd_epi32(__m256d __a) /// \param __a /// A 256-bit vector of [4 x double]. /// \returns A 128-bit integer vector containing the converted values. -static __inline __m128i __DEFAULT_FN_ATTRS -_mm256_cvtpd_epi32(__m256d __a) -{ - return (__m128i)__builtin_ia32_cvtpd2dq256((__v4df) __a); +static __inline __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm256_cvtpd_epi32(__m256d __a) { + return (__m128i)__builtin_ia32_cvtpd2dq256((__v4df)__a); } /// Converts a vector of [8 x float] into eight signed truncated (rounded @@ -2276,10 +2273,9 @@ _mm256_cvtpd_epi32(__m256d __a) /// \param __a /// A 256-bit vector of [8 x float]. /// \returns A 256-bit integer vector containing the converted values. -static __inline __m256i __DEFAULT_FN_ATTRS -_mm256_cvttps_epi32(__m256 __a) -{ - return (__m256i)__builtin_ia32_cvttps2dq256((__v8sf) __a); +static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm256_cvttps_epi32(__m256 __a) { + return (__m256i)__builtin_ia32_cvttps2dq256((__v8sf)__a); } /// Returns the first element of the input vector of [4 x double]. diff --git a/clang/lib/Headers/emmintrin.h b/clang/lib/Headers/emmintrin.h index 3f039edf87e81..eef7077f81e29 100644 --- a/clang/lib/Headers/emmintrin.h +++ b/clang/lib/Headers/emmintrin.h @@ -1342,7 +1342,8 @@ _mm_cvtepi32_pd(__m128i __a) { /// A 128-bit vector of [2 x double]. /// \returns A 128-bit vector of [4 x i32] whose lower 64 bits contain the /// converted values. The upper 64 bits are set to zero. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_cvtpd_epi32(__m128d __a) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_cvtpd_epi32(__m128d __a) { return (__m128i)__builtin_ia32_cvtpd2dq((__v2df)__a); } @@ -1361,7 +1362,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_cvtpd_epi32(__m128d __a) { /// A 128-bit vector of [2 x double]. The lower 64 bits are used in the /// conversion. /// \returns A 32-bit signed integer containing the converted value. -static __inline__ int __DEFAULT_FN_ATTRS _mm_cvtsd_si32(__m128d __a) { +static __inline__ int __DEFAULT_FN_ATTRS_CONSTEXPR _mm_cvtsd_si32(__m128d __a) { return __builtin_ia32_cvtsd2si((__v2df)__a); } @@ -1455,7 +1456,8 @@ _mm_cvtss_sd(__m128d __a, __m128 __b) { /// A 128-bit vector of [2 x double]. /// \returns A 128-bit vector of [4 x i32] whose lower 64 bits contain the /// converted values. The upper 64 bits are set to zero. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_cvttpd_epi32(__m128d __a) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_cvttpd_epi32(__m128d __a) { return (__m128i)__builtin_ia32_cvttpd2dq((__v2df)__a); } @@ -1475,7 +1477,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_cvttpd_epi32(__m128d __a) { /// A 128-bit vector of [2 x double]. The lower 64 bits are used in the /// conversion. /// \returns A 32-bit signed integer containing the converted value. -static __inline__ int __DEFAULT_FN_ATTRS _mm_cvttsd_si32(__m128d __a) { +static __inline__ int __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_cvttsd_si32(__m128d __a) { return __builtin_ia32_cvttsd2si((__v2df)__a); } @@ -1494,7 +1497,8 @@ static __inline__ int __DEFAULT_FN_ATTRS _mm_cvttsd_si32(__m128d __a) { /// \param __a /// A 128-bit vector of [2 x double]. /// \returns A 64-bit vector of [2 x i32] containing the converted values. -static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_cvtpd_pi32(__m128d __a) { +static __inline__ __m64 __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_cvtpd_pi32(__m128d __a) { return __trunc64(__builtin_ia32_cvtpd2dq((__v2df)__a)); } @@ -1513,7 +1517,8 @@ static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_cvtpd_pi32(__m128d __a) { /// \param __a /// A 128-bit vector of [2 x double]. /// \returns A 64-bit vector of [2 x i32] containing the converted values. -static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_cvttpd_pi32(__m128d __a) { +static __inline__ __m64 __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_cvttpd_pi32(__m128d __a) { return __trunc64(__builtin_ia32_cvttpd2dq((__v2df)__a)); } @@ -3287,7 +3292,8 @@ _mm_cvtsi64_sd(__m128d __a, long long __b) { /// A 128-bit vector of [2 x double]. The lower 64 bits are used in the /// conversion. /// \returns A 64-bit signed integer containing the converted value. -static __inline__ long long __DEFAULT_FN_ATTRS _mm_cvtsd_si64(__m128d __a) { +static __inline__ long long __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_cvtsd_si64(__m128d __a) { return __builtin_ia32_cvtsd2si64((__v2df)__a); } @@ -3307,7 +3313,8 @@ static __inline__ long long __DEFAULT_FN_ATTRS _mm_cvtsd_si64(__m128d __a) { /// A 128-bit vector of [2 x double]. The lower 64 bits are used in the /// conversion. /// \returns A 64-bit signed integer containing the converted value. -static __inline__ long long __DEFAULT_FN_ATTRS _mm_cvttsd_si64(__m128d __a) { +static __inline__ long long __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_cvttsd_si64(__m128d __a) { return __builtin_ia32_cvttsd2si64((__v2df)__a); } #endif @@ -3340,7 +3347,8 @@ _mm_cvtepi32_ps(__m128i __a) { /// A 128-bit vector of [4 x float]. /// \returns A 128-bit integer vector of [4 x i32] containing the converted /// values. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_cvtps_epi32(__m128 __a) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_cvtps_epi32(__m128 __a) { return (__m128i)__builtin_ia32_cvtps2dq((__v4sf)__a); } @@ -3359,7 +3367,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_cvtps_epi32(__m128 __a) { /// \param __a /// A 128-bit vector of [4 x float]. /// \returns A 128-bit vector of [4 x i32] containing the converted values. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_cvttps_epi32(__m128 __a) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_cvttps_epi32(__m128 __a) { return (__m128i)__builtin_ia32_cvttps2dq((__v4sf)__a); } diff --git a/clang/lib/Headers/xmmintrin.h b/clang/lib/Headers/xmmintrin.h index 73eab9e460ca5..dc84cbe5e274a 100644 --- a/clang/lib/Headers/xmmintrin.h +++ b/clang/lib/Headers/xmmintrin.h @@ -1382,9 +1382,7 @@ _mm_ucomineq_ss(__m128 __a, __m128 __b) /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are /// used in the conversion. /// \returns A 32-bit integer containing the converted value. -static __inline__ int __DEFAULT_FN_ATTRS -_mm_cvtss_si32(__m128 __a) -{ +static __inline__ int __DEFAULT_FN_ATTRS_CONSTEXPR _mm_cvtss_si32(__m128 __a) { return __builtin_ia32_cvtss2si((__v4sf)__a); } @@ -1404,9 +1402,7 @@ _mm_cvtss_si32(__m128 __a) /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are /// used in the conversion. /// \returns A 32-bit integer containing the converted value. -static __inline__ int __DEFAULT_FN_ATTRS -_mm_cvt_ss2si(__m128 __a) -{ +static __inline__ int __DEFAULT_FN_ATTRS_CONSTEXPR _mm_cvt_ss2si(__m128 __a) { return _mm_cvtss_si32(__a); } @@ -1428,9 +1424,8 @@ _mm_cvt_ss2si(__m128 __a) /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are /// used in the conversion. /// \returns A 64-bit integer containing the converted value. -static __inline__ long long __DEFAULT_FN_ATTRS -_mm_cvtss_si64(__m128 __a) -{ +static __inline__ long long __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_cvtss_si64(__m128 __a) { return __builtin_ia32_cvtss2si64((__v4sf)__a); } @@ -1450,9 +1445,8 @@ _mm_cvtss_si64(__m128 __a) /// \param __a /// A 128-bit vector of [4 x float]. /// \returns A 64-bit integer vector containing the converted values. -static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2 -_mm_cvtps_pi32(__m128 __a) -{ +static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2_CONSTEXPR +_mm_cvtps_pi32(__m128 __a) { return __trunc64(__builtin_ia32_cvtps2dq((__v4sf)__zeroupper64(__a))); } @@ -1470,9 +1464,8 @@ _mm_cvtps_pi32(__m128 __a) /// \param __a /// A 128-bit vector of [4 x float]. /// \returns A 64-bit integer vector containing the converted values. -static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2 -_mm_cvt_ps2pi(__m128 __a) -{ +static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2_CONSTEXPR +_mm_cvt_ps2pi(__m128 __a) { return _mm_cvtps_pi32(__a); } @@ -1492,9 +1485,7 @@ _mm_cvt_ps2pi(__m128 __a) /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are /// used in the conversion. /// \returns A 32-bit integer containing the converted value. -static __inline__ int __DEFAULT_FN_ATTRS -_mm_cvttss_si32(__m128 __a) -{ +static __inline__ int __DEFAULT_FN_ATTRS_CONSTEXPR _mm_cvttss_si32(__m128 __a) { return __builtin_ia32_cvttss2si((__v4sf)__a); } @@ -1514,9 +1505,7 @@ _mm_cvttss_si32(__m128 __a) /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are /// used in the conversion. /// \returns A 32-bit integer containing the converted value. -static __inline__ int __DEFAULT_FN_ATTRS -_mm_cvtt_ss2si(__m128 __a) -{ +static __inline__ int __DEFAULT_FN_ATTRS_CONSTEXPR _mm_cvtt_ss2si(__m128 __a) { return _mm_cvttss_si32(__a); } @@ -1537,9 +1526,8 @@ _mm_cvtt_ss2si(__m128 __a) /// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are /// used in the conversion. /// \returns A 64-bit integer containing the converted value. -static __inline__ long long __DEFAULT_FN_ATTRS -_mm_cvttss_si64(__m128 __a) -{ +static __inline__ long long __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_cvttss_si64(__m128 __a) { return __builtin_ia32_cvttss2si64((__v4sf)__a); } #endif @@ -1560,9 +1548,8 @@ _mm_cvttss_si64(__m128 __a) /// \param __a /// A 128-bit vector of [4 x float]. /// \returns A 64-bit integer vector containing the converted values. -static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2 -_mm_cvttps_pi32(__m128 __a) -{ +static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2_CONSTEXPR +_mm_cvttps_pi32(__m128 __a) { return __trunc64(__builtin_ia32_cvttps2dq((__v4sf)__zeroupper64(__a))); } @@ -1581,9 +1568,8 @@ _mm_cvttps_pi32(__m128 __a) /// \param __a /// A 128-bit vector of [4 x float]. /// \returns A 64-bit integer vector containing the converted values. -static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2 -_mm_cvtt_ps2pi(__m128 __a) -{ +static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2_CONSTEXPR +_mm_cvtt_ps2pi(__m128 __a) { return _mm_cvttps_pi32(__a); } @@ -2956,9 +2942,8 @@ _mm_cvtpi32x2_ps(__m64 __a, __m64 __b) /// A 128-bit floating-point vector of [4 x float]. /// \returns A 64-bit integer vector of [4 x i16] containing the converted /// values. -static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2 -_mm_cvtps_pi16(__m128 __a) -{ +static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2_CONSTEXPR +_mm_cvtps_pi16(__m128 __a) { return __trunc64(__builtin_ia32_packssdw128( (__v4si)__builtin_ia32_cvtps2dq((__v4sf)__a), (__v4si)_mm_setzero_ps())); } @@ -2981,15 +2966,9 @@ _mm_cvtps_pi16(__m128 __a) /// 128-bit floating-point vector of [4 x float]. /// \returns A 64-bit integer vector of [8 x i8]. The lower 32 bits contain the /// converted values and the uppper 32 bits are set to zero. -static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2 -_mm_cvtps_pi8(__m128 __a) -{ - __m64 __b, __c; - - __b = _mm_cvtps_pi16(__a); - __c = _mm_setzero_si64(); - - return _mm_packs_pi16(__b, __c); +static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2_CONSTEXPR +_mm_cvtps_pi8(__m128 __a) { + return _mm_packs_pi16(_mm_cvtps_pi16(__a), _mm_setzero_si64()); } /// Extracts the sign bits from each single-precision floating-point diff --git a/clang/test/CodeGen/X86/avx-builtins.c b/clang/test/CodeGen/X86/avx-builtins.c index 6ed4217231119..d2667432b0b78 100644 --- a/clang/test/CodeGen/X86/avx-builtins.c +++ b/clang/test/CodeGen/X86/avx-builtins.c @@ -961,6 +961,7 @@ __m128i test_mm256_cvtpd_epi32(__m256d A) { // CHECK: call <4 x i32> @llvm.x86.avx.cvt.pd2dq.256(<4 x double> %{{.*}}) return _mm256_cvtpd_epi32(A); } +TEST_CONSTEXPR(match_v4si(_mm256_cvtpd_epi32((__m256d){+96.0, -47.0, +13.0, -11.0}), 96, -47, 13, -11)); __m128 test_mm256_cvtpd_ps(__m256d A) { // CHECK-LABEL: test_mm256_cvtpd_ps @@ -975,6 +976,7 @@ __m256i test_mm256_cvtps_epi32(__m256 A) { // CHECK: call <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float> %{{.*}}) return _mm256_cvtps_epi32(A); } +TEST_CONSTEXPR(match_v8si(_mm256_cvtps_epi32((__m256){+6.0f, -7.0f, +1.0f, -11.0f, +0.0f, 2.0f, -5.0f, +10.0f}), 6, -7, 1, -11, 0, 2, -5, 10)); __m256d test_mm256_cvtps_pd(__m128 A) { // CHECK-LABEL: test_mm256_cvtps_pd @@ -1010,12 +1012,14 @@ __m128i test_mm256_cvttpd_epi32(__m256d A) { // CHECK: call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %{{.*}}) return _mm256_cvttpd_epi32(A); } +TEST_CONSTEXPR(match_v4si(_mm256_cvttpd_epi32((__m256d){+96.0, -47.0, +13.0, -11.0}), 96, -47, 13, -11)); __m256i test_mm256_cvttps_epi32(__m256 A) { // CHECK-LABEL: test_mm256_cvttps_epi32 // CHECK: call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %{{.*}}) return _mm256_cvttps_epi32(A); } +TEST_CONSTEXPR(match_v8si(_mm256_cvttps_epi32((__m256){+36.0f, -74.0f, +91.0f, -11.0f, +10.0f, -2.0f, 5.0f, +11.0f}), 36, -74, 91, -11, 10, -2, 5, 11)); __m256d test_mm256_div_pd(__m256d A, __m256d B) { // CHECK-LABEL: test_mm256_div_pd diff --git a/clang/test/CodeGen/X86/mmx-builtins.c b/clang/test/CodeGen/X86/mmx-builtins.c index 90b42ba3cf099..3cae57b6500c8 100644 --- a/clang/test/CodeGen/X86/mmx-builtins.c +++ b/clang/test/CodeGen/X86/mmx-builtins.c @@ -194,12 +194,14 @@ __m64 test_mm_cvt_ps2pi(__m128 a) { // CHECK: call <4 x i32> @llvm.x86.sse2.cvtps2dq( return _mm_cvt_ps2pi(a); } +TEST_CONSTEXPR(match_v2si(_mm_cvt_ps2pi((__m128){-12.0f, +3.0f, +0.0f, +1.0f}), -12, 3)); __m64 test_mm_cvtpd_pi32(__m128d a) { // CHECK-LABEL: test_mm_cvtpd_pi32 // CHECK: call <4 x i32> @llvm.x86.sse2.cvtpd2dq( return _mm_cvtpd_pi32(a); } +TEST_CONSTEXPR(match_v2si(_mm_cvtpd_pi32((__m128d){+96.0, -24.0}), 96, -24)); __m128 test_mm_cvtpi8_ps(__m64 a) { // CHECK-LABEL: test_mm_cvtpi8_ps @@ -242,12 +244,15 @@ __m64 test_mm_cvtps_pi16(__m128 a) { // CHECK: call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> [[TMP0]], return _mm_cvtps_pi16(a); } +TEST_CONSTEXPR(match_v4hi(_mm_cvtps_pi16((__m128){+1.0f, -2.0f, +0.0f, -32768.0f}), 1, -2, 0, -32768)); __m64 test_mm_cvtps_pi32(__m128 a) { // CHECK-LABEL: test_mm_cvtps_pi32 // CHECK: call <4 x i32> @llvm.x86.sse2.cvtps2dq( return _mm_cvtps_pi32(a); } +TEST_CONSTEXPR(match_v2si(_mm_cvtps_pi32((__m128){+2.0f, 0.0f, 1.0f, -3.0f}), 2, 0)); +TEST_CONSTEXPR(match_v2si(_mm_cvtps_pi32((__m128){-7.0f, +4.0f, 0.0f, -18.0f}), -7, 4)); __m128 test_mm_cvtpu8_ps(__m64 a) { // CHECK-LABEL: test_mm_cvtpu8_ps @@ -282,12 +287,14 @@ __m64 test_mm_cvttpd_pi32(__m128d a) { // CHECK: call <4 x i32> @llvm.x86.sse2.cvttpd2dq( return _mm_cvttpd_pi32(a); } +TEST_CONSTEXPR(match_v2si(_mm_cvttpd_pi32((__m128d){-69.0, +32.0}), -69, 32)); __m64 test_mm_cvttps_pi32(__m128 a) { // CHECK-LABEL: test_mm_cvttps_pi32 // CHECK: call <4 x i32> @llvm.x86.sse2.cvttps2dq( return _mm_cvttps_pi32(a); } +TEST_CONSTEXPR(match_v2si(_mm_cvttps_pi32((__m128){+2.0f, -3.0f, +0.0f, +1.0f}), 2, -3)); int test_mm_extract_pi16(__m64 a) { // CHECK-LABEL: test_mm_extract_pi16 diff --git a/clang/test/CodeGen/X86/sse-builtins.c b/clang/test/CodeGen/X86/sse-builtins.c index 87b9a99a0e058..b26d39d5b7fa4 100644 --- a/clang/test/CodeGen/X86/sse-builtins.c +++ b/clang/test/CodeGen/X86/sse-builtins.c @@ -325,6 +325,8 @@ int test_mm_cvt_ss2si(__m128 A) { // CHECK: call {{.*}}i32 @llvm.x86.sse.cvtss2si(<4 x float> %{{.*}}) return _mm_cvt_ss2si(A); } +TEST_CONSTEXPR(_mm_cvt_ss2si((__m128){+3.0f}) == 3); +TEST_CONSTEXPR(_mm_cvt_ss2si((__m128){-5.0f}) == -5); __m128 test_mm_cvtsi32_ss(__m128 A, int B) { // CHECK-LABEL: test_mm_cvtsi32_ss @@ -364,6 +366,8 @@ int test_mm_cvtss_si32(__m128 A) { // CHECK: call {{.*}}i32 @llvm.x86.sse.cvtss2si(<4 x float> %{{.*}}) return _mm_cvtss_si32(A); } +TEST_CONSTEXPR(_mm_cvtss_si32((__m128){+3.0f}) == 3); +TEST_CONSTEXPR(_mm_cvtss_si32((__m128){-2.0f}) == -2); #ifdef __x86_64__ long long test_mm_cvtss_si64(__m128 A) { @@ -371,6 +375,9 @@ long long test_mm_cvtss_si64(__m128 A) { // CHECK: call {{.*}}i64 @llvm.x86.sse.cvtss2si64(<4 x float> %{{.*}}) return _mm_cvtss_si64(A); } +TEST_CONSTEXPR(_mm_cvtss_si64((__m128){+1.0f}) == 1LL); +TEST_CONSTEXPR(_mm_cvtss_si64((__m128){-7.0f}) == -7LL); +TEST_CONSTEXPR(_mm_cvtss_si64((__m128){0x1p45f}) == (1LL << 45)); #endif int test_mm_cvtt_ss2si(__m128 A) { @@ -378,12 +385,15 @@ int test_mm_cvtt_ss2si(__m128 A) { // CHECK: call {{.*}}i32 @llvm.x86.sse.cvttss2si(<4 x float> %{{.*}}) return _mm_cvtt_ss2si(A); } +TEST_CONSTEXPR(_mm_cvtt_ss2si((__m128){+3.0f}) == 3); int test_mm_cvttss_si32(__m128 A) { // CHECK-LABEL: test_mm_cvttss_si32 // CHECK: call {{.*}}i32 @llvm.x86.sse.cvttss2si(<4 x float> %{{.*}}) return _mm_cvttss_si32(A); } +TEST_CONSTEXPR(_mm_cvttss_si32((__m128){+3.0f}) == 3); + #ifdef __x86_64__ long long test_mm_cvttss_si64(__m128 A) { @@ -391,6 +401,8 @@ long long test_mm_cvttss_si64(__m128 A) { // CHECK: call {{.*}}i64 @llvm.x86.sse.cvttss2si64(<4 x float> %{{.*}}) return _mm_cvttss_si64(A); } +TEST_CONSTEXPR(_mm_cvttss_si64((__m128){-12.0f}) == -12LL); +TEST_CONSTEXPR(_mm_cvttss_si64((__m128){0x1p40f}) == (1LL << 40)); #endif __m128 test_mm_div_ps(__m128 A, __m128 B) { diff --git a/clang/test/CodeGen/X86/sse2-builtins.c b/clang/test/CodeGen/X86/sse2-builtins.c index 3e36c0047baf0..c0c4acf2daea5 100644 --- a/clang/test/CodeGen/X86/sse2-builtins.c +++ b/clang/test/CodeGen/X86/sse2-builtins.c @@ -566,6 +566,7 @@ __m128i test_mm_cvtpd_epi32(__m128d A) { // CHECK: call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %{{.*}}) return _mm_cvtpd_epi32(A); } +TEST_CONSTEXPR(match_v4si(_mm_cvtpd_epi32((__m128d){12.0, -45.0}), 12, -45, 0, 0)); __m128 test_mm_cvtpd_ps(__m128d A) { // CHECK-LABEL: test_mm_cvtpd_ps @@ -580,6 +581,7 @@ __m128i test_mm_cvtps_epi32(__m128 A) { // CHECK: call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %{{.*}}) return _mm_cvtps_epi32(A); } +TEST_CONSTEXPR(match_v4si(_mm_cvtps_epi32((__m128){-96.0f, +32.0f, -12.0f, +0.0f}), -96, 32, -12, 0)); __m128d test_mm_cvtps_pd(__m128 A) { // CHECK-LABEL: test_mm_cvtps_pd @@ -601,6 +603,7 @@ int test_mm_cvtsd_si32(__m128d A) { // CHECK: call {{.*}}i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %{{.*}}) return _mm_cvtsd_si32(A); } +TEST_CONSTEXPR(_mm_cvtsd_si32((__m128d){+45.0, -12.0}) == 45); #ifdef __x86_64__ long long test_mm_cvtsd_si64(__m128d A) { @@ -608,6 +611,8 @@ long long test_mm_cvtsd_si64(__m128d A) { // X64: call {{.*}}i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %{{.*}}) return _mm_cvtsd_si64(A); } +TEST_CONSTEXPR(_mm_cvtsd_si64((__m128d){-78.0, +32.0}) == -78LL); +TEST_CONSTEXPR(_mm_cvtsd_si64((__m128d){0x1p62f}) == (1LL << 62)); #endif __m128 test_mm_cvtsd_ss(__m128 A, __m128d B) { @@ -682,18 +687,21 @@ __m128i test_mm_cvttpd_epi32(__m128d A) { // CHECK: call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %{{.*}}) return _mm_cvttpd_epi32(A); } +TEST_CONSTEXPR(match_v4si(_mm_cvttpd_epi32((__m128d){+45.0, -96.0}), 45, -96, 0, 0)); __m128i test_mm_cvttps_epi32(__m128 A) { // CHECK-LABEL: test_mm_cvttps_epi32 // CHECK: call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %{{.*}}) return _mm_cvttps_epi32(A); } +TEST_CONSTEXPR(match_v4si(_mm_cvttps_epi32((__m128){-16.0f, +34.0f, -2.0f, +1.0f}), -16, 34, -2, 1)); int test_mm_cvttsd_si32(__m128d A) { // CHECK-LABEL: test_mm_cvttsd_si32 // CHECK: call {{.*}}i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %{{.*}}) return _mm_cvttsd_si32(A); } +TEST_CONSTEXPR(_mm_cvttsd_si32((__m128d){-326.0, -96.0}) == -326); #ifdef __x86_64__ long long test_mm_cvttsd_si64(__m128d A) { @@ -701,6 +709,8 @@ long long test_mm_cvttsd_si64(__m128d A) { // X64: call {{.*}}i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %{{.*}}) return _mm_cvttsd_si64(A); } +TEST_CONSTEXPR(_mm_cvttsd_si64((__m128d){-78.0, +45.0}) == -78LL); +TEST_CONSTEXPR(_mm_cvttsd_si64((__m128d){0x1p61f}) == (1LL << 61)); #endif __m128d test_mm_div_pd(__m128d A, __m128d B) { _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
