llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang-codegen Author: TelGome <details> <summary>Changes</summary> Collapse the scalar halfword (`mqacc.h*`, i32) and word (`mqacc.w*`, i64) forms of the Packed Q-format Multiply Parts Accumulate intrinsics into one overloaded intrinsic per element selection (`int_riscv_mqacc_00` covers both `mqacc.h00` and `mqacc.w00`, via result/operand types), mirroring #<!-- -->218875. Packed form (`pmqacc_h*`) and C builtins stay split. No functional change to the generated code. --- Patch is 33.40 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/219345.diff 6 Files Affected: - (modified) clang/lib/CodeGen/TargetBuiltins/RISCV.cpp (+13-24) - (modified) clang/test/CodeGen/RISCV/rvp-intrinsics.c (+24-24) - (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+7-13) - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+63-84) - (modified) llvm/test/CodeGen/RISCV/rvp-simd-32.ll (+6-6) - (modified) llvm/test/CodeGen/RISCV/rvp-simd-64.ll (+6-6) ``````````diff diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp index 91f451e34c2c9..49ad62ae333ea 100644 --- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp @@ -1648,24 +1648,6 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, switch (BuiltinID) { default: llvm_unreachable("unexpected builtin ID"); - case RISCV::BI__builtin_riscv_mqacc_h00_i32: - ID = Intrinsic::riscv_mqacc_h00; - break; - case RISCV::BI__builtin_riscv_mqacc_h01_i32: - ID = Intrinsic::riscv_mqacc_h01; - break; - case RISCV::BI__builtin_riscv_mqacc_h11_i32: - ID = Intrinsic::riscv_mqacc_h11; - break; - case RISCV::BI__builtin_riscv_mqracc_h00_i32: - ID = Intrinsic::riscv_mqracc_h00; - break; - case RISCV::BI__builtin_riscv_mqracc_h01_i32: - ID = Intrinsic::riscv_mqracc_h01; - break; - case RISCV::BI__builtin_riscv_mqracc_h11_i32: - ID = Intrinsic::riscv_mqracc_h11; - break; case RISCV::BI__builtin_riscv_pmqacc_h00_i32x2: ID = Intrinsic::riscv_pmqacc_h00; break; @@ -1684,23 +1666,30 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, case RISCV::BI__builtin_riscv_pmqracc_h11_i32x2: ID = Intrinsic::riscv_pmqracc_h11; break; + // Scalar "Q-format" Multiply Parts Accumulate + case RISCV::BI__builtin_riscv_mqacc_h00_i32: case RISCV::BI__builtin_riscv_mqacc_w00_i64: - ID = Intrinsic::riscv_mqacc_w00; + ID = Intrinsic::riscv_mqacc_00; break; + case RISCV::BI__builtin_riscv_mqacc_h01_i32: case RISCV::BI__builtin_riscv_mqacc_w01_i64: - ID = Intrinsic::riscv_mqacc_w01; + ID = Intrinsic::riscv_mqacc_01; break; + case RISCV::BI__builtin_riscv_mqacc_h11_i32: case RISCV::BI__builtin_riscv_mqacc_w11_i64: - ID = Intrinsic::riscv_mqacc_w11; + ID = Intrinsic::riscv_mqacc_11; break; + case RISCV::BI__builtin_riscv_mqracc_h00_i32: case RISCV::BI__builtin_riscv_mqracc_w00_i64: - ID = Intrinsic::riscv_mqracc_w00; + ID = Intrinsic::riscv_mqracc_00; break; + case RISCV::BI__builtin_riscv_mqracc_h01_i32: case RISCV::BI__builtin_riscv_mqracc_w01_i64: - ID = Intrinsic::riscv_mqracc_w01; + ID = Intrinsic::riscv_mqracc_01; break; + case RISCV::BI__builtin_riscv_mqracc_h11_i32: case RISCV::BI__builtin_riscv_mqracc_w11_i64: - ID = Intrinsic::riscv_mqracc_w11; + ID = Intrinsic::riscv_mqracc_11; break; } diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c index 74a7cb60a6afa..8266259811c14 100644 --- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c +++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c @@ -10113,7 +10113,7 @@ uint32x2_t test_pnclipup_u32x2(uint64_t rs1, uint64_t rs2) { // RV32-NEXT: [[ENTRY:.*:]] // RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> // RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> -// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.h00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) // RV32-NEXT: ret i32 [[TMP2]] // // RV64-LABEL: define dso_local signext i32 @test_mqacc_h00_i32( @@ -10121,7 +10121,7 @@ uint32x2_t test_pnclipup_u32x2(uint64_t rs1, uint64_t rs2) { // RV64-NEXT: [[ENTRY:.*:]] // RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> // RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> -// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.h00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) // RV64-NEXT: ret i32 [[TMP2]] // @@ -10133,7 +10133,7 @@ int32_t test_mqacc_h00_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { // RV32-NEXT: [[ENTRY:.*:]] // RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> // RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> -// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.h01.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.01.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) // RV32-NEXT: ret i32 [[TMP2]] // // RV64-LABEL: define dso_local signext i32 @test_mqacc_h01_i32( @@ -10141,7 +10141,7 @@ int32_t test_mqacc_h00_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { // RV64-NEXT: [[ENTRY:.*:]] // RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> // RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> -// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.h01.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.01.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) // RV64-NEXT: ret i32 [[TMP2]] // int32_t test_mqacc_h01_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { @@ -10153,7 +10153,7 @@ int32_t test_mqacc_h01_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { // RV32-NEXT: [[ENTRY:.*:]] // RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> // RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> -// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.h11.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.11.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) // RV32-NEXT: ret i32 [[TMP2]] // // RV64-LABEL: define dso_local signext i32 @test_mqacc_h11_i32( @@ -10161,7 +10161,7 @@ int32_t test_mqacc_h01_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { // RV64-NEXT: [[ENTRY:.*:]] // RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> // RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> -// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.h11.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.11.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) // RV64-NEXT: ret i32 [[TMP2]] // int32_t test_mqacc_h11_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { @@ -10173,7 +10173,7 @@ int32_t test_mqacc_h11_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { // RV32-NEXT: [[ENTRY:.*:]] // RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> // RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> -// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqracc.h00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqracc.00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) // RV32-NEXT: ret i32 [[TMP2]] // // RV64-LABEL: define dso_local signext i32 @test_mqracc_h00_i32( @@ -10181,7 +10181,7 @@ int32_t test_mqacc_h11_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { // RV64-NEXT: [[ENTRY:.*:]] // RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> // RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> -// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqracc.h00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqracc.00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) // RV64-NEXT: ret i32 [[TMP2]] // int32_t test_mqracc_h00_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { @@ -10193,7 +10193,7 @@ int32_t test_mqracc_h00_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { // RV32-NEXT: [[ENTRY:.*:]] // RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> // RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> -// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqracc.h01.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqracc.01.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) // RV32-NEXT: ret i32 [[TMP2]] // // RV64-LABEL: define dso_local signext i32 @test_mqracc_h01_i32( @@ -10201,7 +10201,7 @@ int32_t test_mqracc_h00_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { // RV64-NEXT: [[ENTRY:.*:]] // RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> // RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> -// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqracc.h01.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqracc.01.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) // RV64-NEXT: ret i32 [[TMP2]] // int32_t test_mqracc_h01_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { @@ -10213,7 +10213,7 @@ int32_t test_mqracc_h01_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { // RV32-NEXT: [[ENTRY:.*:]] // RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> // RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> -// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqracc.h11.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqracc.11.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) // RV32-NEXT: ret i32 [[TMP2]] // // RV64-LABEL: define dso_local signext i32 @test_mqracc_h11_i32( @@ -10221,7 +10221,7 @@ int32_t test_mqracc_h01_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { // RV64-NEXT: [[ENTRY:.*:]] // RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> // RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> -// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqracc.h11.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqracc.11.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) // RV64-NEXT: ret i32 [[TMP2]] // int32_t test_mqracc_h11_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) { @@ -10379,7 +10379,7 @@ int32x2_t test_pmqracc_h11_i32x2(int32x2_t rd, int16x4_t rs1, int16x4_t rs2) { // RV32-NEXT: [[ENTRY:.*:]] // RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> // RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> -// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.w00.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.00.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) // RV32-NEXT: ret i64 [[TMP2]] // // RV64-LABEL: define dso_local i64 @test_mqacc_w00_i64( @@ -10387,7 +10387,7 @@ int32x2_t test_pmqracc_h11_i32x2(int32x2_t rd, int16x4_t rs1, int16x4_t rs2) { // RV64-NEXT: [[ENTRY:.*:]] // RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> // RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> -// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.w00.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.00.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) // RV64-NEXT: ret i64 [[TMP2]] // int64_t test_mqacc_w00_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { @@ -10399,7 +10399,7 @@ int64_t test_mqacc_w00_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { // RV32-NEXT: [[ENTRY:.*:]] // RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> // RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> -// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.w01.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.01.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) // RV32-NEXT: ret i64 [[TMP2]] // // RV64-LABEL: define dso_local i64 @test_mqacc_w01_i64( @@ -10407,7 +10407,7 @@ int64_t test_mqacc_w00_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { // RV64-NEXT: [[ENTRY:.*:]] // RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> // RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> -// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.w01.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.01.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) // RV64-NEXT: ret i64 [[TMP2]] // int64_t test_mqacc_w01_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { @@ -10419,7 +10419,7 @@ int64_t test_mqacc_w01_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { // RV32-NEXT: [[ENTRY:.*:]] // RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> // RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> -// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.w11.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.11.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) // RV32-NEXT: ret i64 [[TMP2]] // // RV64-LABEL: define dso_local i64 @test_mqacc_w11_i64( @@ -10427,7 +10427,7 @@ int64_t test_mqacc_w01_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { // RV64-NEXT: [[ENTRY:.*:]] // RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> // RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> -// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.w11.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqacc.11.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) // RV64-NEXT: ret i64 [[TMP2]] // int64_t test_mqacc_w11_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { @@ -10439,7 +10439,7 @@ int64_t test_mqacc_w11_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { // RV32-NEXT: [[ENTRY:.*:]] // RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> // RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> -// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.w00.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.00.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) // RV32-NEXT: ret i64 [[TMP2]] // // RV64-LABEL: define dso_local i64 @test_mqracc_w00_i64( @@ -10447,7 +10447,7 @@ int64_t test_mqacc_w11_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { // RV64-NEXT: [[ENTRY:.*:]] // RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> // RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> -// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.w00.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.00.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) // RV64-NEXT: ret i64 [[TMP2]] // int64_t test_mqracc_w00_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { @@ -10459,7 +10459,7 @@ int64_t test_mqracc_w00_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { // RV32-NEXT: [[ENTRY:.*:]] // RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> // RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> -// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.w01.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.01.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) // RV32-NEXT: ret i64 [[TMP2]] // // RV64-LABEL: define dso_local i64 @test_mqracc_w01_i64( @@ -10467,7 +10467,7 @@ int64_t test_mqracc_w00_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { // RV64-NEXT: [[ENTRY:.*:]] // RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> // RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> -// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.w01.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.01.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) // RV64-NEXT: ret i64 [[TMP2]] // int64_t test_mqracc_w01_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { @@ -10479,7 +10479,7 @@ int64_t test_mqracc_w01_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { // RV32-NEXT: [[ENTRY:.*:]] // RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> // RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> -// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.w11.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.11.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) // RV32-NEXT: ret i64 [[TMP2]] // // RV64-LABEL: define dso_local i64 @test_mqracc_w11_i64( @@ -10487,7 +10487,7 @@ int64_t test_mqracc_w01_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { // RV64-NEXT: [[ENTRY:.*:]] // RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> // RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> -// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.w11.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.mqracc.11.i64.v2i32(i64 [[RD]], <2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) // RV64-NEXT: ret i64 [[TMP2]] // int64_t test_mqracc_w11_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index b059537fc4943..3ea0bea993a2a 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -2162,30 +2162,24 @@ class RVPBinaryIntrinsic def int_riscv_pnclipp : RVPNarrowingClipIntrinsic; def int_riscv_pnclipup : RVPNarrowingClipIntrinsic; - // Packed "Q-format" Multiply Parts Accumulate + // Packed "Q-format" Multiply Parts Accumulate. class RVPQFormatAccIntrinsic : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, llvm_any_ty, LLVMMatchType<1>], [IntrNoMem, IntrSpeculatable]>; - def int_riscv_mqacc_h00 : RVPQFormatAccIntrinsic; - def int_riscv_mqacc_h01 : RVPQFormatAccIntrinsic; - def int_riscv_mqacc_h11 : RVPQFormatAccIntrinsic; - def int_riscv_mqracc_h00 : RVPQFormatAccIntrinsic; - def int_riscv_mqracc_h01 : RVPQFormatAccIntrinsic; - def int_riscv_mqracc_h11 : RVPQFormatAccIntrinsic; + def int_riscv_mqacc_00 : RVPQFormatAccIntrinsic; + def int_riscv_mqacc_01 : RVPQFormatAccIntrinsic; + def int_riscv_mqacc_11 : RVPQFormatAccIntrinsic; + def int_riscv_mqracc_00 : RVPQFormatAccIntrinsic; + def int_riscv_mqracc_01 : RVPQFormatAccIntrinsic; + def int_riscv_mqracc_11 : RVPQFormatAccIntrinsic; def int_riscv_pmqacc_h00 : RVPQFormatAccIntrinsic; def int_riscv_pmqacc_h01 : RVPQFormatAccIntrinsic; def int_riscv_pmqacc_h11 : RVPQFormatAccIntrinsic; def int_riscv_pmqracc_h00 : RVPQFormatAccIntrinsic; def int_riscv_pmqracc_h01 : RVPQFormatAccIntrinsic; def int_riscv_pmqracc_h11 : RVPQFormatAccIntrinsic; - def int_riscv_mqacc_w00 : RVPQFormatAccIntrinsic; - def int_riscv_mqacc_w01 : RVPQFormatAccIntrinsic; - def int_riscv_mqacc_w11 : RVPQFormatAccIntrinsic; - def int_riscv_mqracc_w00 : RVPQFormatAccIntrinsic; - def int_riscv_mqracc_w01 : RVPQFormatAccIntrinsic; - def int_riscv_mqracc_w11 : RVPQFormatAccIntrinsic; } // TargetPrefix = "riscv" //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 470599784314a..9b80e1f304b3e 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -12270,28 +12270,22 @@ static unsigned getRVPQFormatAccScalarOpcode(Intrinsic::ID IntNo) { switch (IntNo) { default: llvm_unreachable("Unexpected RISC-V packed Q-format accumulate intrinsic"); - c... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/219345 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
