================
@@ -17975,6 +17975,73 @@ static SDValue combineAddMulh(SDNode *N, SelectionDAG
&DAG,
return DAG.getNode(RISCVISD::MULHSU, DL, VT, X, Mulh.getOperand(1));
}
+static SDValue combinePExtWideningAddSub(SDNode *N, SelectionDAG &DAG,
+ const RISCVSubtarget &Subtarget) {
+ // Recognize the RV64 decompositions listed for the 32-bit packed widening
+ // add/sub operations. Mixed signed/unsigned PM2 forms are outside that
group.
+ if (!Subtarget.hasStdExtP() || !Subtarget.is64Bit())
+ return SDValue();
+
+ unsigned Opcode = N->getOpcode();
+ if (Opcode != ISD::ADD && Opcode != ISD::SUB)
+ return SDValue();
+
+ EVT VT = N->getValueType(0);
+ if (VT != MVT::v4i16 && VT != MVT::v2i32)
+ return SDValue();
+
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ bool N0IsSExt = N0.getOpcode() == ISD::SIGN_EXTEND;
+ bool N0IsZExt = N0.getOpcode() == ISD::ZERO_EXTEND;
+ bool N1IsSExt = N1.getOpcode() == ISD::SIGN_EXTEND;
+ bool N1IsZExt = N1.getOpcode() == ISD::ZERO_EXTEND;
+ if (!(N0IsSExt || N0IsZExt) || !(N1IsSExt || N1IsZExt) || !N0.hasOneUse() ||
----------------
topperc wrote:
Should we check that N0 is ZERO_EXTEND/SIGN_EXTEND and that N1 has the same
opcode? That should be able to reduce from 4 flags to 1.
https://github.com/llvm/llvm-project/pull/219348
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