Author: Liao Chunyu Date: 2026-09-02T14:18:34+08:00 New Revision: 311edeecd260dcd6225a6c5c3e5a7b5cc9587fb3
URL: https://github.com/llvm/llvm-project/commit/311edeecd260dcd6225a6c5c3e5a7b5cc9587fb3 DIFF: https://github.com/llvm/llvm-project/commit/311edeecd260dcd6225a6c5c3e5a7b5cc9587fb3.diff LOG: [RISCV]Support Sspmp, Sspmpen and Smpmpdeleg Extensions (#207696) https://docs.riscv.org/reference/isa/extensions/sspmp/_attachments/riscv-spmp.pdf Added: llvm/test/MC/RISCV/spmp-csr-names.s Modified: clang/test/Driver/print-supported-extensions-riscv.c clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.md llvm/docs/ReleaseNotes.md llvm/lib/Target/RISCV/RISCVFeatures.td llvm/lib/Target/RISCV/RISCVSystemOperands.td llvm/test/CodeGen/RISCV/features-info.ll llvm/test/MC/RISCV/attribute-arch.s llvm/unittests/TargetParser/RISCVISAInfoTest.cpp Removed: ################################################################################ diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 545cc3673fa32..8efe2347a56d7 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -136,6 +136,7 @@ // CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection) // CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level Pointer Masking for M-mode) // CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode) +// CHECK-NEXT: smpmpdeleg 1.0 'Smpmpdeleg' (Sharing Hardware Resources between PMP and SPMP) // CHECK-NEXT: smrnmi 1.0 'Smrnmi' (Resumable Non-Maskable Interrupts) // CHECK-NEXT: smstateen 1.0 'Smstateen' (Machine-mode view of the state-enable extension) // CHECK-NEXT: ssaia 1.0 'Ssaia' (Advanced Interrupt Architecture Supervisor Level) @@ -148,6 +149,8 @@ // CHECK-NEXT: ssdbltrp 1.0 'Ssdbltrp' (Double Trap Supervisor Level) // CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode) // CHECK-NEXT: sspm 1.0 'Sspm' (Indicates Supervisor-mode Pointer Masking) +// CHECK-NEXT: sspmp 1.0 'Sspmp' (S-level Physical Memory Protection (SPMP)) +// CHECK-NEXT: sspmpen 1.0 'Sspmpen' (Optimizing Context Switching of SPMP Entries) // CHECK-NEXT: ssqosid 1.0 'Ssqosid' (Quality-of-Service (QoS) Identifiers) // CHECK-NEXT: ssstateen 1.0 'Ssstateen' (Supervisor-mode view of the state-enable extension) // CHECK-NEXT: ssstrict 1.0 'Ssstrict' (No non-conforming extensions are present) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index cadd95f843592..dca3bc32f045d 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -44,6 +44,7 @@ // CHECK-NOT: __riscv_smip {{.*$}} // CHECK-NOT: __riscv_smmpm{{.*$}} // CHECK-NOT: __riscv_smnpm{{.*$}} +// CHECK-NOT: __riscv_smpmpdeleg {{.*$}} // CHECK-NOT: __riscv_smpmpmt {{.*$}} // CHECK-NOT: __riscv_smrnmi {{.*$}} // CHECK-NOT: __riscv_smstateen {{.*$}} @@ -61,6 +62,8 @@ // CHECK-NOT: __riscv_ssip {{.*$}} // CHECK-NOT: __riscv_ssnpm{{.*$}} // CHECK-NOT: __riscv_sspm{{.*$}} +// CHECK-NOT: __riscv_sspmp {{.*$}} +// CHECK-NOT: __riscv_sspmpen {{.*$}} // CHECK-NOT: __riscv_ssqosid{{.*$}} // CHECK-NOT: __riscv_ssstateen {{.*$}} // CHECK-NOT: __riscv_ssstrict {{.*$}} @@ -1373,6 +1376,36 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SSCSRIND-EXT %s // CHECK-SSCSRIND-EXT: __riscv_sscsrind 1000000{{$}} +// RUN: %clang --target=riscv32 \ +// RUN: -march=rv32isspmp1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSPMP-EXT %s +// RUN: %clang --target=riscv64 \ +// RUN: -march=rv64isspmp1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSPMP-EXT %s +// CHECK-SSPMP-EXT: __riscv_sscsrind 1000000{{$}} +// CHECK-SSPMP-EXT: __riscv_sspmp 1000000{{$}} + +// RUN: %clang --target=riscv32 \ +// RUN: -march=rv32isspmpen1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSPMPEN-EXT %s +// RUN: %clang --target=riscv64 \ +// RUN: -march=rv64isspmpen1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSPMPEN-EXT %s +// CHECK-SSPMPEN-EXT: __riscv_sscsrind 1000000{{$}} +// CHECK-SSPMPEN-EXT: __riscv_sspmp 1000000{{$}} +// CHECK-SSPMPEN-EXT: __riscv_sspmpen 1000000{{$}} + +// RUN: %clang --target=riscv32 \ +// RUN: -march=rv32ismpmpdeleg1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMPMPDELEG-EXT %s +// RUN: %clang --target=riscv64 \ +// RUN: -march=rv64ismpmpdeleg1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMPMPDELEG-EXT %s +// CHECK-SMPMPDELEG-EXT: __riscv_smcsrind 1000000{{$}} +// CHECK-SMPMPDELEG-EXT: __riscv_smpmpdeleg 1000000{{$}} +// CHECK-SMPMPDELEG-EXT: __riscv_sscsrind 1000000{{$}} +// CHECK-SMPMPDELEG-EXT: __riscv_sspmp 1000000{{$}} + // RUN: %clang --target=riscv32 \ // RUN: -march=rv32ismdbltrp1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SMDBLTRP-EXT %s diff --git a/llvm/docs/RISCVUsage.md b/llvm/docs/RISCVUsage.md index 1e89c8d7d82bd..a3b9c0fc90a1f 100644 --- a/llvm/docs/RISCVUsage.md +++ b/llvm/docs/RISCVUsage.md @@ -124,6 +124,7 @@ on support follow. | `Smepmp` | Supported | | `Smmpm` | Supported | | `Smnpm` | Supported | +| `Smpmpdeleg` | Supported | | `Smrnmi` | Supported | | `Smstateen` | Assembly Support | | `Ssaia` | Supported | @@ -136,6 +137,8 @@ on support follow. | `Ssdbltrp` | Supported | | `Ssnpm` | Supported | | `Sspm` | Supported | +| `Sspmp` | Supported | +| `Sspmpen` | Supported | | `Ssqosid` | Assembly Support | | `Ssstateen` | Assembly Support ([See note](#riscv-profiles-extensions-note)) | | `Ssstrict` | Assembly Support ([See note](#riscv-profiles-extensions-note)) | diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 5c288a0ee6fa7..9b858caadb6c3 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -217,6 +217,7 @@ Makes programs 10x faster by doing Special New Thing. push/pop extensions. * Bump Svukte extension to 1.0. * Remove experimental from Zicfiss. +* Added support for `Sspmp`, `Sspmpen` and `Smpmpdeleg` extensions. ### Changes to the WebAssembly Backend diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index d388e0ea81c19..1f396b61962f0 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1147,6 +1147,17 @@ def FeatureStdExtSsccfg def FeatureStdExtSsccptr : RISCVExtension<1, 0, "Main memory supports page table reads">; +def FeatureStdExtSspmp + : RISCVExtension<1, 0, "S-level Physical Memory Protection (SPMP)", + [FeatureStdExtSscsrind]>; +def FeatureStdExtSspmpen + : RISCVExtension<1, 0, "Optimizing Context Switching of SPMP Entries", + [FeatureStdExtSspmp]>; + +def FeatureStdExtSmpmpdeleg + : RISCVExtension<1, 0, "Sharing Hardware Resources between PMP and SPMP", + [FeatureStdExtSmcsrind, FeatureStdExtSspmp]>; + def FeatureStdExtSscofpmf : RISCVExtension<1, 0, "Count Overflow and Mode-Based Filtering">; diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td index 421a3ae37338d..0a892d1e3ca53 100644 --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -192,6 +192,8 @@ foreach i = 4...6 in { def : SysReg<"satp", 0x180>; def : DeprecatedSysRegName<"sptbr", 0x180>; +def : SysReg<"spmpen", 0x183>; +def : SysReg<"spmpenh", 0x193, RV32Only=true>; //===----------------------------------------------------------------------===// // Supervisor Timer Compare @@ -413,6 +415,8 @@ def : SysReg<"mseccfgh", 0x757, RV32Only=true>; // Machine Memory Protection //===----------------------------------------------------------------------===// +def : SysReg<"mpmpdeleg", 0x316>; + // pmpcfg0-pmpcfg15 at 0x3A0-0x3AF. Odd-numbered registers are RV32-only. foreach i = 0...15 in { def : SysReg<"pmpcfg"#i, !add(0x3A0, i), RV32Only=!and(i, 1)>; diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index b756a2f862b7d..d4760583cbfc2 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -178,6 +178,7 @@ ; CHECK-NEXT: smepmp - 'Smepmp' (Enhanced Physical Memory Protection). ; CHECK-NEXT: smmpm - 'Smmpm' (Machine-level Pointer Masking for M-mode). ; CHECK-NEXT: smnpm - 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode). +; CHECK-NEXT: smpmpdeleg - 'Smpmpdeleg' (Sharing Hardware Resources between PMP and SPMP). ; CHECK-NEXT: smrnmi - 'Smrnmi' (Resumable Non-Maskable Interrupts). ; CHECK-NEXT: smstateen - 'Smstateen' (Machine-mode view of the state-enable extension). ; CHECK-NEXT: ssaia - 'Ssaia' (Advanced Interrupt Architecture Supervisor Level). @@ -190,6 +191,8 @@ ; CHECK-NEXT: ssdbltrp - 'Ssdbltrp' (Double Trap Supervisor Level). ; CHECK-NEXT: ssnpm - 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode). ; CHECK-NEXT: sspm - 'Sspm' (Indicates Supervisor-mode Pointer Masking). +; CHECK-NEXT: sspmp - 'Sspmp' (S-level Physical Memory Protection (SPMP)). +; CHECK-NEXT: sspmpen - 'Sspmpen' (Optimizing Context Switching of SPMP Entries). ; CHECK-NEXT: ssqosid - 'Ssqosid' (Quality-of-Service (QoS) Identifiers). ; CHECK-NEXT: ssstateen - 'Ssstateen' (Supervisor-mode view of the state-enable extension). ; CHECK-NEXT: ssstrict - 'Ssstrict' (No non-conforming extensions are present). diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index f802e91b312b4..9dce2eae37a41 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -381,6 +381,9 @@ .attribute arch, "rv32i_ssip0p20" # CHECK: attribute 5, "rv32i2p1_ssip0p20" +.attribute arch, "rv32i_smpmpdeleg1p0" +# CHECK: attribute 5, "rv32i2p1_smcsrind1p0_smpmpdeleg1p0_sscsrind1p0_sspmp1p0" + .attribute arch, "rv32i_smpmpmt0p6" # CHECK: attribute 5, "rv32i2p1_smpmpmt0p6" @@ -399,6 +402,12 @@ .attribute arch, "rv32i_sscounterenw1p0" # CHECK: attribute 5, "rv32i2p1_sscounterenw1p0" +.attribute arch, "rv32i_sspmp1p0" +# CHECK: attribute 5, "rv32i2p1_sscsrind1p0_sspmp1p0" + +.attribute arch, "rv32i_sspmpen1p0" +# CHECK: attribute 5, "rv32i2p1_sscsrind1p0_sspmp1p0_sspmpen1p0" + .attribute arch, "rv32i_ssqosid1p0" # CHECK: attribute 5, "rv32i2p1_ssqosid1p0" diff --git a/llvm/test/MC/RISCV/spmp-csr-names.s b/llvm/test/MC/RISCV/spmp-csr-names.s new file mode 100644 index 0000000000000..fb6bce657b351 --- /dev/null +++ b/llvm/test/MC/RISCV/spmp-csr-names.s @@ -0,0 +1,50 @@ +# RUN: llvm-mc %s -triple=riscv32 -M no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s +# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ +# RUN: | llvm-objdump -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s +# RUN: llvm-mc %s -triple=riscv64 -M no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s +# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ +# RUN: | llvm-objdump -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s +# RUN: llvm-mc %s -triple=riscv32 -defsym=RV32=1 -M no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=RV32-INST,RV32-ENC %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -defsym=RV32=1 < %s \ +# RUN: | llvm-objdump -d - \ +# RUN: | FileCheck -check-prefix=RV32-ALIAS %s +# RUN: not llvm-mc %s -triple=riscv64 -defsym=RV32=1 2>&1 \ +# RUN: | FileCheck -check-prefix=CHECK-RV64-ERR %s + +# spmpen +# CHECK-INST: csrrs t1, spmpen, zero +# CHECK-ENC: encoding: [0x73,0x23,0x30,0x18] +# CHECK-INST-ALIAS: csrr t1, spmpen +# CHECK-INST: csrrs t2, spmpen, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x18] +# CHECK-INST-ALIAS: csrr t2, spmpen +csrrs t1, spmpen, zero +csrrs t2, 0x183, zero + +# mpmpdeleg +# CHECK-INST: csrrs t1, mpmpdeleg, zero +# CHECK-ENC: encoding: [0x73,0x23,0x60,0x31] +# CHECK-INST-ALIAS: csrr t1, mpmpdeleg +# CHECK-INST: csrrs t2, mpmpdeleg, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x31] +# CHECK-INST-ALIAS: csrr t2, mpmpdeleg +csrrs t1, mpmpdeleg, zero +csrrs t2, 0x316, zero + +.ifdef RV32 +# spmpenh +# RV32-INST: csrrs t1, spmpenh, zero +# RV32-ENC: encoding: [0x73,0x23,0x30,0x19] +# RV32-ALIAS: csrr t1, spmpenh +# RV32-INST: csrrs t2, spmpenh, zero +# RV32-ENC: encoding: [0xf3,0x23,0x30,0x19] +# RV32-ALIAS: csrr t2, spmpenh +# CHECK-RV64-ERR: error: system register 'spmpenh' is RV32 only +csrrs t1, spmpenh, zero +csrrs t2, 0x193, zero +.endif diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 60a464d1bce2f..6abd70c1f0f32 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1526,6 +1526,7 @@ R"(All available -march extensions for RISC-V smepmp 1.0 smmpm 1.0 smnpm 1.0 + smpmpdeleg 1.0 smrnmi 1.0 smstateen 1.0 ssaia 1.0 @@ -1538,6 +1539,8 @@ R"(All available -march extensions for RISC-V ssdbltrp 1.0 ssnpm 1.0 sspm 1.0 + sspmp 1.0 + sspmpen 1.0 ssqosid 1.0 ssstateen 1.0 ssstrict 1.0 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
