https://github.com/XChy updated https://github.com/llvm/llvm-project/pull/223931
>From 80046b48a09aa45880e8b8d7efc8a161c15778a2 Mon Sep 17 00:00:00 2001 From: XChy <[email protected]> Date: Wed, 16 Sep 2026 15:19:43 +0800 Subject: [PATCH 1/2] [RISCV][P-ext] Support Packed Element Join --- clang/lib/Headers/riscv_packed_simd.h | 26 +++ clang/test/CodeGen/RISCV/rvp-intrinsics.c | 182 ++++++++++++++++++ .../riscv_packed_simd.c | 64 ++++++ 3 files changed, 272 insertions(+) diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h index 8c70a0e70b8a0..a02150066ea51 100644 --- a/clang/lib/Headers/riscv_packed_simd.h +++ b/clang/lib/Headers/riscv_packed_simd.h @@ -335,6 +335,18 @@ typedef uint32_t uint32x2_t __attribute__((__vector_size__(8))); return __v; \ } +#define __packed_join2(name, ty, elt_ty) \ + static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(elt_ty __e0, \ + elt_ty __e1) { \ + return (ty){__e0, __e1}; \ + } + +#define __packed_join4(name, ty, elt_ty) \ + static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name( \ + elt_ty __e0, elt_ty __e1, elt_ty __e2, elt_ty __e3) { \ + return (ty){__e0, __e1, __e2, __e3}; \ + } + // clang-format off: macro call sites have no trailing semicolons, which // confuses clang-format into a deeply nested expression. @@ -602,6 +614,18 @@ __packed_insert(pset_u16_u16x4, uint16x4_t, uint16_t, 3) __packed_insert(pset_i32_i32x2, int32x2_t, int32_t, 1) __packed_insert(pset_u32_u32x2, uint32x2_t, uint32_t, 1) +/* Packed Element Join (32-bit) */ +__packed_join4(pjoin4_i8x4, int8x4_t, int8_t) +__packed_join4(pjoin4_u8x4, uint8x4_t, uint8_t) +__packed_join2(pjoin2_i16x2, int16x2_t, int16_t) +__packed_join2(pjoin2_u16x2, uint16x2_t, uint16_t) + +/* Packed Element Join (64-bit) */ +__packed_join4(pjoin4_i16x4, int16x4_t, int16_t) +__packed_join4(pjoin4_u16x4, uint16x4_t, uint16_t) +__packed_join2(pjoin2_i32x2, int32x2_t, int32_t) +__packed_join2(pjoin2_u32x2, uint32x2_t, uint32_t) + /* Packed Logical Operations (32-bit) */ __packed_binary_op(pand_i8x4, int8x4_t, &) __packed_binary_op(pand_u8x4, uint8x4_t, &) @@ -1249,6 +1273,8 @@ __packed_reinterpret(u32x2_i32x2, int32x2_t, uint32x2_t) #undef __packed_ternary_builtin_cast #undef __packed_extract #undef __packed_insert +#undef __packed_join2 +#undef __packed_join4 #undef __packed_reinterpret #undef __DEFAULT_FN_ATTRS diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c index b7c1f07330ff2..34ce19b84f62e 100644 --- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c +++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c @@ -11392,3 +11392,185 @@ int32x2_t test_pset_i32_i32x2(int32x2_t v, int32_t e) { uint32x2_t test_pset_u32_u32x2(uint32x2_t v, uint32_t e) { return __riscv_pset_u32_u32x2(v, e, 0); } + +/* Packed Element Join (32-bit) */ + +// RV32-LABEL: define dso_local i32 @test_pjoin4_i8x4( +// RV32-SAME: i8 noundef signext [[E0:%.*]], i8 noundef signext [[E1:%.*]], i8 noundef signext [[E2:%.*]], i8 noundef signext [[E3:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[E0]], i64 0 +// RV32-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i8> [[VECINIT_I]], i8 [[E1]], i64 1 +// RV32-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i8> [[VECINIT1_I]], i8 [[E2]], i64 2 +// RV32-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i8> [[VECINIT2_I]], i8 [[E3]], i64 3 +// RV32-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32 +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pjoin4_i8x4( +// RV64-SAME: i8 noundef signext [[E0:%.*]], i8 noundef signext [[E1:%.*]], i8 noundef signext [[E2:%.*]], i8 noundef signext [[E3:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[E0]], i64 0 +// RV64-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i8> [[VECINIT_I]], i8 [[E1]], i64 1 +// RV64-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i8> [[VECINIT1_I]], i8 [[E2]], i64 2 +// RV64-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i8> [[VECINIT2_I]], i8 [[E3]], i64 3 +// RV64-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32 +// RV64-NEXT: ret i32 [[TMP0]] +// +int8x4_t test_pjoin4_i8x4(int8_t e0, int8_t e1, int8_t e2, int8_t e3) { + return __riscv_pjoin4_i8x4(e0, e1, e2, e3); +} + +// RV32-LABEL: define dso_local i32 @test_pjoin4_u8x4( +// RV32-SAME: i8 noundef zeroext [[E0:%.*]], i8 noundef zeroext [[E1:%.*]], i8 noundef zeroext [[E2:%.*]], i8 noundef zeroext [[E3:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[E0]], i64 0 +// RV32-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i8> [[VECINIT_I]], i8 [[E1]], i64 1 +// RV32-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i8> [[VECINIT1_I]], i8 [[E2]], i64 2 +// RV32-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i8> [[VECINIT2_I]], i8 [[E3]], i64 3 +// RV32-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32 +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pjoin4_u8x4( +// RV64-SAME: i8 noundef zeroext [[E0:%.*]], i8 noundef zeroext [[E1:%.*]], i8 noundef zeroext [[E2:%.*]], i8 noundef zeroext [[E3:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[E0]], i64 0 +// RV64-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i8> [[VECINIT_I]], i8 [[E1]], i64 1 +// RV64-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i8> [[VECINIT1_I]], i8 [[E2]], i64 2 +// RV64-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i8> [[VECINIT2_I]], i8 [[E3]], i64 3 +// RV64-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32 +// RV64-NEXT: ret i32 [[TMP0]] +// +uint8x4_t test_pjoin4_u8x4(uint8_t e0, uint8_t e1, uint8_t e2, uint8_t e3) { + return __riscv_pjoin4_u8x4(e0, e1, e2, e3); +} + +// RV32-LABEL: define dso_local i32 @test_pjoin2_i16x2( +// RV32-SAME: i16 noundef signext [[E0:%.*]], i16 noundef signext [[E1:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[E0]], i64 0 +// RV32-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i16> [[VECINIT_I]], i16 [[E1]], i64 1 +// RV32-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32 +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pjoin2_i16x2( +// RV64-SAME: i16 noundef signext [[E0:%.*]], i16 noundef signext [[E1:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[E0]], i64 0 +// RV64-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i16> [[VECINIT_I]], i16 [[E1]], i64 1 +// RV64-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32 +// RV64-NEXT: ret i32 [[TMP0]] +// +int16x2_t test_pjoin2_i16x2(int16_t e0, int16_t e1) { + return __riscv_pjoin2_i16x2(e0, e1); +} + +// RV32-LABEL: define dso_local i32 @test_pjoin2_u16x2( +// RV32-SAME: i16 noundef zeroext [[E0:%.*]], i16 noundef zeroext [[E1:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[E0]], i64 0 +// RV32-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i16> [[VECINIT_I]], i16 [[E1]], i64 1 +// RV32-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32 +// RV32-NEXT: ret i32 [[TMP0]] +// +// RV64-LABEL: define dso_local i32 @test_pjoin2_u16x2( +// RV64-SAME: i16 noundef zeroext [[E0:%.*]], i16 noundef zeroext [[E1:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[E0]], i64 0 +// RV64-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i16> [[VECINIT_I]], i16 [[E1]], i64 1 +// RV64-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32 +// RV64-NEXT: ret i32 [[TMP0]] +// +uint16x2_t test_pjoin2_u16x2(uint16_t e0, uint16_t e1) { + return __riscv_pjoin2_u16x2(e0, e1); +} + +/* Packed Element Join (64-bit) */ + +// RV32-LABEL: define dso_local i64 @test_pjoin4_i16x4( +// RV32-SAME: i16 noundef signext [[E0:%.*]], i16 noundef signext [[E1:%.*]], i16 noundef signext [[E2:%.*]], i16 noundef signext [[E3:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[E0]], i64 0 +// RV32-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[E1]], i64 1 +// RV32-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[E2]], i64 2 +// RV32-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[E3]], i64 3 +// RV32-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64 +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pjoin4_i16x4( +// RV64-SAME: i16 noundef signext [[E0:%.*]], i16 noundef signext [[E1:%.*]], i16 noundef signext [[E2:%.*]], i16 noundef signext [[E3:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[E0]], i64 0 +// RV64-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[E1]], i64 1 +// RV64-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[E2]], i64 2 +// RV64-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[E3]], i64 3 +// RV64-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64 +// RV64-NEXT: ret i64 [[TMP0]] +// +int16x4_t test_pjoin4_i16x4(int16_t e0, int16_t e1, int16_t e2, + int16_t e3) { + return __riscv_pjoin4_i16x4(e0, e1, e2, e3); +} + +// RV32-LABEL: define dso_local i64 @test_pjoin4_u16x4( +// RV32-SAME: i16 noundef zeroext [[E0:%.*]], i16 noundef zeroext [[E1:%.*]], i16 noundef zeroext [[E2:%.*]], i16 noundef zeroext [[E3:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[E0]], i64 0 +// RV32-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[E1]], i64 1 +// RV32-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[E2]], i64 2 +// RV32-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[E3]], i64 3 +// RV32-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64 +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pjoin4_u16x4( +// RV64-SAME: i16 noundef zeroext [[E0:%.*]], i16 noundef zeroext [[E1:%.*]], i16 noundef zeroext [[E2:%.*]], i16 noundef zeroext [[E3:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[E0]], i64 0 +// RV64-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[E1]], i64 1 +// RV64-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[E2]], i64 2 +// RV64-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[E3]], i64 3 +// RV64-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64 +// RV64-NEXT: ret i64 [[TMP0]] +// +uint16x4_t test_pjoin4_u16x4(uint16_t e0, uint16_t e1, uint16_t e2, + uint16_t e3) { + return __riscv_pjoin4_u16x4(e0, e1, e2, e3); +} + +// RV32-LABEL: define dso_local i64 @test_pjoin2_i32x2( +// RV32-SAME: i32 noundef [[E0:%.*]], i32 noundef [[E1:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[E0]], i64 0 +// RV32-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[E1]], i64 1 +// RV32-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to i64 +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pjoin2_i32x2( +// RV64-SAME: i32 noundef signext [[E0:%.*]], i32 noundef signext [[E1:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[E0]], i64 0 +// RV64-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[E1]], i64 1 +// RV64-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to i64 +// RV64-NEXT: ret i64 [[TMP0]] +// +int32x2_t test_pjoin2_i32x2(int32_t e0, int32_t e1) { + return __riscv_pjoin2_i32x2(e0, e1); +} + +// RV32-LABEL: define dso_local i64 @test_pjoin2_u32x2( +// RV32-SAME: i32 noundef [[E0:%.*]], i32 noundef [[E1:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[E0]], i64 0 +// RV32-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[E1]], i64 1 +// RV32-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to i64 +// RV32-NEXT: ret i64 [[TMP0]] +// +// RV64-LABEL: define dso_local i64 @test_pjoin2_u32x2( +// RV64-SAME: i32 noundef signext [[E0:%.*]], i32 noundef signext [[E1:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[E0]], i64 0 +// RV64-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[E1]], i64 1 +// RV64-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to i64 +// RV64-NEXT: ret i64 [[TMP0]] +// +uint32x2_t test_pjoin2_u32x2(uint32_t e0, uint32_t e1) { + return __riscv_pjoin2_u32x2(e0, e1); +} diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c index 51d9c4b0fd986..1c14685f9bb02 100644 --- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c +++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c @@ -4591,3 +4591,67 @@ int32x2_t test_pset_i32_i32x2(int32x2_t v, int32_t e) { uint32x2_t test_pset_u32_u32x2(uint32x2_t v, uint32_t e) { return __riscv_pset_u32_u32x2(v, e, 0); } + +// CHECK-LABEL: test_pjoin4_i8x4: +// RV32: ppaire.db +// RV32: pack +// RV64: ppaire.b +// RV64: ppaire.h +int8x4_t test_pjoin4_i8x4(int8_t e0, int8_t e1, int8_t e2, int8_t e3) { + return __riscv_pjoin4_i8x4(e0, e1, e2, e3); +} + +// CHECK-LABEL: test_pjoin4_u8x4: +// RV32: ppaire.db +// RV32: pack +// RV64: ppaire.b +// RV64: ppaire.h +uint8x4_t test_pjoin4_u8x4(uint8_t e0, uint8_t e1, uint8_t e2, uint8_t e3) { + return __riscv_pjoin4_u8x4(e0, e1, e2, e3); +} + +// CHECK-LABEL: test_pjoin2_i16x2: +// RV32: pack +// RV64: ppaire.h +int16x2_t test_pjoin2_i16x2(int16_t e0, int16_t e1) { + return __riscv_pjoin2_i16x2(e0, e1); +} + +// CHECK-LABEL: test_pjoin2_u16x2: +// RV32: pack +// RV64: ppaire.h +uint16x2_t test_pjoin2_u16x2(uint16_t e0, uint16_t e1) { + return __riscv_pjoin2_u16x2(e0, e1); +} + +// CHECK-LABEL: test_pjoin4_i16x4: +// RV32-COUNT-2: pack +// RV64-COUNT-2: ppaire.h +// RV64: pack +int16x4_t test_pjoin4_i16x4(int16_t e0, int16_t e1, int16_t e2, + int16_t e3) { + return __riscv_pjoin4_i16x4(e0, e1, e2, e3); +} + +// CHECK-LABEL: test_pjoin4_u16x4: +// RV32-COUNT-2: pack +// RV64-COUNT-2: ppaire.h +// RV64: pack +uint16x4_t test_pjoin4_u16x4(uint16_t e0, uint16_t e1, uint16_t e2, + uint16_t e3) { + return __riscv_pjoin4_u16x4(e0, e1, e2, e3); +} + +// CHECK-LABEL: test_pjoin2_i32x2: +// RV32: ret +// RV64: pack +int32x2_t test_pjoin2_i32x2(int32_t e0, int32_t e1) { + return __riscv_pjoin2_i32x2(e0, e1); +} + +// CHECK-LABEL: test_pjoin2_u32x2: +// RV32: ret +// RV64: pack +uint32x2_t test_pjoin2_u32x2(uint32_t e0, uint32_t e1) { + return __riscv_pjoin2_u32x2(e0, e1); +} >From d14f3448ba9c0752055eb6938a666d2e1ac1d2f5 Mon Sep 17 00:00:00 2001 From: XChy <[email protected]> Date: Wed, 16 Sep 2026 19:25:10 +0800 Subject: [PATCH 2/2] format --- clang/lib/Headers/riscv_packed_simd.h | 4 ++-- .../intrinsic-header-tests/riscv_packed_simd.c | 3 +-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h index a02150066ea51..92320df12e988 100644 --- a/clang/lib/Headers/riscv_packed_simd.h +++ b/clang/lib/Headers/riscv_packed_simd.h @@ -343,8 +343,8 @@ typedef uint32_t uint32x2_t __attribute__((__vector_size__(8))); #define __packed_join4(name, ty, elt_ty) \ static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name( \ - elt_ty __e0, elt_ty __e1, elt_ty __e2, elt_ty __e3) { \ - return (ty){__e0, __e1, __e2, __e3}; \ + elt_ty __e0, elt_ty __e1, elt_ty __e2, elt_ty __e3) { \ + return (ty){__e0, __e1, __e2, __e3}; \ } // clang-format off: macro call sites have no trailing semicolons, which diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c index 1c14685f9bb02..0cb773dd21c33 100644 --- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c +++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c @@ -4628,8 +4628,7 @@ uint16x2_t test_pjoin2_u16x2(uint16_t e0, uint16_t e1) { // RV32-COUNT-2: pack // RV64-COUNT-2: ppaire.h // RV64: pack -int16x4_t test_pjoin4_i16x4(int16_t e0, int16_t e1, int16_t e2, - int16_t e3) { +int16x4_t test_pjoin4_i16x4(int16_t e0, int16_t e1, int16_t e2, int16_t e3) { return __riscv_pjoin4_i16x4(e0, e1, e2, e3); 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