================
@@ -1106,4 +1106,57 @@ def XUANTIE_C920V2 : RISCVProcessorModel<"xt-c920v2",
FeatureUnalignedScalarMem]),
[TuneVXRMPipelineFlush,
TunePostRAScheduler]>;
+
+def GAISLER_GR765 : RISCVProcessorModel<"gr765",
+ GR765Model,
+ [Feature64Bit,
+ FeatureStdExtI,
+ FeatureStdExtZifencei,
+ FeatureStdExtZicsr,
+ FeatureStdExtZicntr,
+ FeatureStdExtZihpm,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtH,
+ FeatureStdExtShlcofideleg,
+ FeatureStdExtSmaia,
+ FeatureStdExtSmcdeleg,
+ FeatureStdExtSmcntrpmf,
+ FeatureStdExtSmcsrind,
+ FeatureStdExtSsaia,
+ FeatureStdExtSmdbltrp,
+ FeatureStdExtSmepmp,
+ FeatureStdExtSmrnmi,
+ FeatureStdExtSmstateen,
+ FeatureStdExtSscofpmf,
+ FeatureStdExtSscsrind,
+ FeatureStdExtSsdbltrp,
+ FeatureStdExtSstc,
+ FeatureStdExtSvadu,
+ FeatureStdExtSvinval,
+ FeatureStdExtSvnapot,
+ FeatureStdExtSvpbmt,
+ FeatureStdExtSvrsw60t59b,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbc,
+ FeatureStdExtZbs,
+ FeatureStdExtZcb,
+ FeatureStdExtZcmop,
+ FeatureStdExtZfa,
+ FeatureStdExtZfbfmin,
+ FeatureStdExtZfh,
+ FeatureStdExtZfhmin,
----------------
mshockwave wrote:the spec only says RV64GCH + P, just want to double check if these should be here https://github.com/llvm/llvm-project/pull/225638 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
