================
@@ -0,0 +1,89 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -x hip -fclangir \
+// RUN: -fcuda-is-device -emit-cir %s -o %t.cir
+// RUN: FileCheck --check-prefix=CIR %s --input-file=%t.cir
+
+// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -x hip -fclangir \
+// RUN: -fcuda-is-device -emit-llvm %s -o %t-cir.ll
+// RUN: FileCheck --check-prefix=LLVM %s --input-file=%t-cir.ll
+
+// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -x hip \
+// RUN: -fcuda-is-device -emit-llvm %s -o %t.ll
+// RUN: FileCheck --check-prefix=OGCG %s --input-file=%t.ll
+
+// Test that AMDGPU builtins are available on AMDGCN-flavored SPIR-V.
+
+// FIXME: CIR doesn't propagate the 'contract' fast-math flag to LLVM IR yet,
+// so the LLVM check lines use call{{.*}} to tolerate the difference between
+// CIR (no flags) and classic codegen ('contract').
+
+// FIXME: CIR doesn't cast allocas to the generic address space yet, so the
+// LLVM output lacks the addrspacecast that classic codegen emits.
----------------
aobolensk wrote:
1. yes, already, CIRGenFPOptionsRAII already asserts
MissingFeatures::fastMathFlags
2. here I have added MissingFeatures::spirvDefaultIsGenericAddrSpace
https://github.com/llvm/llvm-project/pull/222018
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