https://github.com/lgirdwood created https://github.com/llvm/llvm-project/pull/228927
## Summary This PR adds processor model definitions and Clang target recognition for Intel Audio DSP (ADSP) architectures: * **`intel_tgl_adsp`**: Tiger Lake Audio DSP (cAVS 2.5 / Intel ACE 1.x) * **`intel_ace15_adsp`**: Meteor Lake / Arrow Lake Audio DSP (Intel ACE 1.5) * **`intel_ace30_adsp`**: Panther Lake Audio DSP (Intel ACE 3.0) * **`intel_ace40_adsp`**: Nova Lake Audio DSP (Intel ACE 4.0) Additionally, aliases (`intel_ace15_mtpm`, `intel_ace30_ptl`, `intel_ace40`) are provided for backward compatibility with existing command-line invocations in Sound Open Firmware (SOF) and Zephyr RTOS. --- ## Context & Motivation This patch is the foundational step of a structured upstreaming series aimed at enabling full Sound Open Firmware (SOF) and Zephyr RTOS support for Intel ADSP platforms on upstream LLVM: 1. **Unified Toolchain Architecture**: Currently, building firmware across the diverse Xtensa ADSP generations relies on a fragmented toolchain matrix (proprietary Cadence compilers, vendor GNU binutils/GAS forks, and GCC). Upstreaming these definitions and subsequent ABI/assembler enhancements enables developers to build both the Zephyr kernel and SOF audio DSP firmware with a **single, unified, upstream Clang/LLVM toolchain**. 2. **Foundation for HiFi DSP Intrinsics**: This processor groundwork prepares the target for subsequent patches in the series, which will introduce Windowed ABI optimizations, integrated assembler (IAS) relaxation, and Tensilica HiFi DSP architectural intrinsics. 3. **Enabling the Rust Ecosystem on Audio DSPs**: A primary long-term objective of standardizing and completing the LLVM Xtensa target upstream is to unlock first-class support for **Rust (`rustc`) on audio DSP cores**. Because the Rust compiler relies directly on upstream LLVM, landing these processor models and ABI capabilities is a necessary prerequisite to bringing modern, memory-safe systems programming to audio firmware. --- ## Implementation Details * **`llvm/lib/Target/Xtensa/XtensaProcessors.td`**: Defines the processor models using only subtarget features already merged upstream (`FeatureDensity`, `FeatureWindowed`, `FeatureBoolean`, `FeatureLoop`, `FeatureSEXT`, `FeatureNSA`, `FeatureMul16`, `FeatureMul32`, `FeatureMul32High`, `FeatureDiv32`, `FeatureS32C1I`, `FeatureSingleFloat`, `FeatureTHREADPTR`, etc.). This avoids any external dependencies on upcoming DSP coprocessor patches. * **`clang/lib/Basic/Targets/Xtensa.h`**: Adds the new processor names to `isValidCPUName` so Clang correctly accepts `-mcpu=intel_*` and passes the target CPU down to CodeGen. * **`llvm/test/CodeGen/Xtensa/cpus.ll`**: Adds regression test lines for each processor and alias, verifying that `llc` accepts the target CPU and generates correct windowed assembly. --- ## Testing * Verified that `llvm/test/CodeGen/Xtensa/cpus.ll` passes cleanly: ```bash $ llvm-lit -va llvm/test/CodeGen/Xtensa/cpus.ll llvm/test/CodeGen/Xtensa/cpus-invalid.ll PASS: LLVM :: CodeGen/Xtensa/cpus-invalid.ll (1 of 2) PASS: LLVM :: CodeGen/Xtensa/cpus.ll (2 of 2) ``` * Verified that Clang accepts `-mcpu=intel_ace30_adsp`, `-mcpu=intel_ace30_ptl`, `-mcpu=intel_tgl_adsp`, and passes `-target-cpu` to `-cc1`. >From cd1ea64031f7d82a79cdb1438ad9603bb5011992 Mon Sep 17 00:00:00 2001 From: Liam Girdwood <[email protected]> Date: Sun, 4 Oct 2026 18:18:25 +0100 Subject: [PATCH] [Xtensa][clang] Add Intel ADSP processor definitions Add processor definitions and Clang target recognition for Intel Audio DSP (ADSP) platforms used in Sound Open Firmware (SOF) and Zephyr: - intel_tgl_adsp: Tiger Lake Audio DSP (cAVS 2.5) - intel_ace15_adsp: Meteor Lake / Arrow Lake Audio DSP (ACE 1.5) - intel_ace30_adsp: Panther Lake Audio DSP (ACE 3.0) - intel_ace40_adsp: Nova Lake Audio DSP (ACE 4.0) Also add platform/SoC aliases (intel_ace15_mtpm, intel_ace30_ptl, intel_ace40) for command-line compatibility with existing Zephyr and SOF configurations. Update test/CodeGen/Xtensa/cpus.ll to verify codegen for the new targets. Signed-off-by: Liam Girdwood <[email protected]> --- clang/lib/Basic/Targets/Xtensa.h | 12 ++++- llvm/lib/Target/Xtensa/XtensaProcessors.td | 59 ++++++++++++++++++++++ llvm/test/CodeGen/Xtensa/cpus.ll | 12 +++++ 3 files changed, 82 insertions(+), 1 deletion(-) diff --git a/clang/lib/Basic/Targets/Xtensa.h b/clang/lib/Basic/Targets/Xtensa.h index fd76e38f797d2..a012b67770430 100644 --- a/clang/lib/Basic/Targets/Xtensa.h +++ b/clang/lib/Basic/Targets/Xtensa.h @@ -97,7 +97,17 @@ class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { } bool isValidCPUName(StringRef Name) const override { - return llvm::StringSwitch<bool>(Name).Case("generic", true).Default(false); + return llvm::StringSwitch<bool>(Name) + .Case("generic", true) + // Intel Audio DSP + .Case("intel_tgl_adsp", true) + .Case("intel_ace15_adsp", true) + .Case("intel_ace15_mtpm", true) + .Case("intel_ace30_adsp", true) + .Case("intel_ace30_ptl", true) + .Case("intel_ace40_adsp", true) + .Case("intel_ace40", true) + .Default(false); } bool setCPU(StringRef Name) override { diff --git a/llvm/lib/Target/Xtensa/XtensaProcessors.td b/llvm/lib/Target/Xtensa/XtensaProcessors.td index b977de596762c..c0c1c5949ece8 100644 --- a/llvm/lib/Target/Xtensa/XtensaProcessors.td +++ b/llvm/lib/Target/Xtensa/XtensaProcessors.td @@ -30,3 +30,62 @@ def : Proc<"esp32s2", [FeatureDensity, FeatureWindowed, FeatureSEXT, FeatureNSA, FeatureDiv32, FeatureDataCache, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureHighPriInterruptsLevel7, FeatureCoprocessor, FeatureInterrupt, FeatureRelocatableVector, FeatureTimers3, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, FeatureMINMAX, FeatureCLAMPS, FeatureESP32S2Ops]>; + +//===----------------------------------------------------------------------===// +// Intel Audio DSP processors +//===----------------------------------------------------------------------===// + +// intel_tgl_adsp - Tiger Lake Audio DSP (cAVS 2.5) +def : Proc<"intel_tgl_adsp", [FeatureDensity, FeatureWindowed, FeatureBoolean, FeatureLoop, FeatureSEXT, + FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDiv32, + FeatureS32C1I, FeatureSingleFloat, + FeatureTHREADPTR, FeatureDebug, FeatureException, FeatureHighPriInterrupts, + FeatureHighPriInterruptsLevel7, FeatureCoprocessor, FeatureInterrupt, + FeatureDataCache, FeatureRelocatableVector, FeatureTimers3, FeaturePRID, + FeatureRegionProtection, FeatureMINMAX, FeatureCLAMPS]>; + +// intel_ace15_adsp - ACE 1.5 Audio DSP (MTL / ARL) +// Note: FeatureSingleFloat intentionally omitted for GNU as compatibility +def : Proc<"intel_ace15_adsp", [FeatureDensity, FeatureWindowed, FeatureBoolean, FeatureLoop, FeatureSEXT, + FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDiv32, FeatureS32C1I, + FeatureTHREADPTR, FeatureDebug, FeatureException, FeatureHighPriInterrupts, + FeatureHighPriInterruptsLevel5, FeatureCoprocessor, FeatureInterrupt, FeatureDataCache, + FeatureRelocatableVector, FeatureTimers1, FeaturePRID, + FeatureRegionProtection, FeatureMINMAX, FeatureCLAMPS]>; + +def : Proc<"intel_ace15_mtpm", [FeatureDensity, FeatureWindowed, FeatureBoolean, FeatureLoop, FeatureSEXT, + FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDiv32, FeatureS32C1I, + FeatureTHREADPTR, FeatureDebug, FeatureException, FeatureHighPriInterrupts, + FeatureHighPriInterruptsLevel5, FeatureCoprocessor, FeatureInterrupt, FeatureDataCache, + FeatureRelocatableVector, FeatureTimers1, FeaturePRID, + FeatureRegionProtection, FeatureMINMAX, FeatureCLAMPS, FeatureSingleFloat]>; + +// intel_ace30_adsp - ACE 3.0 Audio DSP (PTL) +def : Proc<"intel_ace30_adsp", [FeatureDensity, FeatureWindowed, FeatureBoolean, FeatureLoop, FeatureSEXT, + FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDiv32, FeatureS32C1I, + FeatureSingleFloat, FeatureTHREADPTR, FeatureDebug, FeatureException, FeatureHighPriInterrupts, + FeatureHighPriInterruptsLevel5, FeatureHighPriInterruptsLevel6, FeatureHighPriInterruptsLevel7, + FeatureCoprocessor, FeatureInterrupt, FeatureDataCache, FeatureRelocatableVector, FeatureTimers3, + FeaturePRID, FeatureRegionProtection, FeatureMiscSR, FeatureMINMAX, FeatureCLAMPS]>; + +def : Proc<"intel_ace30_ptl", [FeatureDensity, FeatureWindowed, FeatureBoolean, FeatureLoop, FeatureSEXT, + FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDiv32, FeatureS32C1I, + FeatureSingleFloat, FeatureTHREADPTR, FeatureDebug, FeatureException, FeatureHighPriInterrupts, + FeatureHighPriInterruptsLevel5, FeatureCoprocessor, FeatureInterrupt, FeatureDataCache, + FeatureRelocatableVector, FeatureTimers2, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, + FeatureMINMAX, FeatureCLAMPS]>; + +// intel_ace40_adsp - ACE 4.0 Audio DSP (NVL) +def : Proc<"intel_ace40_adsp", [FeatureDensity, FeatureWindowed, FeatureBoolean, FeatureLoop, FeatureSEXT, + FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDiv32, FeatureS32C1I, + FeatureSingleFloat, FeatureTHREADPTR, FeatureDebug, FeatureException, FeatureHighPriInterrupts, + FeatureHighPriInterruptsLevel5, FeatureCoprocessor, FeatureInterrupt, FeatureDataCache, + FeatureRelocatableVector, FeatureTimers2, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, + FeatureMINMAX, FeatureCLAMPS]>; + +def : Proc<"intel_ace40", [FeatureDensity, FeatureWindowed, FeatureBoolean, FeatureLoop, FeatureSEXT, + FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDiv32, FeatureS32C1I, + FeatureSingleFloat, FeatureTHREADPTR, FeatureDebug, FeatureException, FeatureHighPriInterrupts, + FeatureHighPriInterruptsLevel5, FeatureCoprocessor, FeatureInterrupt, FeatureDataCache, + FeatureRelocatableVector, FeatureTimers2, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, + FeatureMINMAX, FeatureCLAMPS]>; diff --git a/llvm/test/CodeGen/Xtensa/cpus.ll b/llvm/test/CodeGen/Xtensa/cpus.ll index 95ae845888e5c..3fe29da21f493 100644 --- a/llvm/test/CodeGen/Xtensa/cpus.ll +++ b/llvm/test/CodeGen/Xtensa/cpus.ll @@ -5,8 +5,20 @@ ; RUN: llc < %s --mtriple=xtensa --mcpu=esp32 2>&1 | FileCheck -check-prefix=XTENSA-ESP32 %s ; RUN: llc < %s --mtriple=xtensa --mcpu=esp32s2 2>&1 | FileCheck -check-prefix=XTENSA-ESP32S2 %s ; RUN: llc < %s --mtriple=xtensa --mcpu=generic 2>&1 | FileCheck -check-prefix=XTENSA-GENERIC %s +; RUN: llc < %s --mtriple=xtensa --mcpu=intel_tgl_adsp 2>&1 | FileCheck -check-prefix=XTENSA-INTEL-ADSP %s +; RUN: llc < %s --mtriple=xtensa --mcpu=intel_ace15_adsp 2>&1 | FileCheck -check-prefix=XTENSA-INTEL-ADSP %s +; RUN: llc < %s --mtriple=xtensa --mcpu=intel_ace30_ptl 2>&1 | FileCheck -check-prefix=XTENSA-INTEL-ADSP %s +; RUN: llc < %s --mtriple=xtensa --mcpu=intel_ace40 2>&1 | FileCheck -check-prefix=XTENSA-INTEL-ADSP %s define i32 @f(i32 %z) { +; XTENSA-INTEL-ADSP-LABEL: f: +; XTENSA-INTEL-ADSP: .cfi_startproc +; XTENSA-INTEL-ADSP-NEXT: # %bb.0: +; XTENSA-INTEL-ADSP-NEXT: entry a1, 32 +; XTENSA-INTEL-ADSP-NEXT: .cfi_def_cfa_offset 32 +; XTENSA-INTEL-ADSP-NEXT: movi a2, 0 +; XTENSA-INTEL-ADSP-NEXT: retw.n +; ; XTENSA-ESP8266-LABEL: f: ; XTENSA-ESP8266: .cfi_startproc ; XTENSA-ESP8266-NEXT: # %bb.0: _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
