https://github.com/bob80905 updated https://github.com/llvm/llvm-project/pull/227160
>From 257d06518c9b9fa1bc1801303148640f7d3d00aa Mon Sep 17 00:00:00 2001 From: Joshua Batista <[email protected]> Date: Mon, 28 Sep 2026 16:25:22 -0700 Subject: [PATCH 1/6] first attempt --- .../Target/SPIRV/SPIRVInstructionSelector.cpp | 1 + .../SPIRV/hlsl-intrinsics/WaveGetLaneCount.ll | 29 +++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneCount.ll diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index 143e1c0e3ef2ab..a81c1d6ad842dd 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -5541,6 +5541,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, return loadVec3BuiltinInputID(SPIRV::BuiltIn::NumWorkgroups, ResVReg, ResType, I); case Intrinsic::spv_subgroup_size: + case Intrinsic::spv_wave_get_lane_count: return loadBuiltinInputID(SPIRV::BuiltIn::SubgroupSize, ResVReg, ResType, I); case Intrinsic::spv_num_subgroups: diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneCount.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneCount.ll new file mode 100644 index 00000000000000..0c475340568185 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneCount.ll @@ -0,0 +1,29 @@ +; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %} + +target triple = "spirv-unknown-vulkan-compute" + +; CHECK-DAG: OpCapability Shader +; CHECK-DAG: OpCapability GroupNonUniform +; CHECK-DAG: OpDecorate %[[#var:]] BuiltIn SubgroupSize +; CHECK-DAG: %[[#uint:]] = OpTypeInt 32 0 +; CHECK-DAG: %[[#ptr:]] = OpTypePointer Input %[[#uint]] +; CHECK-DAG: %[[#var]] = OpVariable %[[#ptr]] Input + +; CHECK-NOT: OpDecorate %[[#var]] LinkageAttributes + +define spir_func i32 @test_fun() #0 { +entry: + %0 = call token @llvm.experimental.convergence.entry() +; CHECK: %[[#count:]] = OpLoad %[[#uint]] %[[#var]] + %1 = call i32 @llvm.spv.wave.get.lane.count() + [ "convergencectrl"(token %0) ] +; CHECK: OpReturnValue %[[#count]] + ret i32 %1 +} + +declare i32 @llvm.spv.wave.get.lane.count() #0 + +declare token @llvm.experimental.convergence.entry() + +attributes #0 = { convergent } >From 8ff8ddcaa67ff7a4d1e88a5f547ec1f8efa3a3e9 Mon Sep 17 00:00:00 2001 From: Joshua Batista <[email protected]> Date: Mon, 28 Sep 2026 16:41:05 -0700 Subject: [PATCH 2/6] drop check-not linkage attributes --- llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneCount.ll | 2 -- 1 file changed, 2 deletions(-) diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneCount.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneCount.ll index 0c475340568185..62247eb200632a 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneCount.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneCount.ll @@ -10,8 +10,6 @@ target triple = "spirv-unknown-vulkan-compute" ; CHECK-DAG: %[[#ptr:]] = OpTypePointer Input %[[#uint]] ; CHECK-DAG: %[[#var]] = OpVariable %[[#ptr]] Input -; CHECK-NOT: OpDecorate %[[#var]] LinkageAttributes - define spir_func i32 @test_fun() #0 { entry: %0 = call token @llvm.experimental.convergence.entry() >From 5336f587900ecf80c3057fe70c4c9c236ad707b4 Mon Sep 17 00:00:00 2001 From: Joshua Batista <[email protected]> Date: Tue, 29 Sep 2026 15:44:32 -0700 Subject: [PATCH 3/6] address Chris --- clang/lib/CodeGen/CGHLSLRuntime.h | 12 ++++++++- .../builtins/wave_get_lane_count.hlsl | 16 ++++------- llvm/include/llvm/IR/IntrinsicsSPIRV.td | 2 -- .../Target/SPIRV/SPIRVInstructionSelector.cpp | 1 - .../SPIRV/hlsl-intrinsics/WaveGetLaneCount.ll | 27 ------------------- 5 files changed, 16 insertions(+), 42 deletions(-) delete mode 100644 llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneCount.ll diff --git a/clang/lib/CodeGen/CGHLSLRuntime.h b/clang/lib/CodeGen/CGHLSLRuntime.h index 11b3e0220dcfba..801d9bfa404e35 100644 --- a/clang/lib/CodeGen/CGHLSLRuntime.h +++ b/clang/lib/CodeGen/CGHLSLRuntime.h @@ -152,7 +152,17 @@ class CGHLSLRuntime { GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveUMin, wave_reduce_umin) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveCountBits, wave_active_countbits) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane) - GENERATE_HLSL_INTRINSIC_FUNCTION(WaveGetLaneCount, wave_get_lane_count) + llvm::Intrinsic::ID getWaveGetLaneCountIntrinsic() { + switch (getArch()) { + case llvm::Triple::dxil: + return llvm::Intrinsic::dx_wave_get_lane_count; + case llvm::Triple::spirv: + return llvm::Intrinsic::spv_subgroup_size; + default: + llvm_unreachable( + "WaveGetLaneCount intrinsic not supported by target architecture"); + } + } GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, wave_readlane) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneFirst, wave_readlane_first) GENERATE_HLSL_INTRINSIC_FUNCTION(QuadReadAcrossX, quad_read_across_x) diff --git a/clang/test/CodeGenHLSL/builtins/wave_get_lane_count.hlsl b/clang/test/CodeGenHLSL/builtins/wave_get_lane_count.hlsl index fdf019262d8cb1..14e2ccebb1de52 100644 --- a/clang/test/CodeGenHLSL/builtins/wave_get_lane_count.hlsl +++ b/clang/test/CodeGenHLSL/builtins/wave_get_lane_count.hlsl @@ -1,32 +1,26 @@ // RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -x hlsl -triple \ // RUN: spirv-pc-vulkan-compute %s -emit-llvm -disable-llvm-passes -o - | \ -// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-SPIRV +// RUN: FileCheck %s --check-prefix=CHECK-SPIRV // RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -x hlsl -triple \ // RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o - | \ -// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL +// RUN: FileCheck %s --check-prefix=CHECK-DXIL [numthreads(1, 1, 1)] void main() { uint a, b; -// CHECK-SPIRV: %[[#entry_tok:]] = call token @llvm.experimental.convergence.entry() -// CHECK-SPIRV: %[[#loop_tok:]] = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %[[#entry_tok]]) ] while (a) { // CHECK-DXIL: %[[#]] = call i32 @llvm.dx.wave.get.lane.count() -// CHECK-SPIRV: %[[#]] = call i32 @llvm.spv.wave.get.lane.count() -// CHECK-SPIRV-SAME: [ "convergencectrl"(token %[[#loop_tok]]) ] +// CHECK-SPIRV: %[[#]] = call i32 @llvm.spv.subgroup.size() a = WaveGetLaneCount(); } // CHECK-DXIL: %[[#]] = call i32 @llvm.dx.wave.get.lane.count() -// CHECK-SPIRV: %[[#]] = call i32 @llvm.spv.wave.get.lane.count() -// CHECK-SPIRV-SAME: [ "convergencectrl"(token %[[#entry_tok]]) ] +// CHECK-SPIRV: %[[#]] = call i32 @llvm.spv.subgroup.size() b = WaveGetLaneCount(); } // CHECK-DXIL: i32 @llvm.dx.wave.get.lane.count() #[[#attr:]] -// CHECK-SPIRV: i32 @llvm.spv.wave.get.lane.count() #[[#attr:]] - -// CHECK: attributes #[[#attr]] = {{{.*}} convergent {{.*}}} +// CHECK-DXIL: attributes #[[#attr]] = {{{.*}} convergent {{.*}}} diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td index 25b5a3c3854654..e2ddbfe199e736 100644 --- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td +++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td @@ -157,8 +157,6 @@ def int_spv_rsqrt : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty] def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>; def int_spv_wave_readlane : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>; def int_spv_wave_readlane_first : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; - def int_spv_wave_get_lane_count - : DefaultAttrsIntrinsic<[llvm_i32_ty], [], [IntrConvergent]>; def int_spv_wave_prefix_sum : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_spv_wave_prefix_product : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_spv_quad_read_across_x : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index a81c1d6ad842dd..143e1c0e3ef2ab 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -5541,7 +5541,6 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, return loadVec3BuiltinInputID(SPIRV::BuiltIn::NumWorkgroups, ResVReg, ResType, I); case Intrinsic::spv_subgroup_size: - case Intrinsic::spv_wave_get_lane_count: return loadBuiltinInputID(SPIRV::BuiltIn::SubgroupSize, ResVReg, ResType, I); case Intrinsic::spv_num_subgroups: diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneCount.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneCount.ll deleted file mode 100644 index 62247eb200632a..00000000000000 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneCount.ll +++ /dev/null @@ -1,27 +0,0 @@ -; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %} - -target triple = "spirv-unknown-vulkan-compute" - -; CHECK-DAG: OpCapability Shader -; CHECK-DAG: OpCapability GroupNonUniform -; CHECK-DAG: OpDecorate %[[#var:]] BuiltIn SubgroupSize -; CHECK-DAG: %[[#uint:]] = OpTypeInt 32 0 -; CHECK-DAG: %[[#ptr:]] = OpTypePointer Input %[[#uint]] -; CHECK-DAG: %[[#var]] = OpVariable %[[#ptr]] Input - -define spir_func i32 @test_fun() #0 { -entry: - %0 = call token @llvm.experimental.convergence.entry() -; CHECK: %[[#count:]] = OpLoad %[[#uint]] %[[#var]] - %1 = call i32 @llvm.spv.wave.get.lane.count() - [ "convergencectrl"(token %0) ] -; CHECK: OpReturnValue %[[#count]] - ret i32 %1 -} - -declare i32 @llvm.spv.wave.get.lane.count() #0 - -declare token @llvm.experimental.convergence.entry() - -attributes #0 = { convergent } >From 46c52df8fc800e5b6b84eaa8a4e6590f1214a783 Mon Sep 17 00:00:00 2001 From: Joshua Batista <[email protected]> Date: Tue, 29 Sep 2026 15:55:32 -0700 Subject: [PATCH 4/6] move function placement --- clang/lib/CodeGen/CGHLSLBuiltins.cpp | 15 ++++++++++++++- clang/lib/CodeGen/CGHLSLRuntime.h | 11 ----------- 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/clang/lib/CodeGen/CGHLSLBuiltins.cpp b/clang/lib/CodeGen/CGHLSLBuiltins.cpp index e66912077924f5..0767961b32f374 100644 --- a/clang/lib/CodeGen/CGHLSLBuiltins.cpp +++ b/clang/lib/CodeGen/CGHLSLBuiltins.cpp @@ -421,6 +421,18 @@ static Intrinsic::ID getPrefixCountBitsIntrinsic(llvm::Triple::ArchType Arch) { } } +static Intrinsic::ID getWaveGetLaneCountIntrinsic(llvm::Triple::ArchType Arch) { + switch (Arch) { + case llvm::Triple::spirv: + return Intrinsic::spv_subgroup_size; + case llvm::Triple::dxil: + return Intrinsic::dx_wave_get_lane_count; + default: + llvm_unreachable("Intrinsic WaveGetLaneCount" + " not supported by target architecture"); + } +} + // Return wave prefix sum that corresponds to the QT scalar type static Intrinsic::ID getWavePrefixSumIntrinsic(llvm::Triple::ArchType Arch, QualType QT) { @@ -1550,7 +1562,8 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, return EmitIntrinsicCall(ID); } case Builtin::BI__builtin_hlsl_wave_get_lane_count: { - Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveGetLaneCountIntrinsic(); + Intrinsic::ID ID = + getWaveGetLaneCountIntrinsic(getTarget().getTriple().getArch()); return EmitIntrinsicCall(ID); } case Builtin::BI__builtin_hlsl_wave_read_lane_at: { diff --git a/clang/lib/CodeGen/CGHLSLRuntime.h b/clang/lib/CodeGen/CGHLSLRuntime.h index 801d9bfa404e35..47a246d5bae306 100644 --- a/clang/lib/CodeGen/CGHLSLRuntime.h +++ b/clang/lib/CodeGen/CGHLSLRuntime.h @@ -152,17 +152,6 @@ class CGHLSLRuntime { GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveUMin, wave_reduce_umin) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveCountBits, wave_active_countbits) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane) - llvm::Intrinsic::ID getWaveGetLaneCountIntrinsic() { - switch (getArch()) { - case llvm::Triple::dxil: - return llvm::Intrinsic::dx_wave_get_lane_count; - case llvm::Triple::spirv: - return llvm::Intrinsic::spv_subgroup_size; - default: - llvm_unreachable( - "WaveGetLaneCount intrinsic not supported by target architecture"); - } - } GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, wave_readlane) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneFirst, wave_readlane_first) GENERATE_HLSL_INTRINSIC_FUNCTION(QuadReadAcrossX, quad_read_across_x) >From 7f26dd4f6b54ad80d58ef1f121f26b5121c16c57 Mon Sep 17 00:00:00 2001 From: Joshua Batista <[email protected]> Date: Wed, 30 Sep 2026 15:23:19 -0700 Subject: [PATCH 5/6] add new macro to handle differing spirv intrinsic names --- clang/lib/CodeGen/CGHLSLBuiltins.cpp | 15 +------------ clang/lib/CodeGen/CGHLSLRuntime.h | 33 +++++++++++++++++++++++++--- 2 files changed, 31 insertions(+), 17 deletions(-) diff --git a/clang/lib/CodeGen/CGHLSLBuiltins.cpp b/clang/lib/CodeGen/CGHLSLBuiltins.cpp index 0767961b32f374..e66912077924f5 100644 --- a/clang/lib/CodeGen/CGHLSLBuiltins.cpp +++ b/clang/lib/CodeGen/CGHLSLBuiltins.cpp @@ -421,18 +421,6 @@ static Intrinsic::ID getPrefixCountBitsIntrinsic(llvm::Triple::ArchType Arch) { } } -static Intrinsic::ID getWaveGetLaneCountIntrinsic(llvm::Triple::ArchType Arch) { - switch (Arch) { - case llvm::Triple::spirv: - return Intrinsic::spv_subgroup_size; - case llvm::Triple::dxil: - return Intrinsic::dx_wave_get_lane_count; - default: - llvm_unreachable("Intrinsic WaveGetLaneCount" - " not supported by target architecture"); - } -} - // Return wave prefix sum that corresponds to the QT scalar type static Intrinsic::ID getWavePrefixSumIntrinsic(llvm::Triple::ArchType Arch, QualType QT) { @@ -1562,8 +1550,7 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, return EmitIntrinsicCall(ID); } case Builtin::BI__builtin_hlsl_wave_get_lane_count: { - Intrinsic::ID ID = - getWaveGetLaneCountIntrinsic(getTarget().getTriple().getArch()); + Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveGetLaneCountIntrinsic(); return EmitIntrinsicCall(ID); } case Builtin::BI__builtin_hlsl_wave_read_lane_at: { diff --git a/clang/lib/CodeGen/CGHLSLRuntime.h b/clang/lib/CodeGen/CGHLSLRuntime.h index 47a246d5bae306..0d319d3d1eb9e4 100644 --- a/clang/lib/CodeGen/CGHLSLRuntime.h +++ b/clang/lib/CodeGen/CGHLSLRuntime.h @@ -33,9 +33,18 @@ #include <optional> #include <vector> -// A function generator macro for picking the right intrinsic -// for the target backend -#define GENERATE_HLSL_INTRINSIC_FUNCTION(FunctionName, IntrinsicPostfix) \ +// Function generator macros for picking the right intrinsic +// for the target backend. +#define _GEN_INTRIN_CHOOSER(_1, _2, _3, NAME, ...) NAME + +#define GENERATE_HLSL_INTRINSIC_FUNCTION(...) \ + _GEN_INTRIN_CHOOSER(__VA_ARGS__, GENERATE_HLSL_INTRINSIC_FUNCTION3, \ + GENERATE_HLSL_INTRINSIC_FUNCTION2, \ + /* dummy to solve pre-C++20 errors */ ignored)( \ + __VA_ARGS__) + +// 2-arg form: same postfix for both backends (uses the identity) +#define GENERATE_HLSL_INTRINSIC_FUNCTION2(FunctionName, IntrinsicPostfix) \ llvm::Intrinsic::ID get##FunctionName##Intrinsic() { \ llvm::Triple::ArchType Arch = getArch(); \ switch (Arch) { \ @@ -49,6 +58,22 @@ } \ } +// 3-arg form: explicit SPIR-V postfix override (perfect for wave->subgroup) +#define GENERATE_HLSL_INTRINSIC_FUNCTION3(FunctionName, DxilPostfix, \ + SpirvPostfix) \ + llvm::Intrinsic::ID get##FunctionName##Intrinsic() { \ + llvm::Triple::ArchType Arch = getArch(); \ + switch (Arch) { \ + case llvm::Triple::dxil: \ + return llvm::Intrinsic::dx_##DxilPostfix; \ + case llvm::Triple::spirv: \ + return llvm::Intrinsic::spv_##SpirvPostfix; \ + default: \ + llvm_unreachable("Intrinsic " #DxilPostfix \ + " not supported by target architecture"); \ + } \ + } + using ResourceClass = llvm::dxil::ResourceClass; namespace llvm { @@ -152,6 +177,8 @@ class CGHLSLRuntime { GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveUMin, wave_reduce_umin) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveCountBits, wave_active_countbits) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane) + GENERATE_HLSL_INTRINSIC_FUNCTION(WaveGetLaneCount, wave_get_lane_count, + subgroup_size) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, wave_readlane) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneFirst, wave_readlane_first) GENERATE_HLSL_INTRINSIC_FUNCTION(QuadReadAcrossX, quad_read_across_x) >From 742f1af543759dcb8d623ce33f354c59d5f2c2c4 Mon Sep 17 00:00:00 2001 From: Joshua Batista <[email protected]> Date: Thu, 1 Oct 2026 16:33:32 -0700 Subject: [PATCH 6/6] address Deric --- clang/lib/CodeGen/CGHLSLRuntime.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/clang/lib/CodeGen/CGHLSLRuntime.h b/clang/lib/CodeGen/CGHLSLRuntime.h index 0d319d3d1eb9e4..80230050390c7d 100644 --- a/clang/lib/CodeGen/CGHLSLRuntime.h +++ b/clang/lib/CodeGen/CGHLSLRuntime.h @@ -35,13 +35,13 @@ // Function generator macros for picking the right intrinsic // for the target backend. -#define _GEN_INTRIN_CHOOSER(_1, _2, _3, NAME, ...) NAME +#define HLSL_INTRINSIC_FUNCTION_CHOOSER(_1, _2, _3, NAME, ...) NAME #define GENERATE_HLSL_INTRINSIC_FUNCTION(...) \ - _GEN_INTRIN_CHOOSER(__VA_ARGS__, GENERATE_HLSL_INTRINSIC_FUNCTION3, \ - GENERATE_HLSL_INTRINSIC_FUNCTION2, \ - /* dummy to solve pre-C++20 errors */ ignored)( \ - __VA_ARGS__) + HLSL_INTRINSIC_FUNCTION_CHOOSER( \ + __VA_ARGS__, GENERATE_HLSL_INTRINSIC_FUNCTION3, \ + GENERATE_HLSL_INTRINSIC_FUNCTION2, \ + /* dummy to solve pre-C++20 errors */ ignored)(__VA_ARGS__) // 2-arg form: same postfix for both backends (uses the identity) #define GENERATE_HLSL_INTRINSIC_FUNCTION2(FunctionName, IntrinsicPostfix) \ _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
