llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Aaditya (easyonaadit) <details> <summary>Changes</summary> The OpenCL/HIP specification marks atomics on thread private memory as UB. Scoped atomics used within a HIP context should also be considered UB, unless explicitly specified via a command line argument. These are now annotated with !noalias.addrspace(5) for amdgpus, to avoid an expensive runtime check. --- Patch is 94.38 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/230044.diff 8 Files Affected: - (modified) clang/include/clang/AST/Expr.h (+3-4) - (modified) clang/include/clang/Basic/LangOptions.def (+1) - (modified) clang/include/clang/Basic/LangOptions.h (+1-1) - (modified) clang/include/clang/Options/Options.td (+6) - (modified) clang/lib/CodeGen/Targets/AMDGPU.cpp (+7-1) - (modified) clang/test/CodeGen/scoped-atomic-ops.c (+76-75) - (modified) clang/test/CodeGenCUDA/atomic-options.hip (+22-20) - (added) clang/test/CodeGenCUDA/private-atomics-undefined.hip (+27) ``````````diff diff --git a/clang/include/clang/AST/Expr.h b/clang/include/clang/AST/Expr.h index a0324240ce34da..5642f26e0c50b0 100644 --- a/clang/include/clang/AST/Expr.h +++ b/clang/include/clang/AST/Expr.h @@ -7097,10 +7097,9 @@ class AtomicExpr : public Expr { Op <= AO__hip_atomic_store; } - /// Return true if atomics operations targeting allocations in private memory - /// are undefined. - bool threadPrivateMemoryAtomicsAreUndefined() const { - return isOpenCL() || isHIP(); + bool isScopedAtomic() const { + return getOp() >= AO__scoped_atomic_add_fetch && + getOp() <= AO__scoped_atomic_xor_fetch; } SourceLocation getBuiltinLoc() const { return BuiltinLoc; } diff --git a/clang/include/clang/Basic/LangOptions.def b/clang/include/clang/Basic/LangOptions.def index e0c29f7b0d791f..37db4f6039dabf 100644 --- a/clang/include/clang/Basic/LangOptions.def +++ b/clang/include/clang/Basic/LangOptions.def @@ -266,6 +266,7 @@ LANGOPT(GPUDeferDiag, 1, 0, NotCompatible, "defer host/device related diagnostic LANGOPT(GPUExcludeWrongSideOverloads, 1, 0, NotCompatible, "always exclude wrong side overloads in overloading resolution for CUDA/HIP") LANGOPT(OffloadViaLLVM, 1, 0, NotCompatible, "target LLVM/Offload as portable offloading runtime.") LANGOPT(CUDANVCCABI, 1, 0, NotCompatible, "emit the NVCC-compatible host registration ABI for CUDA") +LANGOPT(PrivateAtomicsUndefined, 1, 0, NotCompatible, "atomics on thread private memory are undefined behavior") LANGOPT(SYCLIsDevice , 1, 0, NotCompatible, "Generate code for SYCL device") LANGOPT(SYCLIsHost , 1, 0, NotCompatible, "SYCL host compilation") diff --git a/clang/include/clang/Basic/LangOptions.h b/clang/include/clang/Basic/LangOptions.h index 7539e000d03f98..526960bcc44647 100644 --- a/clang/include/clang/Basic/LangOptions.h +++ b/clang/include/clang/Basic/LangOptions.h @@ -715,7 +715,7 @@ class LangOptions : public LangOptionsBase { bool threadPrivateMemoryAtomicsAreUndefined() const { // Should be false for OpenMP. // TODO: Should this be true for SYCL? - return OpenCL || CUDA; + return PrivateAtomicsUndefined; } /// Return the OpenCL C or C++ version as a VersionTuple. diff --git a/clang/include/clang/Options/Options.td b/clang/include/clang/Options/Options.td index f3e50f90835327..93e27d3ab35e3c 100644 --- a/clang/include/clang/Options/Options.td +++ b/clang/include/clang/Options/Options.td @@ -1154,6 +1154,12 @@ defm offload_uniform_block : BoolFOption<"offload-uniform-block", NegFlag<SetFalse, [], [ClangOption, CC1Option], "Don't assume">, BothFlags<[], [ClangOption], " that kernels are launched with uniform block sizes (default true for CUDA/HIP and false otherwise)">>; +defm private_atomics_undefined : BoolFOption<"private-atomics-undefined", + LangOpts<"PrivateAtomicsUndefined">, Default<"LangOpts->CUDA || LangOpts->OpenCL">, + PosFlag<SetTrue, [], [ClangOption, CC1Option], "Assume">, + NegFlag<SetFalse, [], [ClangOption, CC1Option], "Don't assume">, + BothFlags<[], [ClangOption], " that atomics on thread private memory are undefined behavior (default true for HIP/OpenCL)">>; + def fcomplex_arithmetic_EQ : Joined<["-"], "fcomplex-arithmetic=">, Group<f_Group>, Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>, Values<"full,improved,promoted,basic">, NormalizedValuesScope<"LangOptions">, diff --git a/clang/lib/CodeGen/Targets/AMDGPU.cpp b/clang/lib/CodeGen/Targets/AMDGPU.cpp index 0b5ed1898f1389..13dcf7262b7a7c 100644 --- a/clang/lib/CodeGen/Targets/AMDGPU.cpp +++ b/clang/lib/CodeGen/Targets/AMDGPU.cpp @@ -556,13 +556,19 @@ void AMDGPUTargetCodeGenInfo::setTargetAtomicMetadata( // OpenCL and old style HIP atomics consider atomics targeting thread private // memory to be undefined. + // Scoped atomics targeting private memory, when used within a HIP context, + // are considered UB, unless explicitely opted in by the user via a command + // line flag(-f[no-]private-atomics-undefined). // // TODO: This is probably undefined for atomic load/store, but there's not // much direct codegen benefit to knowing this. if (((RMW && RMW->getPointerAddressSpace() == llvm::AMDGPUAS::FLAT_ADDRESS) || (CmpX && CmpX->getPointerAddressSpace() == llvm::AMDGPUAS::FLAT_ADDRESS)) && - AE && AE->threadPrivateMemoryAtomicsAreUndefined()) { + AE && + (AE->isOpenCL() || AE->isHIP() || + (AE->isScopedAtomic() && + CGF.getLangOpts().threadPrivateMemoryAtomicsAreUndefined()))) { llvm::MDBuilder MDHelper(CGF.getLLVMContext()); llvm::MDNode *ASRange = MDHelper.createRange( llvm::APInt(32, llvm::AMDGPUAS::PRIVATE_ADDRESS), diff --git a/clang/test/CodeGen/scoped-atomic-ops.c b/clang/test/CodeGen/scoped-atomic-ops.c index d0feb389256826..2682da9fd25661 100644 --- a/clang/test/CodeGen/scoped-atomic-ops.c +++ b/clang/test/CodeGen/scoped-atomic-ops.c @@ -775,7 +775,7 @@ void fi2b(int *i) { // AMDGCN_CL_20-NEXT: [[TMP0:%.*]] = load ptr, ptr addrspace(5) [[A_ADDR]], align 8 // AMDGCN_CL_20-NEXT: store i32 1, ptr addrspace(5) [[DOTATOMICTMP]], align 4 // AMDGCN_CL_20-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[DOTATOMICTMP]], align 4 -// AMDGCN_CL_20-NEXT: [[TMP2:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP1]] monotonic, align 4, !amdgpu.no.fine.grained.memory [[META3:![0-9]+]], !amdgpu.no.remote.memory [[META3]] +// AMDGCN_CL_20-NEXT: [[TMP2:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP1]] monotonic, align 4, !noalias.addrspace [[META3:![0-9]+]], !amdgpu.no.fine.grained.memory [[META4:![0-9]+]], !amdgpu.no.remote.memory [[META4]] // AMDGCN_CL_20-NEXT: store i32 [[TMP2]], ptr addrspace(5) [[ATOMIC_TEMP]], align 4 // AMDGCN_CL_20-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(5) [[ATOMIC_TEMP]], align 4 // AMDGCN_CL_20-NEXT: [[TMP4:%.*]] = load ptr, ptr addrspace(5) [[A_ADDR]], align 8 @@ -783,7 +783,7 @@ void fi2b(int *i) { // AMDGCN_CL_20-NEXT: [[TMP5:%.*]] = load ptr, ptr addrspace(5) [[B_ADDR]], align 8 // AMDGCN_CL_20-NEXT: store i32 1, ptr addrspace(5) [[DOTATOMICTMP1]], align 4 // AMDGCN_CL_20-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(5) [[DOTATOMICTMP1]], align 4 -// AMDGCN_CL_20-NEXT: [[TMP7:%.*]] = atomicrmw sub ptr [[TMP5]], i32 [[TMP6]] monotonic, align 4, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] +// AMDGCN_CL_20-NEXT: [[TMP7:%.*]] = atomicrmw sub ptr [[TMP5]], i32 [[TMP6]] monotonic, align 4, !noalias.addrspace [[META3]], !amdgpu.no.fine.grained.memory [[META4]], !amdgpu.no.remote.memory [[META4]] // AMDGCN_CL_20-NEXT: store i32 [[TMP7]], ptr addrspace(5) [[ATOMIC_TEMP2]], align 4 // AMDGCN_CL_20-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(5) [[ATOMIC_TEMP2]], align 4 // AMDGCN_CL_20-NEXT: [[TMP9:%.*]] = load ptr, ptr addrspace(5) [[B_ADDR]], align 8 @@ -791,7 +791,7 @@ void fi2b(int *i) { // AMDGCN_CL_20-NEXT: [[TMP10:%.*]] = load ptr, ptr addrspace(5) [[C_ADDR]], align 8 // AMDGCN_CL_20-NEXT: store i32 1, ptr addrspace(5) [[DOTATOMICTMP3]], align 4 // AMDGCN_CL_20-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(5) [[DOTATOMICTMP3]], align 4 -// AMDGCN_CL_20-NEXT: [[TMP12:%.*]] = atomicrmw and ptr [[TMP10]], i32 [[TMP11]] monotonic, align 4, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] +// AMDGCN_CL_20-NEXT: [[TMP12:%.*]] = atomicrmw and ptr [[TMP10]], i32 [[TMP11]] monotonic, align 4, !noalias.addrspace [[META3]], !amdgpu.no.fine.grained.memory [[META4]], !amdgpu.no.remote.memory [[META4]] // AMDGCN_CL_20-NEXT: store i32 [[TMP12]], ptr addrspace(5) [[ATOMIC_TEMP4]], align 4 // AMDGCN_CL_20-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(5) [[ATOMIC_TEMP4]], align 4 // AMDGCN_CL_20-NEXT: [[TMP14:%.*]] = load ptr, ptr addrspace(5) [[C_ADDR]], align 8 @@ -799,7 +799,7 @@ void fi2b(int *i) { // AMDGCN_CL_20-NEXT: [[TMP15:%.*]] = load ptr, ptr addrspace(5) [[D_ADDR]], align 8 // AMDGCN_CL_20-NEXT: store i32 1, ptr addrspace(5) [[DOTATOMICTMP5]], align 4 // AMDGCN_CL_20-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(5) [[DOTATOMICTMP5]], align 4 -// AMDGCN_CL_20-NEXT: [[TMP17:%.*]] = atomicrmw or ptr [[TMP15]], i32 [[TMP16]] monotonic, align 4, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] +// AMDGCN_CL_20-NEXT: [[TMP17:%.*]] = atomicrmw or ptr [[TMP15]], i32 [[TMP16]] monotonic, align 4, !noalias.addrspace [[META3]], !amdgpu.no.fine.grained.memory [[META4]], !amdgpu.no.remote.memory [[META4]] // AMDGCN_CL_20-NEXT: store i32 [[TMP17]], ptr addrspace(5) [[ATOMIC_TEMP6]], align 4 // AMDGCN_CL_20-NEXT: [[TMP18:%.*]] = load i32, ptr addrspace(5) [[ATOMIC_TEMP6]], align 4 // AMDGCN_CL_20-NEXT: [[TMP19:%.*]] = load ptr, ptr addrspace(5) [[D_ADDR]], align 8 @@ -807,7 +807,7 @@ void fi2b(int *i) { // AMDGCN_CL_20-NEXT: [[TMP20:%.*]] = load ptr, ptr addrspace(5) [[E_ADDR]], align 8 // AMDGCN_CL_20-NEXT: store i32 1, ptr addrspace(5) [[DOTATOMICTMP7]], align 4 // AMDGCN_CL_20-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(5) [[DOTATOMICTMP7]], align 4 -// AMDGCN_CL_20-NEXT: [[TMP22:%.*]] = atomicrmw xor ptr [[TMP20]], i32 [[TMP21]] monotonic, align 4, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] +// AMDGCN_CL_20-NEXT: [[TMP22:%.*]] = atomicrmw xor ptr [[TMP20]], i32 [[TMP21]] monotonic, align 4, !noalias.addrspace [[META3]], !amdgpu.no.fine.grained.memory [[META4]], !amdgpu.no.remote.memory [[META4]] // AMDGCN_CL_20-NEXT: store i32 [[TMP22]], ptr addrspace(5) [[ATOMIC_TEMP8]], align 4 // AMDGCN_CL_20-NEXT: [[TMP23:%.*]] = load i32, ptr addrspace(5) [[ATOMIC_TEMP8]], align 4 // AMDGCN_CL_20-NEXT: [[TMP24:%.*]] = load ptr, ptr addrspace(5) [[E_ADDR]], align 8 @@ -815,7 +815,7 @@ void fi2b(int *i) { // AMDGCN_CL_20-NEXT: [[TMP25:%.*]] = load ptr, ptr addrspace(5) [[F_ADDR]], align 8 // AMDGCN_CL_20-NEXT: store i32 1, ptr addrspace(5) [[DOTATOMICTMP9]], align 4 // AMDGCN_CL_20-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(5) [[DOTATOMICTMP9]], align 4 -// AMDGCN_CL_20-NEXT: [[TMP27:%.*]] = atomicrmw nand ptr [[TMP25]], i32 [[TMP26]] monotonic, align 4, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] +// AMDGCN_CL_20-NEXT: [[TMP27:%.*]] = atomicrmw nand ptr [[TMP25]], i32 [[TMP26]] monotonic, align 4, !noalias.addrspace [[META3]], !amdgpu.no.fine.grained.memory [[META4]], !amdgpu.no.remote.memory [[META4]] // AMDGCN_CL_20-NEXT: store i32 [[TMP27]], ptr addrspace(5) [[ATOMIC_TEMP10]], align 4 // AMDGCN_CL_20-NEXT: [[TMP28:%.*]] = load i32, ptr addrspace(5) [[ATOMIC_TEMP10]], align 4 // AMDGCN_CL_20-NEXT: [[TMP29:%.*]] = load ptr, ptr addrspace(5) [[F_ADDR]], align 8 @@ -823,7 +823,7 @@ void fi2b(int *i) { // AMDGCN_CL_20-NEXT: [[TMP30:%.*]] = load ptr, ptr addrspace(5) [[G_ADDR]], align 8 // AMDGCN_CL_20-NEXT: store i32 1, ptr addrspace(5) [[DOTATOMICTMP11]], align 4 // AMDGCN_CL_20-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(5) [[DOTATOMICTMP11]], align 4 -// AMDGCN_CL_20-NEXT: [[TMP32:%.*]] = atomicrmw min ptr [[TMP30]], i32 [[TMP31]] monotonic, align 4, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] +// AMDGCN_CL_20-NEXT: [[TMP32:%.*]] = atomicrmw min ptr [[TMP30]], i32 [[TMP31]] monotonic, align 4, !noalias.addrspace [[META3]], !amdgpu.no.fine.grained.memory [[META4]], !amdgpu.no.remote.memory [[META4]] // AMDGCN_CL_20-NEXT: store i32 [[TMP32]], ptr addrspace(5) [[ATOMIC_TEMP12]], align 4 // AMDGCN_CL_20-NEXT: [[TMP33:%.*]] = load i32, ptr addrspace(5) [[ATOMIC_TEMP12]], align 4 // AMDGCN_CL_20-NEXT: [[TMP34:%.*]] = load ptr, ptr addrspace(5) [[G_ADDR]], align 8 @@ -831,7 +831,7 @@ void fi2b(int *i) { // AMDGCN_CL_20-NEXT: [[TMP35:%.*]] = load ptr, ptr addrspace(5) [[H_ADDR]], align 8 // AMDGCN_CL_20-NEXT: store i32 1, ptr addrspace(5) [[DOTATOMICTMP13]], align 4 // AMDGCN_CL_20-NEXT: [[TMP36:%.*]] = load i32, ptr addrspace(5) [[DOTATOMICTMP13]], align 4 -// AMDGCN_CL_20-NEXT: [[TMP37:%.*]] = atomicrmw max ptr [[TMP35]], i32 [[TMP36]] monotonic, align 4, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] +// AMDGCN_CL_20-NEXT: [[TMP37:%.*]] = atomicrmw max ptr [[TMP35]], i32 [[TMP36]] monotonic, align 4, !noalias.addrspace [[META3]], !amdgpu.no.fine.grained.memory [[META4]], !amdgpu.no.remote.memory [[META4]] // AMDGCN_CL_20-NEXT: store i32 [[TMP37]], ptr addrspace(5) [[ATOMIC_TEMP14]], align 4 // AMDGCN_CL_20-NEXT: [[TMP38:%.*]] = load i32, ptr addrspace(5) [[ATOMIC_TEMP14]], align 4 // AMDGCN_CL_20-NEXT: [[TMP39:%.*]] = load ptr, ptr addrspace(5) [[H_ADDR]], align 8 @@ -1198,7 +1198,7 @@ void fi3a(int *a, int *b, int *c, int *d, int *e, int *f, int *g, int *h) { // AMDGCN_CL_20-NEXT: [[TMP0:%.*]] = load ptr, ptr addrspace(5) [[A_ADDR]], align 8 // AMDGCN_CL_20-NEXT: store i32 1, ptr addrspace(5) [[DOTATOMICTMP]], align 4 // AMDGCN_CL_20-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[DOTATOMICTMP]], align 4 -// AMDGCN_CL_20-NEXT: [[TMP2:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP1]] syncscope("agent") monotonic, align 4, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] +// AMDGCN_CL_20-NEXT: [[TMP2:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP1]] syncscope("agent") monotonic, align 4, !noalias.addrspace [[META3]], !amdgpu.no.fine.grained.memory [[META4]], !amdgpu.no.remote.memory [[META4]] // AMDGCN_CL_20-NEXT: store i32 [[TMP2]], ptr addrspace(5) [[ATOMIC_TEMP]], align 4 // AMDGCN_CL_20-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(5) [[ATOMIC_TEMP]], align 4 // AMDGCN_CL_20-NEXT: [[TMP4:%.*]] = load ptr, ptr addrspace(5) [[A_ADDR]], align 8 @@ -1206,7 +1206,7 @@ void fi3a(int *a, int *b, int *c, int *d, int *e, int *f, int *g, int *h) { // AMDGCN_CL_20-NEXT: [[TMP5:%.*]] = load ptr, ptr addrspace(5) [[B_ADDR]], align 8 // AMDGCN_CL_20-NEXT: store i32 1, ptr addrspace(5) [[DOTATOMICTMP1]], align 4 // AMDGCN_CL_20-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(5) [[DOTATOMICTMP1]], align 4 -// AMDGCN_CL_20-NEXT: [[TMP7:%.*]] = atomicrmw sub ptr [[TMP5]], i32 [[TMP6]] syncscope("agent") monotonic, align 4, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] +// AMDGCN_CL_20-NEXT: [[TMP7:%.*]] = atomicrmw sub ptr [[TMP5]], i32 [[TMP6]] syncscope("agent") monotonic, align 4, !noalias.addrspace [[META3]], !amdgpu.no.fine.grained.memory [[META4]], !amdgpu.no.remote.memory [[META4]] // AMDGCN_CL_20-NEXT: store i32 [[TMP7]], ptr addrspace(5) [[ATOMIC_TEMP2]], align 4 // AMDGCN_CL_20-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(5) [[ATOMIC_TEMP2]], align 4 // AMDGCN_CL_20-NEXT: [[TMP9:%.*]] = load ptr, ptr addrspace(5) [[B_ADDR]], align 8 @@ -1214,7 +1214,7 @@ void fi3a(int *a, int *b, int *c, int *d, int *e, int *f, int *g, int *h) { // AMDGCN_CL_20-NEXT: [[TMP10:%.*]] = load ptr, ptr addrspace(5) [[C_ADDR]], align 8 // AMDGCN_CL_20-NEXT: store i32 1, ptr addrspace(5) [[DOTATOMICTMP3]], align 4 // AMDGCN_CL_20-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(5) [[DOTATOMICTMP3]], align 4 -// AMDGCN_CL_20-NEXT: [[TMP12:%.*]] = atomicrmw and ptr [[TMP10]], i32 [[TMP11]] syncscope("agent") monotonic, align 4, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] +// AMDGCN_CL_20-NEXT: [[TMP12:%.*]] = atomicrmw and ptr [[TMP10]], i32 [[TMP11]] syncscope("agent") monotonic, align 4, !noalias.addrspace [[META3]], !amdgpu.no.fine.grained.memory [[META4]], !amdgpu.no.remote.memory [[META4]] // AMDGCN_CL_20-NEXT: store i32 [[TMP12]], ptr addrspace(5) [[ATOMIC_TEMP4]], align 4 // AMDGCN_CL_20-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(5) [[ATOMIC_TEMP4]], align 4 // AMDGCN_CL_20-NEXT: [[TMP14:%.*]] = load ptr, ptr addrspace(5) [[C_ADDR]], align 8 @@ -1222,7 +1222,7 @@ void fi3a(int *a, int *b, int *c, int *d, int *e, int *f, int *g, int *h) { // AMDGCN_CL_20-NEXT: [[TMP15:%.*]] = load ptr, ptr addrspace(5) [[D_ADDR]], align 8 // AMDGCN_CL_20-NEXT: store i32 1, ptr addrspace(5) [[DOTATOMICTMP5]], align 4 // AMDGCN_CL_20-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(5) [[DOTATOMICTMP5]], align 4 -// AMDGCN_CL_20-NEXT: [[TMP17:%.*]] = atomicrmw or ptr [[TMP15]], i32 [[TMP16]] syncscope("agent") monotonic, align 4, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] +// AMDGCN_CL_20-NEXT: [[TMP17:%.*]] = atomicrmw or ptr [[TMP15]], i32 [[TMP16]] syncscope("agent") monotonic, align 4, !noalias.addrspace [[META3]], !amdgpu.no.fine.grained.memory [[META4]], !amdgpu.no.remote.memory [[META4]] // AMDGCN_CL_20-NEXT: store i32 [[TMP17]], ptr addrspace(5) [[ATOMIC_TEMP6]], align 4 // AMDGCN_CL_20-NEXT: [[TMP18:%.*]] = load i32, ptr addrspace(5) [[ATOMIC_TEMP6]], align 4 // AMDGCN_CL_20-NEXT: [[TMP19:%.*]] = load ptr, ptr addrspace(5) [[D_ADDR]], align 8 @@ -1230,7 +1230,7 @@ void fi3a(int *a, int *b, int *c, int *d, int *e, int *f, int *g, int *h) { // AMDGCN_CL_20-NEXT: [[TMP20:%.*]] = load ptr, ptr addrspace(5) [[E_ADDR]], align 8 // AMDGCN_CL_20-NEXT: store i32 1, ptr addrspace(5) [[DOTATOMICTMP7]], align 4 // AMDGCN_CL_20-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(5) [[DOTATOMICTMP7]], align 4 -// AMDGCN_CL_20-NEXT: [[TMP22:%.*]] = atomicrmw xor ptr [[TMP20]], i32 [[TMP21]] syncscope("agent") monotonic, align 4, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] +// AMDGCN_CL_20-NEXT: [[TMP22:%.*]] = atomicrmw xor ptr [[TMP20]], i32 [[TMP21]] syncscope("agent") monotonic, align 4, !noalias.addrspace [[META3]], !amdgpu.no.fine.grained.memory [[META4]], !amdgpu.no.remote.memory [[META4]] // AMDGCN_CL_20-NEXT: store i32 [[TMP22]], ptr addrspace(5) [[ATOMIC_TEMP8]], align 4 // AMDGCN_CL_20-NEXT: [[TMP23:%.*]] = load i32, ptr addrspace(5) [[ATOMIC_TEMP8]], align 4 // AMDGCN_CL_20-NEXT: [[TMP24:%.*]] = load ptr, ptr addrspace(5) [[E_ADDR]], align 8 @@ -1238,7 +1238,7 @@ void fi3a(int *a, int *b, int *c, int *d, int *e, int *f, int *g, int *h) { // AMDGCN_CL_20-NEXT: [[TMP25:%.*]] = load ptr, ptr addrspace(5) [[F_ADDR]], align 8 // AMDGCN_CL_20-NEXT: store i32 1, ptr addrspace(5) [[DOTATOMICTMP9]], align 4 // AMDGCN_CL_20-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(5) [[DOTATOMICTMP9]], align 4 -// AMDGCN_CL_20-NEXT: [[TMP27:%.*]] = atomicrmw nand ptr [[TMP25]], i32 [[TMP26]] syncscope("agent") monotonic, align 4, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] +// AMDGCN_CL_20-NEXT: [[TMP27:%.*]] = atomicrmw nand ptr [[TMP25]], i32 [[TMP26]] syncscope("agent") monotonic, align 4, !noalias.addrspace [[META3]], !amdgpu.no.fine.grained.memory [[META4]], !amdgpu.no.remote.memory [[META4]] // AMDGCN_CL_20-NEXT: store i32 [[TMP27]], ptr addrspace(5) [[ATOMIC_TEMP10]], align 4 // AMDGCN_CL_20-NEXT: [[TMP28:%.*]] = load i32, ptr addrspace(5) [[ATOMIC_TEMP10]], align 4 // AMDGCN_CL_20-NEXT: [[TMP29:%.*]] = load ptr, ptr addrspace(5) [[F_ADDR]], align 8 @@ -1246,7 +1246,7 @@ void fi3a(int *a, int *b, int *c, int *d, int *e, int *f, int *g, int *h) { // AMDGCN_CL_20-NEXT: [[TMP30:%.*]] = load ptr, ptr addrspace(5) [[G_ADDR]], align 8 // AMDGCN_CL_20-NEXT: store i32 1, ptr addrspace(5) [[DOTATOMICTMP11]], align 4 // AMDGCN_CL_20-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(5) [[DOTATOMICTMP11]], align 4 -// AMDGCN_CL_20-NEXT: [[TMP32:%.*]] = atomicrmw min ptr [[TMP30]], i32 [[TMP31]] syncscope("agent") monotonic, align 4, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] +// AMDGCN_CL_20-NEXT: [[TMP32:%.*]] = atomicrmw min ptr [[TMP30]], i32 [[TMP31]] syncscope("agent") monotonic, align 4, !noalias.addrspace [[META3]], !amdgpu.no.fine.grained.memory [[META4]], !amdgpu.no.remote.memory [[META4]] // AMDGCN_CL_20-NEXT: store i32 [[TMP32]], ptr addrspace(5) [[ATOMIC_TEMP12]], align 4 // AMDGCN_CL_20-NEXT: [[TMP33:%.*]] = load i32, ptr addrspace(5) [[ATOMIC_TEMP12]], align 4 // AMDGCN_CL_20-NEXT: [[TMP34:%.*]] = load ptr, ptr addrspace(5) [[G_ADDR]], align 8 @@ -1254,7 +1254,7 @@ void fi3a(int *a, int *b, int *c, int *d, int *e, int *f, int *g, int *h) { // AMDGCN_CL_20-NEXT: [[TMP35:%.*]] = load ptr, ptr addrspace(5) [[H_ADDR]], align 8 // AMDGCN_CL_20-NEXT: store i32 1, ptr addrspace(5... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/230044 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
