https://github.com/topperc created https://github.com/llvm/llvm-project/pull/238068
Similar for riscv.pmulh.b0 and riscv.pmulh.h0. This includes different signedness and different half number. The underlying RISCVISD opcodes were already combined. I added ".half." to the intrinsic name to better distinquish from the riscv.pmulh intrinsic. Otherwise we would have riscv.pmulh, riscv.pmulh.0, and riscv.pmulh.1. Assisted-by: Claude >From 094d9aa6db6c89b0c44ac11331f5dcdf630a28ea Mon Sep 17 00:00:00 2001 From: Craig Topper <[email protected]> Date: Mon, 2 Nov 2026 10:55:30 -0800 Subject: [PATCH] [RISCV][P-ext] Combine riscv.pmhacc.b0 and riscv.pmhacc.h0 into a single intrinsic. Similar for riscv.pmulh.b0 and riscv.pmulh.h0. This includes different signedness and different half number. The underlying RISCVISD opcodes were already combined. I added ".half." to the intrinsic name to better separate from the riscv.pmulh intrinsic. Assisted-by: Claude --- clang/lib/CodeGen/TargetBuiltins/RISCV.cpp | 56 +++++--------- clang/test/CodeGen/RISCV/rvp-intrinsics.c | 48 ++++++------ llvm/include/llvm/IR/IntrinsicsRISCV.td | 40 ++-------- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 84 ++++++--------------- llvm/test/CodeGen/RISCV/rvp-simd-32.ll | 16 ++-- llvm/test/CodeGen/RISCV/rvp-simd-64.ll | 48 ++++++------ 6 files changed, 109 insertions(+), 183 deletions(-) diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp index 0d6bc6c66c1a01..d2a646f9e1bc65 100644 --- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp @@ -1587,31 +1587,23 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, break; case RISCV::BI__builtin_riscv_pmhacc_b0_i16x2: case RISCV::BI__builtin_riscv_pmhacc_b0_i16x4: - ID = Intrinsic::riscv_pmhacc_b0; - break; - case RISCV::BI__builtin_riscv_pmhacc_b1_i16x2: - case RISCV::BI__builtin_riscv_pmhacc_b1_i16x4: - ID = Intrinsic::riscv_pmhacc_b1; + case RISCV::BI__builtin_riscv_pmhacc_h0_i32x2: + ID = Intrinsic::riscv_pmhacc_half_0; break; case RISCV::BI__builtin_riscv_pmhaccsu_b0_i16x2: case RISCV::BI__builtin_riscv_pmhaccsu_b0_i16x4: - ID = Intrinsic::riscv_pmhaccsu_b0; - break; - case RISCV::BI__builtin_riscv_pmhaccsu_b1_i16x2: - case RISCV::BI__builtin_riscv_pmhaccsu_b1_i16x4: - ID = Intrinsic::riscv_pmhaccsu_b1; - break; - case RISCV::BI__builtin_riscv_pmhacc_h0_i32x2: - ID = Intrinsic::riscv_pmhacc_h0; + case RISCV::BI__builtin_riscv_pmhaccsu_h0_i32x2: + ID = Intrinsic::riscv_pmhaccsu_half_0; break; + case RISCV::BI__builtin_riscv_pmhacc_b1_i16x2: + case RISCV::BI__builtin_riscv_pmhacc_b1_i16x4: case RISCV::BI__builtin_riscv_pmhacc_h1_i32x2: - ID = Intrinsic::riscv_pmhacc_h1; - break; - case RISCV::BI__builtin_riscv_pmhaccsu_h0_i32x2: - ID = Intrinsic::riscv_pmhaccsu_h0; + ID = Intrinsic::riscv_pmhacc_half_1; break; + case RISCV::BI__builtin_riscv_pmhaccsu_b1_i16x2: + case RISCV::BI__builtin_riscv_pmhaccsu_b1_i16x4: case RISCV::BI__builtin_riscv_pmhaccsu_h1_i32x2: - ID = Intrinsic::riscv_pmhaccsu_h1; + ID = Intrinsic::riscv_pmhaccsu_half_1; break; case RISCV::BI__builtin_riscv_psabs_i8x4: case RISCV::BI__builtin_riscv_psabs_i16x2: @@ -2144,31 +2136,23 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, break; case RISCV::BI__builtin_riscv_pmulh_b0_i16x2: case RISCV::BI__builtin_riscv_pmulh_b0_i16x4: - ID = Intrinsic::riscv_pmulh_b0; - break; - case RISCV::BI__builtin_riscv_pmulh_b1_i16x2: - case RISCV::BI__builtin_riscv_pmulh_b1_i16x4: - ID = Intrinsic::riscv_pmulh_b1; + case RISCV::BI__builtin_riscv_pmulh_h0_i32x2: + ID = Intrinsic::riscv_pmulh_half_0; break; case RISCV::BI__builtin_riscv_pmulhsu_b0_i16x2: case RISCV::BI__builtin_riscv_pmulhsu_b0_i16x4: - ID = Intrinsic::riscv_pmulhsu_b0; - break; - case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x2: - case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x4: - ID = Intrinsic::riscv_pmulhsu_b1; - break; - case RISCV::BI__builtin_riscv_pmulh_h0_i32x2: - ID = Intrinsic::riscv_pmulh_h0; + case RISCV::BI__builtin_riscv_pmulhsu_h0_i32x2: + ID = Intrinsic::riscv_pmulhsu_half_0; break; + case RISCV::BI__builtin_riscv_pmulh_b1_i16x2: + case RISCV::BI__builtin_riscv_pmulh_b1_i16x4: case RISCV::BI__builtin_riscv_pmulh_h1_i32x2: - ID = Intrinsic::riscv_pmulh_h1; - break; - case RISCV::BI__builtin_riscv_pmulhsu_h0_i32x2: - ID = Intrinsic::riscv_pmulhsu_h0; + ID = Intrinsic::riscv_pmulh_half_1; break; + case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x2: + case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x4: case RISCV::BI__builtin_riscv_pmulhsu_h1_i32x2: - ID = Intrinsic::riscv_pmulhsu_h1; + ID = Intrinsic::riscv_pmulhsu_half_1; break; } diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c index 0fa253c1cba893..956d80beb1228b 100644 --- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c +++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c @@ -8291,7 +8291,7 @@ int64_t test_mqracc_w11_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.b0.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.half.0.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]]) // CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32 // CHECK-NEXT: ret i32 [[TMP3]] // @@ -8304,7 +8304,7 @@ int16x2_t test_pmulh_b0_i16x2(int16x2_t rs1, int8x4_t rs2) { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.b1.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.half.1.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]]) // CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32 // CHECK-NEXT: ret i32 [[TMP3]] // @@ -8317,7 +8317,7 @@ int16x2_t test_pmulh_b1_i16x2(int16x2_t rs1, int8x4_t rs2) { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.b0.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.half.0.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]]) // CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32 // CHECK-NEXT: ret i32 [[TMP3]] // @@ -8330,7 +8330,7 @@ int16x2_t test_pmulhsu_b0_i16x2(int16x2_t rs1, uint8x4_t rs2) { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.b1.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.half.1.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]]) // CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32 // CHECK-NEXT: ret i32 [[TMP3]] // @@ -8417,7 +8417,7 @@ int32_t test_mulhsu_h1_i32(int32_t rs1, uint16x2_t rs2) { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulh.b0.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulh.half.0.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]]) // CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64 // CHECK-NEXT: ret i64 [[TMP3]] // @@ -8430,7 +8430,7 @@ int16x4_t test_pmulh_b0_i16x4(int16x4_t rs1, int8x8_t rs2) { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulh.b1.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulh.half.1.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]]) // CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64 // CHECK-NEXT: ret i64 [[TMP3]] // @@ -8443,7 +8443,7 @@ int16x4_t test_pmulh_b1_i16x4(int16x4_t rs1, int8x8_t rs2) { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhsu.b0.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhsu.half.0.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]]) // CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64 // CHECK-NEXT: ret i64 [[TMP3]] // @@ -8456,7 +8456,7 @@ int16x4_t test_pmulhsu_b0_i16x4(int16x4_t rs1, uint8x8_t rs2) { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhsu.b1.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhsu.half.1.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]]) // CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64 // CHECK-NEXT: ret i64 [[TMP3]] // @@ -8469,7 +8469,7 @@ int16x4_t test_pmulhsu_b1_i16x4(int16x4_t rs1, uint8x8_t rs2) { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> -// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulh.h0.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulh.half.0.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]]) // CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64 // CHECK-NEXT: ret i64 [[TMP3]] // @@ -8482,7 +8482,7 @@ int32x2_t test_pmulh_h0_i32x2(int32x2_t rs1, int16x4_t rs2) { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> -// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulh.h1.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulh.half.1.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]]) // CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64 // CHECK-NEXT: ret i64 [[TMP3]] // @@ -8495,7 +8495,7 @@ int32x2_t test_pmulh_h1_i32x2(int32x2_t rs1, int16x4_t rs2) { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> -// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhsu.h0.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhsu.half.0.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]]) // CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64 // CHECK-NEXT: ret i64 [[TMP3]] // @@ -8508,7 +8508,7 @@ int32x2_t test_pmulhsu_h0_i32x2(int32x2_t rs1, uint16x4_t rs2) { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> -// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhsu.h1.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhsu.half.1.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]]) // CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64 // CHECK-NEXT: ret i64 [[TMP3]] // @@ -11936,7 +11936,7 @@ int32x2_t test_pmhraccsu_i32x2(int32x2_t rd, int32x2_t a, uint32x2_t b) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16> // CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8> -// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmhacc.b0.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i8> [[TMP2]]) +// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmhacc.half.0.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i8> [[TMP2]]) // CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32 // CHECK-NEXT: ret i32 [[TMP4]] // @@ -11950,7 +11950,7 @@ int16x2_t test_pmhacc_b0_i16x2(int16x2_t rd, int16x2_t a, int8x4_t b) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16> // CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8> -// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmhacc.b1.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i8> [[TMP2]]) +// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmhacc.half.1.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i8> [[TMP2]]) // CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32 // CHECK-NEXT: ret i32 [[TMP4]] // @@ -11964,7 +11964,7 @@ int16x2_t test_pmhacc_b1_i16x2(int16x2_t rd, int16x2_t a, int8x4_t b) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16> // CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8> -// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmhaccsu.b0.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i8> [[TMP2]]) +// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmhaccsu.half.0.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i8> [[TMP2]]) // CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32 // CHECK-NEXT: ret i32 [[TMP4]] // @@ -11978,7 +11978,7 @@ int16x2_t test_pmhaccsu_b0_i16x2(int16x2_t rd, int16x2_t a, uint8x4_t b) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16> // CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8> -// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmhaccsu.b1.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i8> [[TMP2]]) +// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmhaccsu.half.1.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i8> [[TMP2]]) // CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32 // CHECK-NEXT: ret i32 [[TMP4]] // @@ -11992,7 +11992,7 @@ int16x2_t test_pmhaccsu_b1_i16x2(int16x2_t rd, int16x2_t a, uint8x4_t b) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16> // CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8> -// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmhacc.b0.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <8 x i8> [[TMP2]]) +// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmhacc.half.0.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <8 x i8> [[TMP2]]) // CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64 // CHECK-NEXT: ret i64 [[TMP4]] // @@ -12006,7 +12006,7 @@ int16x4_t test_pmhacc_b0_i16x4(int16x4_t rd, int16x4_t a, int8x8_t b) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16> // CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8> -// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmhacc.b1.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <8 x i8> [[TMP2]]) +// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmhacc.half.1.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <8 x i8> [[TMP2]]) // CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64 // CHECK-NEXT: ret i64 [[TMP4]] // @@ -12020,7 +12020,7 @@ int16x4_t test_pmhacc_b1_i16x4(int16x4_t rd, int16x4_t a, int8x8_t b) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16> // CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8> -// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmhaccsu.b0.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <8 x i8> [[TMP2]]) +// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmhaccsu.half.0.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <8 x i8> [[TMP2]]) // CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64 // CHECK-NEXT: ret i64 [[TMP4]] // @@ -12034,7 +12034,7 @@ int16x4_t test_pmhaccsu_b0_i16x4(int16x4_t rd, int16x4_t a, uint8x8_t b) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16> // CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8> -// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmhaccsu.b1.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <8 x i8> [[TMP2]]) +// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmhaccsu.half.1.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <8 x i8> [[TMP2]]) // CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64 // CHECK-NEXT: ret i64 [[TMP4]] // @@ -12048,7 +12048,7 @@ int16x4_t test_pmhaccsu_b1_i16x4(int16x4_t rd, int16x4_t a, uint8x8_t b) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32> // CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16> -// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmhacc.h0.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <4 x i16> [[TMP2]]) +// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmhacc.half.0.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <4 x i16> [[TMP2]]) // CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64 // CHECK-NEXT: ret i64 [[TMP4]] // @@ -12062,7 +12062,7 @@ int32x2_t test_pmhacc_h0_i32x2(int32x2_t rd, int32x2_t a, int16x4_t b) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32> // CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16> -// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmhacc.h1.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <4 x i16> [[TMP2]]) +// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmhacc.half.1.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <4 x i16> [[TMP2]]) // CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64 // CHECK-NEXT: ret i64 [[TMP4]] // @@ -12076,7 +12076,7 @@ int32x2_t test_pmhacc_h1_i32x2(int32x2_t rd, int32x2_t a, int16x4_t b) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32> // CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16> -// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmhaccsu.h0.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <4 x i16> [[TMP2]]) +// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmhaccsu.half.0.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <4 x i16> [[TMP2]]) // CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64 // CHECK-NEXT: ret i64 [[TMP4]] // @@ -12090,7 +12090,7 @@ int32x2_t test_pmhaccsu_h0_i32x2(int32x2_t rd, int32x2_t a, uint16x4_t b) { // CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32> // CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32> // CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16> -// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmhaccsu.h1.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <4 x i16> [[TMP2]]) +// CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmhaccsu.half.1.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <4 x i16> [[TMP2]]) // CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64 // CHECK-NEXT: ret i64 [[TMP4]] // diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index 397f0f4efa9b67..c85ed3658ba844 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -2232,42 +2232,22 @@ class RVPBinaryIntrinsic // operand's elements are half as wide, with twice the element count. For // the .b forms the third operand holds bytes, for the .w forms it holds // halfwords. - def int_riscv_pmhacc_b0 + def int_riscv_pmhacc_half_0 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMSubdivide2VectorType<0>], [IntrNoMem, IntrSpeculatable]>; - def int_riscv_pmhacc_b1 + def int_riscv_pmhacc_half_1 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMSubdivide2VectorType<0>], [IntrNoMem, IntrSpeculatable]>; - def int_riscv_pmhaccsu_b0 + def int_riscv_pmhaccsu_half_0 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMSubdivide2VectorType<0>], [IntrNoMem, IntrSpeculatable]>; - def int_riscv_pmhaccsu_b1 - : DefaultAttrsIntrinsic<[llvm_anyvector_ty], - [LLVMMatchType<0>, LLVMMatchType<0>, - LLVMSubdivide2VectorType<0>], - [IntrNoMem, IntrSpeculatable]>; - def int_riscv_pmhacc_h0 - : DefaultAttrsIntrinsic<[llvm_anyvector_ty], - [LLVMMatchType<0>, LLVMMatchType<0>, - LLVMSubdivide2VectorType<0>], - [IntrNoMem, IntrSpeculatable]>; - def int_riscv_pmhacc_h1 - : DefaultAttrsIntrinsic<[llvm_anyvector_ty], - [LLVMMatchType<0>, LLVMMatchType<0>, - LLVMSubdivide2VectorType<0>], - [IntrNoMem, IntrSpeculatable]>; - def int_riscv_pmhaccsu_h0 - : DefaultAttrsIntrinsic<[llvm_anyvector_ty], - [LLVMMatchType<0>, LLVMMatchType<0>, - LLVMSubdivide2VectorType<0>], - [IntrNoMem, IntrSpeculatable]>; - def int_riscv_pmhaccsu_h1 + def int_riscv_pmhaccsu_half_1 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMSubdivide2VectorType<0>], @@ -2280,14 +2260,10 @@ class RVPBinaryIntrinsic [LLVMMatchType<0>, LLVMSubdivide2VectorType<0>], [IntrNoMem, IntrSpeculatable]>; - def int_riscv_pmulh_b0 : RVPMulHighPartsIntrinsic; - def int_riscv_pmulh_b1 : RVPMulHighPartsIntrinsic; - def int_riscv_pmulhsu_b0 : RVPMulHighPartsIntrinsic; - def int_riscv_pmulhsu_b1 : RVPMulHighPartsIntrinsic; - def int_riscv_pmulh_h0 : RVPMulHighPartsIntrinsic; - def int_riscv_pmulh_h1 : RVPMulHighPartsIntrinsic; - def int_riscv_pmulhsu_h0 : RVPMulHighPartsIntrinsic; - def int_riscv_pmulhsu_h1 : RVPMulHighPartsIntrinsic; + def int_riscv_pmulh_half_0 : RVPMulHighPartsIntrinsic; + def int_riscv_pmulh_half_1 : RVPMulHighPartsIntrinsic; + def int_riscv_pmulhsu_half_0 : RVPMulHighPartsIntrinsic; + def int_riscv_pmulhsu_half_1 : RVPMulHighPartsIntrinsic; // Packed "Q-format" Multiply with Widening Accumulate. class RVPQFormatWideningAccIntrinsic diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index d923a3f43878c6..3e53ff3f79ce56 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -12531,17 +12531,13 @@ static unsigned getRVPMulHighAccumulateHalfOpcode(unsigned IntNo) { default: llvm_unreachable("Unexpected RISC-V packed multiply high accumulate half " "intrinsic"); - case Intrinsic::riscv_pmhacc_b0: - case Intrinsic::riscv_pmhacc_h0: + case Intrinsic::riscv_pmhacc_half_0: return RISCVISD::MHACC_HALF_0; - case Intrinsic::riscv_pmhacc_b1: - case Intrinsic::riscv_pmhacc_h1: + case Intrinsic::riscv_pmhacc_half_1: return RISCVISD::MHACC_HALF_1; - case Intrinsic::riscv_pmhaccsu_b0: - case Intrinsic::riscv_pmhaccsu_h0: + case Intrinsic::riscv_pmhaccsu_half_0: return RISCVISD::MHACCSU_HALF_0; - case Intrinsic::riscv_pmhaccsu_b1: - case Intrinsic::riscv_pmhaccsu_h1: + case Intrinsic::riscv_pmhaccsu_half_1: return RISCVISD::MHACCSU_HALF_1; } } @@ -12553,20 +12549,16 @@ static unsigned getRVPMulHighHalfOpcode(unsigned IntNo) { switch (IntNo) { default: llvm_unreachable("Unexpected RISC-V multiply high half intrinsic"); - case Intrinsic::riscv_pmulh_b0: - case Intrinsic::riscv_pmulh_h0: + case Intrinsic::riscv_pmulh_half_0: case Intrinsic::riscv_mulh_h0: return RISCVISD::MULH_HALF_0; - case Intrinsic::riscv_pmulh_b1: - case Intrinsic::riscv_pmulh_h1: + case Intrinsic::riscv_pmulh_half_1: case Intrinsic::riscv_mulh_h1: return RISCVISD::MULH_HALF_1; - case Intrinsic::riscv_pmulhsu_b0: - case Intrinsic::riscv_pmulhsu_h0: + case Intrinsic::riscv_pmulhsu_half_0: case Intrinsic::riscv_mulhsu_h0: return RISCVISD::MULHSU_HALF_0; - case Intrinsic::riscv_pmulhsu_b1: - case Intrinsic::riscv_pmulhsu_h1: + case Intrinsic::riscv_pmulhsu_half_1: case Intrinsic::riscv_mulhsu_h1: return RISCVISD::MULHSU_HALF_1; } @@ -13510,10 +13502,10 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, return DAG.getNode(MulOpc, DL, VT, Rd, Rs1, Rs2); } - case Intrinsic::riscv_pmhacc_b0: - case Intrinsic::riscv_pmhacc_b1: - case Intrinsic::riscv_pmhaccsu_b0: - case Intrinsic::riscv_pmhaccsu_b1: { + case Intrinsic::riscv_pmhacc_half_0: + case Intrinsic::riscv_pmhacc_half_1: + case Intrinsic::riscv_pmhaccsu_half_0: + case Intrinsic::riscv_pmhaccsu_half_1: { EVT VT = Op.getValueType(); unsigned Opc = getRVPMulHighAccumulateHalfOpcode(IntNo); SDValue Rd = Op.getOperand(1); @@ -13530,18 +13522,6 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi); } - return DAG.getNode(Opc, DL, VT, Rd, Rs1, Rs2); - } - case Intrinsic::riscv_pmhacc_h0: - case Intrinsic::riscv_pmhacc_h1: - case Intrinsic::riscv_pmhaccsu_h0: - case Intrinsic::riscv_pmhaccsu_h1: { - EVT VT = Op.getValueType(); - unsigned Opc = getRVPMulHighAccumulateHalfOpcode(IntNo); - SDValue Rd = Op.getOperand(1); - SDValue Rs1 = Op.getOperand(2); - SDValue Rs2 = Op.getOperand(3); - // RV32 has no 64-bit packed form: split into two scalar operations, each // accumulating one word of the result. if (!Subtarget.is64Bit() && VT == MVT::v2i32) { @@ -13558,10 +13538,10 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, return DAG.getNode(Opc, DL, VT, Rd, Rs1, Rs2); } - case Intrinsic::riscv_pmulh_b0: - case Intrinsic::riscv_pmulh_b1: - case Intrinsic::riscv_pmulhsu_b0: - case Intrinsic::riscv_pmulhsu_b1: { + case Intrinsic::riscv_pmulh_half_0: + case Intrinsic::riscv_pmulh_half_1: + case Intrinsic::riscv_pmulhsu_half_0: + case Intrinsic::riscv_pmulhsu_half_1: { EVT VT = Op.getValueType(); SDValue Rs1 = Op.getOperand(1); SDValue Rs2 = Op.getOperand(2); @@ -13577,17 +13557,6 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi); } - return DAG.getNode(Opc, DL, VT, Rs1, Rs2); - } - case Intrinsic::riscv_pmulh_h0: - case Intrinsic::riscv_pmulh_h1: - case Intrinsic::riscv_pmulhsu_h0: - case Intrinsic::riscv_pmulhsu_h1: { - EVT VT = Op.getValueType(); - SDValue Rs1 = Op.getOperand(1); - SDValue Rs2 = Op.getOperand(2); - unsigned Opc = getRVPMulHighHalfOpcode(IntNo); - // RV32 has no single instruction for a 64-bit packed word multiply-high // parts. Split v2i32 into two scalar operations, one per result word. if (!Subtarget.is64Bit() && VT == MVT::v2i32) { @@ -13600,10 +13569,7 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Lo, Hi); } - if (Subtarget.is64Bit()) - return DAG.getNode(Opc, DL, VT, Rs1, Rs2); - - return SDValue(); + return DAG.getNode(Opc, DL, VT, Rs1, Rs2); } case Intrinsic::riscv_pmqwacc_i32x2: case Intrinsic::riscv_pmqrwacc_i32x2: { @@ -18013,10 +17979,10 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, Results.push_back(DAG.getExtractSubvector(DL, VT, Res, 0)); return; } - case Intrinsic::riscv_pmhacc_b0: - case Intrinsic::riscv_pmhacc_b1: - case Intrinsic::riscv_pmhaccsu_b0: - case Intrinsic::riscv_pmhaccsu_b1: { + case Intrinsic::riscv_pmhacc_half_0: + case Intrinsic::riscv_pmhacc_half_1: + case Intrinsic::riscv_pmhaccsu_half_0: + case Intrinsic::riscv_pmhaccsu_half_1: { // pmhacc.h.bXX operates on the whole register: v2i16 on RV32 and // v4i16 on RV64. On RV64 a v2i16 result widens to the packed v4i16 // form and extracts the low half. @@ -18173,10 +18139,10 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, } reportFatalUsageError("unsupported llvm.riscv multiply-parts intrinsic"); } - case Intrinsic::riscv_pmulh_b0: - case Intrinsic::riscv_pmulh_b1: - case Intrinsic::riscv_pmulhsu_b0: - case Intrinsic::riscv_pmulhsu_b1: { + case Intrinsic::riscv_pmulh_half_0: + case Intrinsic::riscv_pmulh_half_1: + case Intrinsic::riscv_pmulhsu_half_0: + case Intrinsic::riscv_pmulhsu_half_1: { // A 32-bit result has no legal container on RV64; widen the result and // both sources to the 64-bit packed form. EVT VT = N->getValueType(0); diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll index a70a00ebcd58dc..8c57d611888f5b 100644 --- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll +++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll @@ -3921,7 +3921,7 @@ define <2 x i16> @test_pmhacc_b0_v2i16(<2 x i16> %rd, <2 x i16> %rs1, <4 x i8> % ; CHECK: # %bb.0: ; CHECK-NEXT: pmhacc.h.b0 a0, a1, a2 ; CHECK-NEXT: ret - %res = call <2 x i16> @llvm.riscv.pmhacc.b0.v2i16(<2 x i16> %rd, <2 x i16> %rs1, <4 x i8> %rs2) + %res = call <2 x i16> @llvm.riscv.pmhacc.half.0.v2i16(<2 x i16> %rd, <2 x i16> %rs1, <4 x i8> %rs2) ret <2 x i16> %res } @@ -3930,7 +3930,7 @@ define <2 x i16> @test_pmhacc_b1_v2i16(<2 x i16> %rd, <2 x i16> %rs1, <4 x i8> % ; CHECK: # %bb.0: ; CHECK-NEXT: pmhacc.h.b1 a0, a1, a2 ; CHECK-NEXT: ret - %res = call <2 x i16> @llvm.riscv.pmhacc.b1.v2i16(<2 x i16> %rd, <2 x i16> %rs1, <4 x i8> %rs2) + %res = call <2 x i16> @llvm.riscv.pmhacc.half.1.v2i16(<2 x i16> %rd, <2 x i16> %rs1, <4 x i8> %rs2) ret <2 x i16> %res } @@ -3939,7 +3939,7 @@ define <2 x i16> @test_pmhaccsu_b0_v2i16(<2 x i16> %rd, <2 x i16> %rs1, <4 x i8> ; CHECK: # %bb.0: ; CHECK-NEXT: pmhaccsu.h.b0 a0, a1, a2 ; CHECK-NEXT: ret - %res = call <2 x i16> @llvm.riscv.pmhaccsu.b0.v2i16(<2 x i16> %rd, <2 x i16> %rs1, <4 x i8> %rs2) + %res = call <2 x i16> @llvm.riscv.pmhaccsu.half.0.v2i16(<2 x i16> %rd, <2 x i16> %rs1, <4 x i8> %rs2) ret <2 x i16> %res } @@ -3948,7 +3948,7 @@ define <2 x i16> @test_pmhaccsu_b1_v2i16(<2 x i16> %rd, <2 x i16> %rs1, <4 x i8> ; CHECK: # %bb.0: ; CHECK-NEXT: pmhaccsu.h.b1 a0, a1, a2 ; CHECK-NEXT: ret - %res = call <2 x i16> @llvm.riscv.pmhaccsu.b1.v2i16(<2 x i16> %rd, <2 x i16> %rs1, <4 x i8> %rs2) + %res = call <2 x i16> @llvm.riscv.pmhaccsu.half.1.v2i16(<2 x i16> %rd, <2 x i16> %rs1, <4 x i8> %rs2) ret <2 x i16> %res } @@ -3958,7 +3958,7 @@ define <2 x i16> @test_pmulh_b0_v2i16(<2 x i16> %a, <4 x i8> %b) { ; CHECK: # %bb.0: ; CHECK-NEXT: pmulh.h.b0 a0, a0, a1 ; CHECK-NEXT: ret - %r = call <2 x i16> @llvm.riscv.pmulh.b0.v2i16(<2 x i16> %a, <4 x i8> %b) + %r = call <2 x i16> @llvm.riscv.pmulh.half.0.v2i16(<2 x i16> %a, <4 x i8> %b) ret <2 x i16> %r } @@ -3967,7 +3967,7 @@ define <2 x i16> @test_pmulh_b1_v2i16(<2 x i16> %a, <4 x i8> %b) { ; CHECK: # %bb.0: ; CHECK-NEXT: pmulh.h.b1 a0, a0, a1 ; CHECK-NEXT: ret - %r = call <2 x i16> @llvm.riscv.pmulh.b1.v2i16(<2 x i16> %a, <4 x i8> %b) + %r = call <2 x i16> @llvm.riscv.pmulh.half.1.v2i16(<2 x i16> %a, <4 x i8> %b) ret <2 x i16> %r } @@ -3976,7 +3976,7 @@ define <2 x i16> @test_pmulhsu_b0_v2i16(<2 x i16> %a, <4 x i8> %b) { ; CHECK: # %bb.0: ; CHECK-NEXT: pmulhsu.h.b0 a0, a0, a1 ; CHECK-NEXT: ret - %r = call <2 x i16> @llvm.riscv.pmulhsu.b0.v2i16(<2 x i16> %a, <4 x i8> %b) + %r = call <2 x i16> @llvm.riscv.pmulhsu.half.0.v2i16(<2 x i16> %a, <4 x i8> %b) ret <2 x i16> %r } @@ -3985,7 +3985,7 @@ define <2 x i16> @test_pmulhsu_b1_v2i16(<2 x i16> %a, <4 x i8> %b) { ; CHECK: # %bb.0: ; CHECK-NEXT: pmulhsu.h.b1 a0, a0, a1 ; CHECK-NEXT: ret - %r = call <2 x i16> @llvm.riscv.pmulhsu.b1.v2i16(<2 x i16> %a, <4 x i8> %b) + %r = call <2 x i16> @llvm.riscv.pmulhsu.half.1.v2i16(<2 x i16> %a, <4 x i8> %b) ret <2 x i16> %r } diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll index 72f1d03f237249..51d5652b42de76 100644 --- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll +++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll @@ -8288,14 +8288,14 @@ declare i64 @llvm.riscv.maccu.01.i64.v2i32(i64, <2 x i32>, <2 x i32>) declare i64 @llvm.riscv.maccu.11.i64.v2i32(i64, <2 x i32>, <2 x i32>) declare i64 @llvm.riscv.maccsu.00.i64.v2i32(i64, <2 x i32>, <2 x i32>) declare i64 @llvm.riscv.maccsu.11.i64.v2i32(i64, <2 x i32>, <2 x i32>) -declare <4 x i16> @llvm.riscv.pmhacc.b0.v4i16(<4 x i16>, <4 x i16>, <8 x i8>) -declare <4 x i16> @llvm.riscv.pmhacc.b1.v4i16(<4 x i16>, <4 x i16>, <8 x i8>) -declare <4 x i16> @llvm.riscv.pmhaccsu.b0.v4i16(<4 x i16>, <4 x i16>, <8 x i8>) -declare <4 x i16> @llvm.riscv.pmhaccsu.b1.v4i16(<4 x i16>, <4 x i16>, <8 x i8>) -declare <2 x i32> @llvm.riscv.pmhacc.h0.v2i32(<2 x i32>, <2 x i32>, <4 x i16>) -declare <2 x i32> @llvm.riscv.pmhacc.h1.v2i32(<2 x i32>, <2 x i32>, <4 x i16>) -declare <2 x i32> @llvm.riscv.pmhaccsu.h0.v2i32(<2 x i32>, <2 x i32>, <4 x i16>) -declare <2 x i32> @llvm.riscv.pmhaccsu.h1.v2i32(<2 x i32>, <2 x i32>, <4 x i16>) +declare <4 x i16> @llvm.riscv.pmhacc.half.0.v4i16(<4 x i16>, <4 x i16>, <8 x i8>) +declare <4 x i16> @llvm.riscv.pmhacc.half.1.v4i16(<4 x i16>, <4 x i16>, <8 x i8>) +declare <4 x i16> @llvm.riscv.pmhaccsu.half.0.v4i16(<4 x i16>, <4 x i16>, <8 x i8>) +declare <4 x i16> @llvm.riscv.pmhaccsu.half.1.v4i16(<4 x i16>, <4 x i16>, <8 x i8>) +declare <2 x i32> @llvm.riscv.pmhacc.half.0.v2i32(<2 x i32>, <2 x i32>, <4 x i16>) +declare <2 x i32> @llvm.riscv.pmhacc.half.1.v2i32(<2 x i32>, <2 x i32>, <4 x i16>) +declare <2 x i32> @llvm.riscv.pmhaccsu.half.0.v2i32(<2 x i32>, <2 x i32>, <4 x i16>) +declare <2 x i32> @llvm.riscv.pmhaccsu.half.1.v2i32(<2 x i32>, <2 x i32>, <4 x i16>) declare <2 x i32> @llvm.riscv.pmqwacc.i32x2(<2 x i32>, <2 x i16>, <2 x i16>) declare <2 x i32> @llvm.riscv.pmqrwacc.i32x2(<2 x i32>, <2 x i16>, <2 x i16>) @@ -8620,7 +8620,7 @@ define <4 x i16> @test_pmhacc_b0_v4i16(<4 x i16> %rd, <4 x i16> %rs1, <8 x i8> % ; RV64: # %bb.0: ; RV64-NEXT: pmhacc.h.b0 a0, a1, a2 ; RV64-NEXT: ret - %res = call <4 x i16> @llvm.riscv.pmhacc.b0.v4i16(<4 x i16> %rd, <4 x i16> %rs1, <8 x i8> %rs2) + %res = call <4 x i16> @llvm.riscv.pmhacc.half.0.v4i16(<4 x i16> %rd, <4 x i16> %rs1, <8 x i8> %rs2) ret <4 x i16> %res } @@ -8635,7 +8635,7 @@ define <4 x i16> @test_pmhacc_b1_v4i16(<4 x i16> %rd, <4 x i16> %rs1, <8 x i8> % ; RV64: # %bb.0: ; RV64-NEXT: pmhacc.h.b1 a0, a1, a2 ; RV64-NEXT: ret - %res = call <4 x i16> @llvm.riscv.pmhacc.b1.v4i16(<4 x i16> %rd, <4 x i16> %rs1, <8 x i8> %rs2) + %res = call <4 x i16> @llvm.riscv.pmhacc.half.1.v4i16(<4 x i16> %rd, <4 x i16> %rs1, <8 x i8> %rs2) ret <4 x i16> %res } @@ -8650,7 +8650,7 @@ define <4 x i16> @test_pmhaccsu_b0_v4i16(<4 x i16> %rd, <4 x i16> %rs1, <8 x i8> ; RV64: # %bb.0: ; RV64-NEXT: pmhaccsu.h.b0 a0, a1, a2 ; RV64-NEXT: ret - %res = call <4 x i16> @llvm.riscv.pmhaccsu.b0.v4i16(<4 x i16> %rd, <4 x i16> %rs1, <8 x i8> %rs2) + %res = call <4 x i16> @llvm.riscv.pmhaccsu.half.0.v4i16(<4 x i16> %rd, <4 x i16> %rs1, <8 x i8> %rs2) ret <4 x i16> %res } @@ -8665,7 +8665,7 @@ define <4 x i16> @test_pmhaccsu_b1_v4i16(<4 x i16> %rd, <4 x i16> %rs1, <8 x i8> ; RV64: # %bb.0: ; RV64-NEXT: pmhaccsu.h.b1 a0, a1, a2 ; RV64-NEXT: ret - %res = call <4 x i16> @llvm.riscv.pmhaccsu.b1.v4i16(<4 x i16> %rd, <4 x i16> %rs1, <8 x i8> %rs2) + %res = call <4 x i16> @llvm.riscv.pmhaccsu.half.1.v4i16(<4 x i16> %rd, <4 x i16> %rs1, <8 x i8> %rs2) ret <4 x i16> %res } @@ -8681,7 +8681,7 @@ define <2 x i32> @test_pmhacc_h0_v2i32(<2 x i32> %rd, <2 x i32> %rs1, <4 x i16> ; RV64: # %bb.0: ; RV64-NEXT: pmhacc.w.h0 a0, a1, a2 ; RV64-NEXT: ret - %res = call <2 x i32> @llvm.riscv.pmhacc.h0.v2i32(<2 x i32> %rd, <2 x i32> %rs1, <4 x i16> %rs2) + %res = call <2 x i32> @llvm.riscv.pmhacc.half.0.v2i32(<2 x i32> %rd, <2 x i32> %rs1, <4 x i16> %rs2) ret <2 x i32> %res } @@ -8696,7 +8696,7 @@ define <2 x i32> @test_pmhacc_h1_v2i32(<2 x i32> %rd, <2 x i32> %rs1, <4 x i16> ; RV64: # %bb.0: ; RV64-NEXT: pmhacc.w.h1 a0, a1, a2 ; RV64-NEXT: ret - %res = call <2 x i32> @llvm.riscv.pmhacc.h1.v2i32(<2 x i32> %rd, <2 x i32> %rs1, <4 x i16> %rs2) + %res = call <2 x i32> @llvm.riscv.pmhacc.half.1.v2i32(<2 x i32> %rd, <2 x i32> %rs1, <4 x i16> %rs2) ret <2 x i32> %res } @@ -8711,7 +8711,7 @@ define <2 x i32> @test_pmhaccsu_h0_v2i32(<2 x i32> %rd, <2 x i32> %rs1, <4 x i16 ; RV64: # %bb.0: ; RV64-NEXT: pmhaccsu.w.h0 a0, a1, a2 ; RV64-NEXT: ret - %res = call <2 x i32> @llvm.riscv.pmhaccsu.h0.v2i32(<2 x i32> %rd, <2 x i32> %rs1, <4 x i16> %rs2) + %res = call <2 x i32> @llvm.riscv.pmhaccsu.half.0.v2i32(<2 x i32> %rd, <2 x i32> %rs1, <4 x i16> %rs2) ret <2 x i32> %res } @@ -8726,7 +8726,7 @@ define <2 x i32> @test_pmhaccsu_h1_v2i32(<2 x i32> %rd, <2 x i32> %rs1, <4 x i16 ; RV64: # %bb.0: ; RV64-NEXT: pmhaccsu.w.h1 a0, a1, a2 ; RV64-NEXT: ret - %res = call <2 x i32> @llvm.riscv.pmhaccsu.h1.v2i32(<2 x i32> %rd, <2 x i32> %rs1, <4 x i16> %rs2) + %res = call <2 x i32> @llvm.riscv.pmhaccsu.half.1.v2i32(<2 x i32> %rd, <2 x i32> %rs1, <4 x i16> %rs2) ret <2 x i32> %res } @@ -8742,7 +8742,7 @@ define <4 x i16> @test_pmulh_b0_v4i16(<4 x i16> %a, <8 x i8> %b) { ; RV64: # %bb.0: ; RV64-NEXT: pmulh.h.b0 a0, a0, a1 ; RV64-NEXT: ret - %r = call <4 x i16> @llvm.riscv.pmulh.b0.v4i16(<4 x i16> %a, <8 x i8> %b) + %r = call <4 x i16> @llvm.riscv.pmulh.half.0.v4i16(<4 x i16> %a, <8 x i8> %b) ret <4 x i16> %r } @@ -8757,7 +8757,7 @@ define <4 x i16> @test_pmulh_b1_v4i16(<4 x i16> %a, <8 x i8> %b) { ; RV64: # %bb.0: ; RV64-NEXT: pmulh.h.b1 a0, a0, a1 ; RV64-NEXT: ret - %r = call <4 x i16> @llvm.riscv.pmulh.b1.v4i16(<4 x i16> %a, <8 x i8> %b) + %r = call <4 x i16> @llvm.riscv.pmulh.half.1.v4i16(<4 x i16> %a, <8 x i8> %b) ret <4 x i16> %r } @@ -8772,7 +8772,7 @@ define <4 x i16> @test_pmulhsu_b0_v4i16(<4 x i16> %a, <8 x i8> %b) { ; RV64: # %bb.0: ; RV64-NEXT: pmulhsu.h.b0 a0, a0, a1 ; RV64-NEXT: ret - %r = call <4 x i16> @llvm.riscv.pmulhsu.b0.v4i16(<4 x i16> %a, <8 x i8> %b) + %r = call <4 x i16> @llvm.riscv.pmulhsu.half.0.v4i16(<4 x i16> %a, <8 x i8> %b) ret <4 x i16> %r } @@ -8787,7 +8787,7 @@ define <4 x i16> @test_pmulhsu_b1_v4i16(<4 x i16> %a, <8 x i8> %b) { ; RV64: # %bb.0: ; RV64-NEXT: pmulhsu.h.b1 a0, a0, a1 ; RV64-NEXT: ret - %r = call <4 x i16> @llvm.riscv.pmulhsu.b1.v4i16(<4 x i16> %a, <8 x i8> %b) + %r = call <4 x i16> @llvm.riscv.pmulhsu.half.1.v4i16(<4 x i16> %a, <8 x i8> %b) ret <4 x i16> %r } @@ -8802,7 +8802,7 @@ define <2 x i32> @test_pmulh_h0_v2i32(<2 x i32> %a, <4 x i16> %b) { ; RV64: # %bb.0: ; RV64-NEXT: pmulh.w.h0 a0, a0, a1 ; RV64-NEXT: ret - %r = call <2 x i32> @llvm.riscv.pmulh.h0.v2i32(<2 x i32> %a, <4 x i16> %b) + %r = call <2 x i32> @llvm.riscv.pmulh.half.0.v2i32(<2 x i32> %a, <4 x i16> %b) ret <2 x i32> %r } @@ -8817,7 +8817,7 @@ define <2 x i32> @test_pmulh_h1_v2i32(<2 x i32> %a, <4 x i16> %b) { ; RV64: # %bb.0: ; RV64-NEXT: pmulh.w.h1 a0, a0, a1 ; RV64-NEXT: ret - %r = call <2 x i32> @llvm.riscv.pmulh.h1.v2i32(<2 x i32> %a, <4 x i16> %b) + %r = call <2 x i32> @llvm.riscv.pmulh.half.1.v2i32(<2 x i32> %a, <4 x i16> %b) ret <2 x i32> %r } @@ -8832,7 +8832,7 @@ define <2 x i32> @test_pmulhsu_h0_v2i32(<2 x i32> %a, <4 x i16> %b) { ; RV64: # %bb.0: ; RV64-NEXT: pmulhsu.w.h0 a0, a0, a1 ; RV64-NEXT: ret - %r = call <2 x i32> @llvm.riscv.pmulhsu.h0.v2i32(<2 x i32> %a, <4 x i16> %b) + %r = call <2 x i32> @llvm.riscv.pmulhsu.half.0.v2i32(<2 x i32> %a, <4 x i16> %b) ret <2 x i32> %r } @@ -8847,7 +8847,7 @@ define <2 x i32> @test_pmulhsu_h1_v2i32(<2 x i32> %a, <4 x i16> %b) { ; RV64: # %bb.0: ; RV64-NEXT: pmulhsu.w.h1 a0, a0, a1 ; RV64-NEXT: ret - %r = call <2 x i32> @llvm.riscv.pmulhsu.h1.v2i32(<2 x i32> %a, <4 x i16> %b) + %r = call <2 x i32> @llvm.riscv.pmulhsu.half.1.v2i32(<2 x i32> %a, <4 x i16> %b) ret <2 x i32> %r } _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
