Author: ctopper
Date: Wed Dec 27 14:25:59 2017
New Revision: 321502
URL: http://llvm.org/viewvc/llvm-project?rev=321502&view=rev
Log:
[X86] Enable avx512vpopcntdq and clwb for icelake.
Per table 1-1 of the October 2017 edition of Intel® Architecture Instruction
Set Extensions and Future Features Programming Reference
Modified:
cfe/trunk/lib/Basic/Targets/X86.cpp
cfe/trunk/test/Preprocessor/predefined-arch-macros.c
Modified: cfe/trunk/lib/Basic/Targets/X86.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/X86.cpp?rev=321502&r1=321501&r2=321502&view=diff
==============================================================================
--- cfe/trunk/lib/Basic/Targets/X86.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/X86.cpp Wed Dec 27 14:25:59 2017
@@ -132,13 +132,14 @@ bool X86TargetInfo::initFeatureMap(
break;
case CK_Icelake:
- // TODO: Add icelake features here.
setFeatureEnabledImpl(Features, "vaes", true);
setFeatureEnabledImpl(Features, "gfni", true);
setFeatureEnabledImpl(Features, "vpclmulqdq", true);
setFeatureEnabledImpl(Features, "avx512bitalg", true);
setFeatureEnabledImpl(Features, "avx512vnni", true);
setFeatureEnabledImpl(Features, "avx512vbmi2", true);
+ setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
+ setFeatureEnabledImpl(Features, "clwb", true);
LLVM_FALLTHROUGH;
case CK_Cannonlake:
setFeatureEnabledImpl(Features, "avx512ifma", true);
Modified: cfe/trunk/test/Preprocessor/predefined-arch-macros.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Preprocessor/predefined-arch-macros.c?rev=321502&r1=321501&r2=321502&view=diff
==============================================================================
--- cfe/trunk/test/Preprocessor/predefined-arch-macros.c (original)
+++ cfe/trunk/test/Preprocessor/predefined-arch-macros.c Wed Dec 27 14:25:59
2017
@@ -1060,10 +1060,12 @@
// CHECK_ICL_M32: #define __AVX512VBMI__ 1
// CHECK_ICL_M32: #define __AVX512VL__ 1
// CHECK_ICL_M32: #define __AVX512VNNI__ 1
+// CHECK_ICL_M32: #define __AVX512VPOPCNTDQ__ 1
// CHECK_ICL_M32: #define __AVX__ 1
// CHECK_ICL_M32: #define __BMI2__ 1
// CHECK_ICL_M32: #define __BMI__ 1
// CHECK_ICL_M32: #define __CLFLUSHOPT__ 1
+// CHECK_ICL_M32: #define __CLWB__ 1
// CHECK_ICL_M32: #define __F16C__ 1
// CHECK_ICL_M32: #define __FMA__ 1
// CHECK_ICL_M32: #define __GFNI__ 1
@@ -1111,10 +1113,12 @@
// CHECK_ICL_M64: #define __AVX512VBMI__ 1
// CHECK_ICL_M64: #define __AVX512VL__ 1
// CHECK_ICL_M64: #define __AVX512VNNI__ 1
+// CHECK_ICL_M64: #define __AVX512VPOPCNTDQ__ 1
// CHECK_ICL_M64: #define __AVX__ 1
// CHECK_ICL_M64: #define __BMI2__ 1
// CHECK_ICL_M64: #define __BMI__ 1
// CHECK_ICL_M64: #define __CLFLUSHOPT__ 1
+// CHECK_ICL_M64: #define __CLWB__ 1
// CHECK_ICL_M64: #define __F16C__ 1
// CHECK_ICL_M64: #define __FMA__ 1
// CHECK_ICL_M64: #define __GFNI__ 1
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