mgrang added a comment.

Here is a test case which improves with this patch (for RISCV target). It is 
able to detect load/store halfword for size 16 bitfields.

  struct st {
    int a:1;
    int b:8;
    int c:11;
    int d:12;
    int e:16;
    int f:16;
    int g:16;
  } S;
  
  void foo(int x) {
    S.e = x;
  }

GCC:

  00000000 <foo>:
     0: 000007b7                lui     x15,0x0
     4: 00a79223                sh      x10,4(x15) # 4 <foo+0x4>
     8: 00008067                jalr    x0,0(x1)

LLVM without this patch:

  00000000 <foo>:
     0: 000105b7                lui     x11,0x10
     4: fff58593                addi    x11,x11,-1 # ffff <foo+0xffff>
     8: 00b57533                and     x10,x10,x11
     c: 000005b7                lui     x11,0x0
    10: 00058593                addi    x11,x11,0 # 0 <foo>
    14: 0045a603                lw      x12,4(x11)
    18: ffff06b7                lui     x13,0xffff0
    1c: 00d67633                and     x12,x12,x13
    20: 00a66533                or      x10,x12,x10
    24: 00a5a223                sw      x10,4(x11)
    28: 00008067                jalr    x0,0(x1)

LLVM with this patch:

  00000000 <foo>:
     0: 000005b7                lui     x11,0x0
     4: 00058593                addi    x11,x11,0 # 0 <foo>
     8: 00a59223                sh      x10,4(x11)
     c: 00008067                jalr    x0,0(x1)




https://reviews.llvm.org/D39053



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