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here is the log from the commit of package CoreFreq for openSUSE:Factory 
checked in at 2024-08-13 13:24:11
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/CoreFreq (Old)
 and      /work/SRC/openSUSE:Factory/.CoreFreq.new.7232 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Package is "CoreFreq"

Tue Aug 13 13:24:11 2024 rev:35 rq:1193475 version:1.98.2

Changes:
--------
--- /work/SRC/openSUSE:Factory/CoreFreq/CoreFreq.changes        2024-08-08 
10:58:38.176206881 +0200
+++ /work/SRC/openSUSE:Factory/.CoreFreq.new.7232/CoreFreq.changes      
2024-08-13 13:24:48.354150960 +0200
@@ -1,0 +2,28 @@
+Mon Aug 12 15:07:52 UTC 2024 - Michael Pujos <pujos.mich...@gmail.com>
+
+- Update to 1.98.2
+  * [Intel]
+    - [WDT] Adding multiple devices to probe TCO
+        C620 Series Chipset Production SKUs (0xa1a3)
+        C620 Series Chipset Super SKUs (0xa223)
+        Sunrise Point/H (0xa123)
+        Cannon Lake/LP (0x9da3)
+        Comet Lake/H (0x06a3)
+        Ice Lake/LP (0x34a3)
+        Tiger Lake/H (0x43a3)
+        Elkhart Lake (0x4b23)
+        Kaby Lake/H (0xa2a3)
+        Cannon Lake (0xa323)
+        Comet Lake/V (0xa3a3)
+        Ice Lake/NG (0x38a3)
+        Alder lake/M (0x54a3)
+        Arrow Lake/S (0x7f23)
+        Jasper Lake SMBus (0x4da3)
+        Sunrise Point-LP SMBus (0x9d23)
+        Comet Lake PCH-LP SMBus (0x02a3)
+    - MSR_FLEX_RATIO register
+        Grant access to Alder Lake/H (06_9A)
+        Deny access to Nehalem/Bloomfield (06_1A)
+        Removed a condition in access function
+
+-------------------------------------------------------------------

Old:
----
  CoreFreq-1.98.1.tar.gz

New:
----
  CoreFreq-1.98.2.tar.gz

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Other differences:
------------------
++++++ CoreFreq.spec ++++++
--- /var/tmp/diff_new_pack.LFhyRd/_old  2024-08-13 13:24:49.006178127 +0200
+++ /var/tmp/diff_new_pack.LFhyRd/_new  2024-08-13 13:24:49.006178127 +0200
@@ -17,7 +17,7 @@
 
 
 Name:           CoreFreq
-Version:        1.98.1
+Version:        1.98.2
 Release:        0
 Summary:        CPU monitoring software for 64-bit processors
 License:        GPL-2.0-or-later

++++++ CoreFreq-1.98.1.tar.gz -> CoreFreq-1.98.2.tar.gz ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' 
'--exclude=.svnignore' old/CoreFreq-1.98.1/Makefile new/CoreFreq-1.98.2/Makefile
--- old/CoreFreq-1.98.1/Makefile        2024-08-06 19:01:28.000000000 +0200
+++ new/CoreFreq-1.98.2/Makefile        2024-08-12 00:35:24.000000000 +0200
@@ -4,7 +4,7 @@
 
 COREFREQ_MAJOR = 1
 COREFREQ_MINOR = 98
-COREFREQ_REV = 1
+COREFREQ_REV = 2
 HW = $(shell uname -m)
 CC ?= cc
 WARNING = -Wall -Wfatal-errors
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' 
'--exclude=.svnignore' old/CoreFreq-1.98.1/x86_64/corefreq-api.h 
new/CoreFreq-1.98.2/x86_64/corefreq-api.h
--- old/CoreFreq-1.98.1/x86_64/corefreq-api.h   2024-08-06 19:01:28.000000000 
+0200
+++ new/CoreFreq-1.98.2/x86_64/corefreq-api.h   2024-08-12 00:35:24.000000000 
+0200
@@ -1228,6 +1228,9 @@
 #define DID_INTEL_X58_HUB_CORE         0x342e
 #define DID_INTEL_X58_HUB_CTRL         0x3423
 #define DID_INTEL_IIO_CORE_REG         0x3728
+/* Source: Intel Corporation Elkhart Lake SMBus and Jasper Lake SMBus  */
+#define DID_INTEL_EHL_SMBUS            0x4b23
+#define DID_INTEL_JSL_SMBUS            0x4da3
 /* Source: /include/linux/pci_ids.h                                    */
 #define DID_INTEL_SNB_IMC_HA0          0x3ca0
 /* Source: 2nd Generation Intel Core Processor Family Vol2             */
@@ -1381,6 +1384,9 @@
 #define DID_INTEL_SKYLAKE_H_IMC_HAQ    0x1910
 /* Source: Intel Xeon Processor E3-1200 v5 Product Family              */
 #define DID_INTEL_SKYLAKE_DT_IMC_HA    0x1918
+/* Source: Intel C620 Series Chipset Platform Controller Hub Datasheet */
+#define DID_INTEL_C620_PCH_SMBUS       0xa1a3
+#define DID_INTEL_C620_SUPER_SMBUS     0xa223
 /* Source:7th Generation Intel Processor for S-Platforms & Core X-Series Vol2*/
 #define DID_INTEL_KABYLAKE_H_IMC_HAD   0x5900
 #define DID_INTEL_KABYLAKE_U_IMC_HA    0x5904
@@ -1392,6 +1398,10 @@
 #define DID_INTEL_KABYLAKE_U_IMC_HAQ   0x5914
 #define DID_INTEL_KABYLAKE_S_IMC_HAQ   0x591f
 #define DID_INTEL_KABYLAKE_X_IMC_HAQ   0x5906
+#define DID_INTEL_KBL_PCH_H_SMBUS      0xa2a3
+/* Source: Hewlett-Packard Company - Sunrise Point-LP SMBus            */
+#define DID_INTEL_SPT_LP_SMBUS         0x9d23
+#define DID_INTEL_SPT_H_PCH_SMBUS      0xa123
 /* Source: 8th Generation Intel Processor for S-Platforms Datasheet Vol2 */
 #define DID_INTEL_COFFEELAKE_S_IMC_HAQ 0x3e1f
 #define DID_INTEL_COFFEELAKE_S_IMC_HAS 0x3ec2
@@ -1412,6 +1422,12 @@
 #define DID_INTEL_WHISKEYLAKE_U_IMC_HAD 0x3e35
 #define DID_INTEL_WHISKEYLAKE_U_IMC_HAQ 0x3e34
 #define DID_INTEL_CANNONLAKE_U_IMC_HB  0x5a04
+#define DID_INTEL_CNL_PCH_LP_SMBUS     0x9da3
+#define DID_INTEL_CNL_PCH_SMBUS        0xa323
+/* Source: Comet Lake PCH-LP SMBus and PCH-V SMBus Host Controllers    */
+#define DID_INTEL_CML_PCH_LP_SMBUS     0x02a3
+#define DID_INTEL_CML_PCH_V_SMBUS      0xa3a3
+#define DID_INTEL_CML_H_PCH_SMBUS      0x06a3
 /* Source: Intel 400 Series Chipset Family On-Package Platform Controller Hub 
*/
 #define DID_INTEL_COMETLAKE_S_IMC_6C   0x9b53
 #define DID_INTEL_COMETLAKE_S_IMC_10C  0x9b54
@@ -1433,6 +1449,9 @@
 #define DID_INTEL_COMETLAKE_W480_PCH   0x0697
 #define DID_INTEL_ICELAKE_U_4C         0x8a12
 #define DID_INTEL_ICELAKE_U_PCH        0x3482
+#define DID_INTEL_ICL_LP_SMBUS         0x34a3
+/* Source: Apple MacBook Air/Pro - Intel Core i5-1038NG7               */
+#define DID_INTEL_ICL_PCH_NG_SMBUS     0x38a3
 /* Source: Linux: arch/x86/events/intel/uncore_snb.c                   */
 #define DID_INTEL_COMETLAKE_U1_IMC     0x9b51
 #define DID_INTEL_COMETLAKE_U3_IMC     0x9b71
@@ -1449,6 +1468,7 @@
 #define DID_INTEL_TIGERLAKE_UP3_IMC    0xa082
 #define DID_INTEL_TIGERLAKE_UP4_IMC    0xa087
 #define DID_INTEL_TGL_PCH_LP_SMBUS     0xa0a3 /* TGL-LP Watchdog       */
+#define DID_INTEL_TGL_H_PCH_SMBUS      0x43a3
 #define DID_INTEL_ROCKETLAKE_S_8C_IMC_HB 0x4c43
 #define DID_INTEL_ROCKETLAKE_S_6C_IMC_HB 0x4c53
 /* Source: Intel 500 Series Chipset Family Platform Controller Hub     */
@@ -1486,6 +1506,7 @@
 #define DID_INTEL_ALDERLAKE_PCH_P      0x5182 /* PCH eSPI Controller   */
 #define DID_INTEL_ALDERLAKE_PCH_U      0x5188 /* PCH-U eSPI Controller */
 #define DID_INTEL_ADL_PCH_P_SMBUS      0x51a3 /* ADL PCH-P Watchdog    */
+#define DID_INTEL_ADL_PCH_M_SMBUS      0x54a3 /* ADL PCH-M Watchdog    */
 #define DID_INTEL_ADL_S_PCH_SMBUS      0x7aa3
 /* Source: 13th Generation Intel Core Processors Datasheet, vol 1      */
 #define DID_INTEL_RAPTORLAKE_S_8P_16E_HB 0xa700
@@ -1533,6 +1554,8 @@
 #define DID_INTEL_METEORLAKE_H_PCH     0x7e02
 #define DID_INTEL_METEORLAKE_U_PCH     0x7e03
 #define DID_INTEL_METEORLAKE_UT4_PCH   0x7e07
+/* Source: Arrow Lake Client Platform/MTL-S (0x6-0xc6, stepping: 0x0)  */
+#define DID_INTEL_ARL_MTL_PCH_S_SMBUS  0x7f23
 /* Source: /include/linux/pci_ids.h                                    */
 #define DID_AMD_K8_NB_MEMCTL           0x1102
 #define DID_AMD_K8_NB                  0x1100
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' 
'--exclude=.svnignore' old/CoreFreq-1.98.1/x86_64/corefreqk.c 
new/CoreFreq-1.98.2/x86_64/corefreqk.c
--- old/CoreFreq-1.98.1/x86_64/corefreqk.c      2024-08-06 19:01:28.000000000 
+0200
+++ new/CoreFreq-1.98.2/x86_64/corefreqk.c      2024-08-12 00:35:24.000000000 
+0200
@@ -2686,9 +2686,8 @@
        return NULL;
 }
 
-static void Intel_FlexRatio(bool OC_ENABLED)
+static void Intel_FlexRatio(void)
 {
-  if (OC_ENABLED) {
     static struct {
                struct SIGNATURE Arch;
                unsigned short  grantFlex       :  1-0,
@@ -2718,13 +2717,13 @@
                {_Atom_Merrifield,      1, 1, 0, 0},    /* 06_4A */
                {_Atom_Moorefield,      1, 1, 0, 0},    /* 06_5A */
 
-               {_Nehalem_Bloomfield,   1, 1, 0, 1},    /* 06_1A */
+               {_Nehalem_Bloomfield,   0, 0, 0, 1},    /* 06_1A */
                {_Nehalem_Lynnfield,    1, 1, 0, 1},    /* 06_1E */
                {_Nehalem_MB,           1, 1, 0, 1},    /* 06_1F */
                {_Nehalem_EX,           1, 1, 0, 1},    /* 06_2E */
 
                {_Westmere,             1, 1, 0, 1},    /* 06_25 */
-               {_Westmere_EP,          1, 0, 0, 1},    /* 06_2C */
+               {_Westmere_EP,          1, 0, 0, 1},    /* 06_2C : R/W */
                {_Westmere_EX,          1, 1, 0, 1},    /* 06_2F */
 
                {_SandyBridge,          1, 1, 0, 0},    /* 06_2A */
@@ -2761,7 +2760,7 @@
                {_Icelake_D,            1, 1, 0, 0},
                {_Sunny_Cove,           1, 1, 0, 0},
                {_Tigerlake,            1, 1, 0, 0},
-               {_Tigerlake_U,          1, 0, 0, 0},    /* 06_8C */
+               {_Tigerlake_U,          1, 0, 0, 0},    /* 06_8C : R/W */
                {_Cometlake,            1, 1, 0, 0},
                {_Cometlake_UY,         1, 1, 0, 0},
                {_Atom_Denverton,       1, 1, 0, 0},
@@ -2778,7 +2777,7 @@
                {_Rocketlake,           1, 1, 0, 0},
                {_Rocketlake_U,         1, 1, 0, 0},
                {_Alderlake_S,          1, 0, 0, 0},    /* 06_97 */
-               {_Alderlake_H,          1, 1, 0, 0},
+               {_Alderlake_H,          1, 0, 0, 0},    /* 06_9A */
                {_Alderlake_N,          1, 1, 0, 0},
                {_Meteorlake_M,         1, 1, 0, 0},
                {_Meteorlake_N,         1, 1, 0, 0},
@@ -2830,7 +2829,6 @@
        break;
     }
    }
-  }
 }
 
 static int Intel_MaxBusRatio(PLATFORM_ID *PfID)
@@ -6040,7 +6038,7 @@
        pci_read_config_dword(dev, 0xd0,
                                &PUBLIC(RO(Proc))->Uncore.Bus.QuickPath.value);
 
-       Intel_FlexRatio(true);
+       Intel_FlexRatio();
 
        return (PCI_CALLBACK) 0;
 }
@@ -6089,7 +6087,7 @@
        pci_read_config_dword(dev, 0xe8,
                                &PUBLIC(RO(Proc))->Uncore.Bus.IVB_Cap.value);
 
-       Intel_FlexRatio(PUBLIC(RO(Proc))->Uncore.Bus.IVB_Cap.OC_ENABLED == 1);
+       Intel_FlexRatio();
 
        PUBLIC(RO(Proc))->Uncore.CtrlCount = 1;
 
@@ -6291,7 +6289,7 @@
        pci_read_config_dword(dev, 0xe8,
                                &PUBLIC(RO(Proc))->Uncore.Bus.IVB_Cap.value);
 
-       Intel_FlexRatio(PUBLIC(RO(Proc))->Uncore.Bus.IVB_Cap.OC_ENABLED == 1);
+       Intel_FlexRatio();
 
        PUBLIC(RO(Proc))->Uncore.CtrlCount = 1;
 
@@ -6534,7 +6532,7 @@
        pci_read_config_dword(dev, 0xec,
                                &PUBLIC(RO(Proc))->Uncore.Bus.SKL_Cap_C.value);
 
-       Intel_FlexRatio(PUBLIC(RO(Proc))->Uncore.Bus.SKL_Cap_B.OC_ENABLED == 1);
+       Intel_FlexRatio();
 
        SoC_SKL_VTD();
 
@@ -6599,7 +6597,7 @@
        pci_read_config_dword(dev, 0xf0,
                                &PUBLIC(RO(Proc))->Uncore.Bus.ADL_Cap_E.value);
 
-       Intel_FlexRatio(PUBLIC(RO(Proc))->Uncore.Bus.ADL_Cap_B.OC_ENABLED == 1);
+       Intel_FlexRatio();
 
        SoC_SKL_VTD();
 
@@ -6656,7 +6654,7 @@
        pci_read_config_dword(dev, 0xf0,
                                &PUBLIC(RO(Proc))->Uncore.Bus.MTL_Cap_E.value);
 
-       Intel_FlexRatio(PUBLIC(RO(Proc))->Uncore.Bus.MTL_Cap_B.OC_ENABLED == 1);
+       Intel_FlexRatio();
 
        SoC_SKL_VTD();
 
@@ -6706,7 +6704,7 @@
        pci_read_config_dword(dev, 0xe8,
                                &PUBLIC(RO(Proc))->Uncore.Bus.GLK_Cap_B.value);
 
-       Intel_FlexRatio(PUBLIC(RO(Proc))->Uncore.Bus.GLK_Cap_B.OC_ENABLED == 1);
+       Intel_FlexRatio();
 
        SoC_SKL_VTD();
 
@@ -10376,14 +10374,78 @@
                .driver_data = (kernel_ulong_t) ICH_TCO
                },
                {
+               PCI_VDEVICE(INTEL, DID_INTEL_EHL_SMBUS),
+               .driver_data = (kernel_ulong_t) TCOBASE
+               },
+               {
+               PCI_VDEVICE(INTEL, DID_INTEL_JSL_SMBUS),
+               .driver_data = (kernel_ulong_t) TCOBASE
+               },
+               {
+               PCI_VDEVICE(INTEL, DID_INTEL_C620_PCH_SMBUS),
+               .driver_data = (kernel_ulong_t) TCOBASE
+               },
+               {
+               PCI_VDEVICE(INTEL, DID_INTEL_C620_SUPER_SMBUS),
+               .driver_data = (kernel_ulong_t) TCOBASE
+               },
+               {
+               PCI_VDEVICE(INTEL, DID_INTEL_KBL_PCH_H_SMBUS),
+               .driver_data = (kernel_ulong_t) TCOBASE
+               },
+               {
+               PCI_VDEVICE(INTEL, DID_INTEL_SPT_LP_SMBUS),
+               .driver_data = (kernel_ulong_t) TCOBASE
+               },
+               {
+               PCI_VDEVICE(INTEL, DID_INTEL_SPT_H_PCH_SMBUS),
+               .driver_data = (kernel_ulong_t) TCOBASE
+               },
+               {
+               PCI_VDEVICE(INTEL, DID_INTEL_CNL_PCH_LP_SMBUS),
+               .driver_data = (kernel_ulong_t) TCOBASE
+               },
+               {
+               PCI_VDEVICE(INTEL, DID_INTEL_CNL_PCH_SMBUS),
+               .driver_data = (kernel_ulong_t) TCOBASE
+               },
+               {
+               PCI_VDEVICE(INTEL, DID_INTEL_CML_PCH_LP_SMBUS),
+               .driver_data = (kernel_ulong_t) TCOBASE
+               },
+               {
+               PCI_VDEVICE(INTEL, DID_INTEL_CML_PCH_V_SMBUS),
+               .driver_data = (kernel_ulong_t) TCOBASE
+               },
+               {
+               PCI_VDEVICE(INTEL, DID_INTEL_CML_H_PCH_SMBUS),
+               .driver_data = (kernel_ulong_t) TCOBASE
+               },
+               {
+               PCI_VDEVICE(INTEL, DID_INTEL_ICL_LP_SMBUS),
+               .driver_data = (kernel_ulong_t) TCOBASE
+               },
+               {
+               PCI_VDEVICE(INTEL, DID_INTEL_ICL_PCH_NG_SMBUS),
+               .driver_data = (kernel_ulong_t) TCOBASE
+               },
+               {
                PCI_VDEVICE(INTEL, DID_INTEL_TGL_PCH_LP_SMBUS),
                .driver_data = (kernel_ulong_t) TCOBASE
                },
                {
+               PCI_VDEVICE(INTEL, DID_INTEL_TGL_H_PCH_SMBUS),
+               .driver_data = (kernel_ulong_t) TCOBASE
+               },
+               {
                PCI_VDEVICE(INTEL, DID_INTEL_ADL_PCH_P_SMBUS),
                .driver_data = (kernel_ulong_t) TCOBASE
                },
                {
+               PCI_VDEVICE(INTEL, DID_INTEL_ADL_PCH_M_SMBUS),
+               .driver_data = (kernel_ulong_t) TCOBASE
+               },
+               {
                PCI_VDEVICE(INTEL, DID_INTEL_ADL_S_PCH_SMBUS),
                .driver_data = (kernel_ulong_t) TCOBASE
                },
@@ -10391,6 +10453,10 @@
                PCI_VDEVICE(INTEL, DID_INTEL_RPL_D_PCH_SMBUS),
                .driver_data = (kernel_ulong_t) TCOBASE
                },
+               {
+               PCI_VDEVICE(INTEL, DID_INTEL_ARL_MTL_PCH_S_SMBUS),
+               .driver_data = (kernel_ulong_t) TCOBASE
+               },
                {0, }
        };
        if (CoreFreqK_ProbePCI(PCI_WDT_ids, NULL, NULL) < RC_SUCCESS) {

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