Script 'mail_helper' called by obssrc
Hello community,
here is the log from the commit of package CoreFreq for openSUSE:Factory
checked in at 2024-11-17 16:42:05
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/CoreFreq (Old)
and /work/SRC/openSUSE:Factory/.CoreFreq.new.2017 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "CoreFreq"
Sun Nov 17 16:42:05 2024 rev:39 rq:1224578 version:1.98.6
Changes:
--------
--- /work/SRC/openSUSE:Factory/CoreFreq/CoreFreq.changes 2024-11-09
20:57:55.033287846 +0100
+++ /work/SRC/openSUSE:Factory/.CoreFreq.new.2017/CoreFreq.changes
2024-11-17 16:42:10.957684689 +0100
@@ -1,0 +2,25 @@
+Sat Nov 16 14:22:18 UTC 2024 - Michael Pujos <pujos.mich...@gmail.com>
+
+- Update to 1.98.6
+ * [AMD]
+ - [V2000 Series] Adding the Ryzen Embedded V2A46
+ - [Family 1Ah][All Families] Refactoring topology for CCD cluster
+ Confirmed 7950X, 3950X
+ * [Intel]
+ - ODCM is confirmed working on Raptor Lake architecture
+ Confirmed i9-14900K
+ * [UI]
+ - Increased max ratio in HWP condition to avoid a zero frequency
+ Confirmed i9-14900K
+ * [Build]
+ - Print other variables from Makefile recipe info
+ CORE_COUNT
+ TASK_ORDER
+ MAX_FREQ_HZ
+ HWM_CHIPSET
+ * [CI]
+ - [AArch64] Commenting out the debian-testing and alpine-latest
+ * [Doc]
+ - Mention the AMD family 1Ah support in README
+
+-------------------------------------------------------------------
Old:
----
CoreFreq-1.98.5.tar.gz
New:
----
CoreFreq-1.98.6.tar.gz
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ CoreFreq.spec ++++++
--- /var/tmp/diff_new_pack.9Sv5Ky/_old 2024-11-17 16:42:11.777718751 +0100
+++ /var/tmp/diff_new_pack.9Sv5Ky/_new 2024-11-17 16:42:11.777718751 +0100
@@ -17,7 +17,7 @@
Name: CoreFreq
-Version: 1.98.5
+Version: 1.98.6
Release: 0
Summary: CPU monitoring software for 64-bit processors
License: GPL-2.0-or-later
++++++ CoreFreq-1.98.5.tar.gz -> CoreFreq-1.98.6.tar.gz ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.5/.github/workflows/build.yml
new/CoreFreq-1.98.6/.github/workflows/build.yml
--- old/CoreFreq-1.98.5/.github/workflows/build.yml 2024-11-01
08:57:26.000000000 +0100
+++ new/CoreFreq-1.98.6/.github/workflows/build.yml 2024-11-16
13:35:40.000000000 +0100
@@ -56,10 +56,10 @@
# base_image: amd64/fedora:26
# packages: kernel-devel
- - arch: aarch64
- distro: debian-testing
- base_image: arm64v8/debian:testing
- packages: linux-headers-arm64
+ #- arch: aarch64
+ # distro: debian-testing
+ # base_image: arm64v8/debian:testing
+ # packages: linux-headers-arm64
- arch: aarch64
distro: debian-10-buster
base_image: arm64v8/debian:10
@@ -76,10 +76,10 @@
distro: ubuntu-14.04-trusty
base_image: arm64v8/ubuntu:14.04
packages: linux-headers-generic
- - arch: aarch64
- distro: alpine-latest
- base_image: arm64v8/alpine:latest
- packages: linux-virt-dev
+ #- arch: aarch64
+ # distro: alpine-latest
+ # base_image: arm64v8/alpine:latest
+ # packages: linux-virt-dev
#- arch: aarch64
# distro: alpine-3.10
# base_image: arm64v8/alpine:3.10
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.5/Makefile new/CoreFreq-1.98.6/Makefile
--- old/CoreFreq-1.98.5/Makefile 2024-11-01 08:57:26.000000000 +0100
+++ new/CoreFreq-1.98.6/Makefile 2024-11-16 13:35:40.000000000 +0100
@@ -4,7 +4,7 @@
COREFREQ_MAJOR = 1
COREFREQ_MINOR = 98
-COREFREQ_REV = 5
+COREFREQ_REV = 6
HW = $(shell uname -m)
CC ?= cc
WARNING = -Wall -Wfatal-errors
@@ -318,6 +318,10 @@
$(info FEAT_DBG [$(FEAT_DBG)])
$(info DELAY_TSC [$(DELAY_TSC)])
$(info OPTIM_LVL [$(OPTIM_LVL)])
+ $(info CORE_COUNT [$(CORE_COUNT)])
+ $(info TASK_ORDER [$(TASK_ORDER)])
+ $(info MAX_FREQ_HZ [$(MAX_FREQ_HZ)])
+ $(info HWM_CHIPSET [$(HWM_CHIPSET)])
$(info MSR_CORE_PERF_UCC [$(MSR_CORE_PERF_UCC)])
$(info MSR_CORE_PERF_URC [$(MSR_CORE_PERF_URC)])
$(info ARCH_PMC [$(ARCH_PMC)])
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.5/README.md
new/CoreFreq-1.98.6/README.md
--- old/CoreFreq-1.98.5/README.md 2024-11-01 08:57:26.000000000 +0100
+++ new/CoreFreq-1.98.6/README.md 2024-11-16 13:35:40.000000000 +0100
@@ -1,6 +1,6 @@
# _CoreFreq_
## Purpose
-_CoreFreq_, a CPU monitoring software with BIOS like functionalities, is
designed for the 64-bits Processors of architecture Intel Atom, Core2, Nehalem,
SandyBridge and superiors; AMD Families from 0Fh ... up to 17h (Zen , Zen+ ,
Zen 2), 18h (Hygon Dhyana), 19h (Zen 3, Zen 3+, Zen 4, Zen 4c); Arm A64
+_CoreFreq_, CPU monitoring software with BIOS like functionalities, is
designed for the 64-bits Processors of architecture Intel Atom, Core2, Nehalem,
SandyBridge and superiors; AMD Families from 0Fh ... up to 17h (Zen , Zen+ ,
Zen 2), 18h (Hygon Dhyana), 19h (Zen 3, Zen 3+, Zen 4, Zen 4c), 1Ah (Zen 5, Zen
5c); Arm A64
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.5/aarch64/corefreq-cli.c
new/CoreFreq-1.98.6/aarch64/corefreq-cli.c
--- old/CoreFreq-1.98.5/aarch64/corefreq-cli.c 2024-11-01 08:57:26.000000000
+0100
+++ new/CoreFreq-1.98.6/aarch64/corefreq-cli.c 2024-11-16 13:35:40.000000000
+0100
@@ -2907,8 +2907,7 @@
CFlop->Clock
);
- const unsigned int maxRatio = MAXCLOCK_TO_RATIO(unsigned int,
- CFlop->Clock.Hz);
+ const unsigned int maxRatio = 99;
if (StrLenFormat(length, item, grid->cell.length + 1,
"CPU #%-3u %7.2f (%3u) %7.2f (%3u) %7.2f (%3u) %7.2f (%3u)",
@@ -3190,8 +3189,7 @@
CFlop->Clock
);
- const unsigned int maxRatio = MAXCLOCK_TO_RATIO(unsigned int,
- CFlop->Clock.Hz);
+ const unsigned int maxRatio = 99;
GridCall(
PUT(SCANKEY_NULL, HWP_Cap_Attr[bix], width, 3,
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.5/x86_64/corefreq-cli.c
new/CoreFreq-1.98.6/x86_64/corefreq-cli.c
--- old/CoreFreq-1.98.5/x86_64/corefreq-cli.c 2024-11-01 08:57:26.000000000
+0100
+++ new/CoreFreq-1.98.6/x86_64/corefreq-cli.c 2024-11-16 13:35:40.000000000
+0100
@@ -4714,8 +4714,7 @@
CFlop->Clock
);
- const unsigned int maxRatio = MAXCLOCK_TO_RATIO(unsigned int,
- CFlop->Clock.Hz);
+ const unsigned int maxRatio = 99;
if (StrLenFormat(length, item, grid->cell.length + 1,
"CPU #%-3u %7.2f (%3u) %7.2f (%3u) %7.2f (%3u) %7.2f (%3u)",
@@ -5366,8 +5365,7 @@
CFlop->Clock
);
- const unsigned int maxRatio = MAXCLOCK_TO_RATIO(unsigned int,
- CFlop->Clock.Hz);
+ const unsigned int maxRatio = 99;
GridCall(
PUT(SCANKEY_NULL, HWP_Cap_Attr[bix], width, 3,
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.5/x86_64/corefreqk.c
new/CoreFreq-1.98.6/x86_64/corefreqk.c
--- old/CoreFreq-1.98.5/x86_64/corefreqk.c 2024-11-01 08:57:26.000000000
+0100
+++ new/CoreFreq-1.98.6/x86_64/corefreqk.c 2024-11-16 13:35:40.000000000
+0100
@@ -2215,8 +2215,6 @@
};
/* Fn8000_001D Cache Properties. */
unsigned long idx, level[CACHE_MAX_LEVEL] = {1, 0, 2, 3};
- /* Skip one CDD on two with Threadripper. */
- unsigned int factor = 0;
for (idx = 0; idx < CACHE_MAX_LEVEL; idx++ ) {
__asm__ volatile
@@ -2267,93 +2265,51 @@
{ /* SMT is enabled . */
Core->T.ThreadID = leaf8000001e.EAX.ExtApicId & 1;
- /* CCD factor for [x24 ... x384] SMT EPYC & Threadripper */
- factor = (leaf80000008.ECX.NC == 0xff)
- || (leaf80000008.ECX.NC == 0xdf)
- || (leaf80000008.ECX.NC == 0xbf)
- || (leaf80000008.ECX.NC == 0xa7)
- || (leaf80000008.ECX.NC == 0x8f)
- || (leaf80000008.ECX.NC == 0x7f)
- || (leaf80000008.ECX.NC == 0x5f)
- || (leaf80000008.ECX.NC == 0x3f)
- || (leaf80000008.ECX.NC == 0x2f)
-
- || ((leaf80000008.ECX.F1Ah.NC == 0x17f)
- && ((PUBLIC(RO(Proc))->ArchID == AMD_Zen5_Turin)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen5_Turin_Dense)))
-
- || ((leaf80000008.ECX.F1Ah.NC == 0x13f)
- && ((PUBLIC(RO(Proc))->ArchID == AMD_Zen5_Turin)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen5_Turin_Dense)))
-
- || ((leaf80000008.ECX.F1Ah.NC == 0x11f)
- && ((PUBLIC(RO(Proc))->ArchID == AMD_Zen5_Turin)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen5_Turin_Dense)))
-
- || ((leaf80000008.ECX.NC == 0x1f)
- && ((PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Rome_CPK)
- || (PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Milan)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Chagall)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Badami)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Genoa)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Bergamo)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_STP)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen5_Turin)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen5_Turin_Dense)))
-
- || ((leaf80000008.ECX.NC == 0x17)
- && ((PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Rome_CPK)
- || (PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Milan)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Chagall)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Badami)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Genoa)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Bergamo)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_STP)));
}
else
{ /* SMT is disabled. */
Core->T.ThreadID = 0;
-
- /* CCD factor for [x12 ... x192] physical EPYC & Threadripper */
- factor = (leaf80000008.ECX.NC == 0xbf)
- || (leaf80000008.ECX.NC == 0x9f)
- || (leaf80000008.ECX.NC == 0x8f)
- || (leaf80000008.ECX.NC == 0x7f)
- || (leaf80000008.ECX.NC == 0x6f)
- || (leaf80000008.ECX.NC == 0x5f)
- || (leaf80000008.ECX.NC == 0x53)
- || (leaf80000008.ECX.NC == 0x3f)
- || (leaf80000008.ECX.NC == 0x2f)
- || (leaf80000008.ECX.NC == 0x1f)
- || (leaf80000008.ECX.NC == 0x17)
-
- || ((leaf80000008.ECX.NC == 0x0f)
- && ((PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Rome_CPK)
- || (PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Milan)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Chagall)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Badami)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Genoa)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Bergamo)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_STP)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen5_Turin)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen5_Turin_Dense)))
-
- || ((leaf80000008.ECX.NC == 0x0b)
- && ((PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Rome_CPK)
- || (PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Milan)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Chagall)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Badami)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Genoa)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Bergamo)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_STP)));
}
- /* CCD has to remain within range values from 0 to 7 */
- factor = factor & (Core->T.CoreID < 32);
Core->T.Cluster.Node = leaf8000001e.ECX.NodeId;
+ if (PUBLIC(RO(Proc))->Features.Info.LargestExtFunc >= 0x80000026)
+ {
+ CPUID_0x80000026 leaf80000026 = {
+ .EAX = {0}, .EBX = {0}, .ECX = {0}, .EDX = {0}
+ };
+ __asm__ volatile
+ (
+ "movq $0x80000026, %%rax \n\t"
+ "xorq %%rbx, %%rbx \n\t"
+ "xorq %%rcx, %%rcx \n\t"
+ "xorq %%rdx, %%rdx \n\t"
+ "cpuid \n\t"
+ "mov %%eax, %0 \n\t"
+ "mov %%ebx, %1 \n\t"
+ "mov %%ecx, %2 \n\t"
+ "mov %%edx, %3"
+ : "=r" (leaf80000026.EAX),
+ "=r" (leaf80000026.EBX),
+ "=r" (leaf80000026.ECX),
+ "=r" (leaf80000026.EDX)
+ :
+ : "%rax", "%rbx", "%rcx", "%rdx"
+ );
+ if ( ((PUBLIC(RO(Proc))->ArchID == AMD_Zen5_Turin)
+ || (PUBLIC(RO(Proc))->ArchID == AMD_Zen5_Turin_Dense))
+ && (leaf80000008.ECX.F1Ah.NC > 0xff) )
+ {
+ Core->T.Cluster.CCD=(leaf80000026.EDX.Extended_APIC_ID & 0xf00);
+ Core->T.Cluster.CCD= Core->T.Cluster.CCD >> 8;
+ } else {
+ Core->T.Cluster.CCD=(leaf80000026.EDX.Extended_APIC_ID & 0xf0);
+ Core->T.Cluster.CCD= Core->T.Cluster.CCD >> 4;
+ }
+ } else {
+ Core->T.Cluster.CCD = (Core->T.ApicID & 0xf0) >> 4;
+ }
if (CPU_Complex == true ) {
- Core->T.Cluster.CCD = (Core->T.CoreID >> 3) << factor;
Core->T.Cluster.CCX = Core->T.CoreID >> 2;
}
} else { /* Fallback algorithm. */
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.5/x86_64/corefreqk.h
new/CoreFreq-1.98.6/x86_64/corefreqk.h
--- old/CoreFreq-1.98.5/x86_64/corefreqk.h 2024-11-01 08:57:26.000000000
+0100
+++ new/CoreFreq-1.98.6/x86_64/corefreqk.h 2024-11-16 13:35:40.000000000
+0100
@@ -6679,6 +6679,17 @@
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
+ {
+ .Brand = ZLIST("AMD Ryzen Embedded V2A46"),
+ .Boost = {+2, 0},
+ .Param.Offset = {105, 0, 0},
+ .CodeNameIdx = CN_GREY_HAWK,
+ .TgtRatioUnlocked = 1,
+ .ClkRatioUnlocked = 0b10,
+ .TurboUnlocked = 0,
+ .UncoreUnlocked = 0,
+ .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
+ },
{0}
};
static PROCESSOR_SPECIFIC AMD_Zen2_LCN_Specific[] = {
