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Hello community,
here is the log from the commit of package CoreFreq for openSUSE:Factory
checked in at 2024-11-22 23:52:13
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/CoreFreq (Old)
and /work/SRC/openSUSE:Factory/.CoreFreq.new.28523 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "CoreFreq"
Fri Nov 22 23:52:13 2024 rev:40 rq:1225774 version:1.98.7
Changes:
--------
--- /work/SRC/openSUSE:Factory/CoreFreq/CoreFreq.changes 2024-11-17
16:42:10.957684689 +0100
+++ /work/SRC/openSUSE:Factory/.CoreFreq.new.28523/CoreFreq.changes
2024-11-22 23:52:55.052879243 +0100
@@ -1,0 +2,13 @@
+Fri Nov 22 09:42:29 UTC 2024 - Michael Pujos <pujos.mich...@gmail.com>
+
+- Update to 1.98.7
+ * [AMD]
+ - [Family 1Ah][Granite Ridge]
+ - P-State programming fix
+ - Merge PCI identifier lists
+ - Reserve the BTC-NOBR aggregation to Zen2 architecture
+ * [AArch64]
+ - Query and JSON export Hypervisor Configuration Register HCR_EL2
+ - Experimental mode required
+
+-------------------------------------------------------------------
Old:
----
CoreFreq-1.98.6.tar.gz
New:
----
CoreFreq-1.98.7.tar.gz
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ CoreFreq.spec ++++++
--- /var/tmp/diff_new_pack.tbGdOJ/_old 2024-11-22 23:52:56.332932570 +0100
+++ /var/tmp/diff_new_pack.tbGdOJ/_new 2024-11-22 23:52:56.332932570 +0100
@@ -17,7 +17,7 @@
Name: CoreFreq
-Version: 1.98.6
+Version: 1.98.7
Release: 0
Summary: CPU monitoring software for 64-bit processors
License: GPL-2.0-or-later
++++++ CoreFreq-1.98.6.tar.gz -> CoreFreq-1.98.7.tar.gz ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.6/Makefile new/CoreFreq-1.98.7/Makefile
--- old/CoreFreq-1.98.6/Makefile 2024-11-16 13:35:40.000000000 +0100
+++ new/CoreFreq-1.98.7/Makefile 2024-11-19 21:23:20.000000000 +0100
@@ -4,7 +4,7 @@
COREFREQ_MAJOR = 1
COREFREQ_MINOR = 98
-COREFREQ_REV = 6
+COREFREQ_REV = 7
HW = $(shell uname -m)
CC ?= cc
WARNING = -Wall -Wfatal-errors
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.6/aarch64/corefreq-api.h
new/CoreFreq-1.98.7/aarch64/corefreq-api.h
--- old/CoreFreq-1.98.6/aarch64/corefreq-api.h 2024-11-16 13:35:40.000000000
+0100
+++ new/CoreFreq-1.98.7/aarch64/corefreq-api.h 2024-11-19 21:23:20.000000000
+0100
@@ -200,6 +200,7 @@
struct {
Bit64 FLAGS __attribute__ ((aligned (8)));
+ Bit64 HCR __attribute__ ((aligned (8)));
Bit64 SCTLR __attribute__ ((aligned (8)));
Bit64 SCTLR2 __attribute__ ((aligned (8)));
Bit64 EL __attribute__ ((aligned (8)));
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.6/aarch64/corefreq-cli-json.c
new/CoreFreq-1.98.7/aarch64/corefreq-cli-json.c
--- old/CoreFreq-1.98.6/aarch64/corefreq-cli-json.c 2024-11-16
13:35:40.000000000 +0100
+++ new/CoreFreq-1.98.7/aarch64/corefreq-cli-json.c 2024-11-19
21:23:20.000000000 +0100
@@ -1391,6 +1391,10 @@
json_key(&s, "FLAGS");
json_string(&s, hexStr);
+ snprintf(hexStr, 32, "0x%llx",
RO(Shm)->Cpu[cpu].SystemRegister.HCR);
+ json_key(&s, "HCR");
+ json_string(&s, hexStr);
+
snprintf(hexStr, 32, "0x%llx",
RO(Shm)->Cpu[cpu].SystemRegister.SCTLR);
json_key(&s, "SCTLR");
json_string(&s, hexStr);
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.6/aarch64/corefreq.h
new/CoreFreq-1.98.7/aarch64/corefreq.h
--- old/CoreFreq-1.98.6/aarch64/corefreq.h 2024-11-16 13:35:40.000000000
+0100
+++ new/CoreFreq-1.98.7/aarch64/corefreq.h 2024-11-19 21:23:20.000000000
+0100
@@ -187,6 +187,7 @@
struct {
Bit64 FLAGS __attribute__ ((aligned (8)));
+ Bit64 HCR __attribute__ ((aligned (8)));
Bit64 SCTLR __attribute__ ((aligned (8)));
Bit64 SCTLR2 __attribute__ ((aligned (8)));
Bit64 EL __attribute__ ((aligned (8)));
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.6/aarch64/corefreqd.c
new/CoreFreq-1.98.7/aarch64/corefreqd.c
--- old/CoreFreq-1.98.6/aarch64/corefreqd.c 2024-11-16 13:35:40.000000000
+0100
+++ new/CoreFreq-1.98.7/aarch64/corefreqd.c 2024-11-19 21:23:20.000000000
+0100
@@ -860,6 +860,9 @@
RO(Shm)->Cpu[cpu].SystemRegister.FLAGS = \
RO(Core, AT(cpu))->SystemRegister.FLAGS;
+ RO(Shm)->Cpu[cpu].SystemRegister.HCR = \
+ RO(Core, AT(cpu))->SystemRegister.HCR;
+
RO(Shm)->Cpu[cpu].SystemRegister.SCTLR = \
RO(Core, AT(cpu))->SystemRegister.SCTLR;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.6/aarch64/corefreqk.c
new/CoreFreq-1.98.7/aarch64/corefreqk.c
--- old/CoreFreq-1.98.6/aarch64/corefreqk.c 2024-11-16 13:35:40.000000000
+0100
+++ new/CoreFreq-1.98.7/aarch64/corefreqk.c 2024-11-19 21:23:20.000000000
+0100
@@ -2449,6 +2449,14 @@
isar2.value = SysRegRead(ID_AA64ISAR2_EL1);
+ if (Experimental) {
+ __asm__ __volatile__(
+ "mrs %[hcr] , hcr_el2"
+ : [hcr] "=r" (Core->SystemRegister.HCR)
+ :
+ : "cc", "memory"
+ );
+ }
__asm__ __volatile__(
"mrs %[sctlr], sctlr_el1" "\n\t"
"mrs %[mmfr1], id_aa64mmfr1_el1""\n\t"
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.6/x86_64/corefreqd.c
new/CoreFreq-1.98.7/x86_64/corefreqd.c
--- old/CoreFreq-1.98.6/x86_64/corefreqd.c 2024-11-16 13:35:40.000000000
+0100
+++ new/CoreFreq-1.98.7/x86_64/corefreqd.c 2024-11-19 21:23:20.000000000
+0100
@@ -2183,11 +2183,6 @@
Mitigation_2nd_Stage(RO(Shm), RO(Proc), RW(Proc));
- RO(Shm)->Proc.Mechanisms.BTC_NOBR = (
- RO(Shm)->Proc.Features.leaf80000008.EBX.STIBP == 1
- );
- RO(Shm)->Proc.Mechanisms.BTC_NOBR += (2 * BTC_NOBR);
-
switch (RO(Shm)->Proc.ArchID) {
case AMD_EPYC_Rome_CPK:
case AMD_Zen2_Renoir:
@@ -2197,6 +2192,11 @@
case AMD_Zen2_Jupiter:
case AMD_Zen2_Galileo:
case AMD_Zen2_MDN:
+ RO(Shm)->Proc.Mechanisms.BTC_NOBR = (
+ RO(Shm)->Proc.Features.leaf80000008.EBX.STIBP == 1
+ );
+ RO(Shm)->Proc.Mechanisms.BTC_NOBR += (2 * BTC_NOBR);
+
RO(Shm)->Proc.Mechanisms.XPROC_LEAK = \
BITCMP_CC(LOCKLESS,
RW(Proc)->XPROC_LEAK,
@@ -2208,6 +2208,7 @@
RO(Proc)->BTC_NOBR_Mask) ? 0b11 : 0b10;
break;
default:
+ RO(Shm)->Proc.Mechanisms.BTC_NOBR = 0;
RO(Shm)->Proc.Mechanisms.XPROC_LEAK = 0;
RO(Shm)->Proc.Mechanisms.AGENPICK = 0;
break;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.6/x86_64/corefreqk.c
new/CoreFreq-1.98.7/x86_64/corefreqk.c
--- old/CoreFreq-1.98.6/x86_64/corefreqk.c 2024-11-16 13:35:40.000000000
+0100
+++ new/CoreFreq-1.98.7/x86_64/corefreqk.c 2024-11-19 21:23:20.000000000
+0100
@@ -8095,28 +8095,37 @@
}
inline COF_ST AMD_Zen_CoreCOF(PSTATEDEF PStateDef)
-{/* Source: PPR for AMD Family 17h Model 01h, Revision B1 Processors
- CoreCOF = (PStateDef[CpuFid[7:0]] / PStateDef[CpuDfsId]) * 200 */
+{
unsigned long remainder;
COF_ST COF;
- if (PStateDef.Family_17h.CpuDfsId > 0b111) {
- COF.Q = (PStateDef.Family_17h.CpuFid << 1)
- / PStateDef.Family_17h.CpuDfsId;
- remainder = (UNIT_KHz(1) * (PStateDef.Family_17h.CpuFid
- - ((COF.Q * PStateDef.Family_17h.CpuDfsId) >> 1))) >> 2;
- COF.R = (unsigned short) remainder;
- } else switch (PUBLIC(RO(Proc))->Features.Std.EAX.ExtFamily) {
- case 0xB: /* Zen5: Granite Ridge, Strix Point, Turin */
+ switch (PUBLIC(RO(Proc))->Features.Std.EAX.ExtFamily) {
+ case 0xB:
+ /* Source: PPR Family 1Ah Model 02h.
+ * Arch: Granite Ridge, Strix Point, Turin, Dense
+ * CoreCOF = Core::X86::Msr::PStateDef[CpuFid[11:0]] * 5 MHz
+ */
COF.Q = (PStateDef.Family_1Ah.CpuFid >> 1) / 10;
remainder = (PRECISION * PStateDef.Family_1Ah.CpuFid) >> 1;
remainder = remainder - (UNIT_KHz(1) * COF.Q);
COF.R = (unsigned short) remainder;
break;
- default:
+ default:
+ /* Source: PPR for AMD Family 17h Model 01h, Revision B1 Processors
+ * CoreCOF = (PStateDef[CpuFid[7:0]] / PStateDef[CpuDfsId]) * 200
+ */
+ if (PStateDef.Family_17h.CpuDfsId != 0)
+ {
+ COF.Q = (PStateDef.Family_17h.CpuFid << 1)
+ / PStateDef.Family_17h.CpuDfsId;
+ remainder = (UNIT_KHz(1) * (PStateDef.Family_17h.CpuFid
+ - ((COF.Q * PStateDef.Family_17h.CpuDfsId) >> 1))) >> 2;
+ COF.R = (unsigned short) remainder;
+ } else {
COF.Q = PStateDef.Family_17h.CpuFid >> 2;
COF.R = 0;
+ }
break;
- }
+ }
return COF;
}
@@ -8138,16 +8147,36 @@
}
}
+inline unsigned short AMD_Zen5_Compute_FID( unsigned int COF,
+ unsigned int *FID )
+{
+ unsigned int tmp = (COF << 1) * 10;
+ if ((tmp >= 0x10) && (tmp <= 0xfff)) {
+ (*FID) = tmp;
+ return 0;
+ } else {
+ return 1;
+ }
+}
+
static unsigned short AMD_Zen_CoreFID( unsigned int COF,
unsigned int *FID,
unsigned int *DID )
{
- unsigned short ret = AMD_Zen_Compute_FID_DID(COF, FID, DID);
+ unsigned short ret;
+ switch (PUBLIC(RO(Proc))->Features.Std.EAX.ExtFamily) {
+ case 0xB:
+ ret = AMD_Zen5_Compute_FID(COF, FID);
+ break;
+ default:
+ ret = AMD_Zen_Compute_FID_DID(COF, FID, DID);
while ((ret != 0) && ((*DID) > 0))
{
(*DID) = (*DID) >> 1;
ret = AMD_Zen_Compute_FID_DID(COF, FID, DID);
}
+ break;
+ }
return ret;
}
@@ -8332,7 +8361,7 @@
CLOCK_ZEN_ARG *pClockZen = (CLOCK_ZEN_ARG *) arg;
PSTATEDEF PstateDef = {.value = 0};
COF_ST COF = {.Q = 0, .R = 0};
- unsigned int FID, DID;
+ unsigned int FID, DID = 0;
const unsigned int smp = pClockZen->pClockMod->cpu == -1 ?
smp_processor_id() : pClockZen->pClockMod->cpu;
@@ -8351,13 +8380,27 @@
COF.Q = COF.Q + pClockZen->pClockMod->Offset;
}
- FID = PstateDef.Family_17h.CpuFid;
- DID = PstateDef.Family_17h.CpuDfsId;
+ switch (PUBLIC(RO(Proc))->Features.Std.EAX.ExtFamily) {
+ case 0xB:
+ FID = PstateDef.Family_1Ah.CpuFid;
+ break;
+ default:
+ FID = PstateDef.Family_17h.CpuFid;
+ DID = PstateDef.Family_17h.CpuDfsId;
+ break;
+ }
/* Attempt to write the P-State MSR with new FID and DID */
if (AMD_Zen_CoreFID(COF.Q, &FID, &DID) == 0)
{
- PstateDef.Family_17h.CpuFid = FID;
- PstateDef.Family_17h.CpuDfsId = DID;
+ switch (PUBLIC(RO(Proc))->Features.Std.EAX.ExtFamily) {
+ case 0xB:
+ PstateDef.Family_1Ah.CpuFid = FID;
+ break;
+ default:
+ PstateDef.Family_17h.CpuFid = FID;
+ PstateDef.Family_17h.CpuDfsId = DID;
+ break;
+ }
WRMSR(PstateDef, pClockZen->PstateAddr);
pClockZen->rc = RC_OK_COMPUTE;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.6/x86_64/corefreqk.h
new/CoreFreq-1.98.7/x86_64/corefreqk.h
--- old/CoreFreq-1.98.6/x86_64/corefreqk.h 2024-11-16 13:35:40.000000000
+0100
+++ new/CoreFreq-1.98.7/x86_64/corefreqk.h 2024-11-19 21:23:20.000000000
+0100
@@ -3442,13 +3442,7 @@
PCI_VDEVICE(AMD, DID_AMD_19H_PHOENIX_DF_UMC),
.driver_data = (kernel_ulong_t) AMD_DataFabric_Phoenix
},
- {0, }
-};
-
-#define PCI_AMD_19h_ids PCI_AMD_17h_ids
-
/* AMD Family 1Ah */
-static struct pci_device_id PCI_AMD_1Ah_ids[] = {
{
PCI_VDEVICE(AMD, DID_AMD_1AH_ZEN5_TURIN_IOMMU),
.driver_data = (kernel_ulong_t) AMD_Zen_IOMMU
@@ -3460,6 +3454,9 @@
{0, }
};
+#define PCI_AMD_19h_ids PCI_AMD_17h_ids
+#define PCI_AMD_1Ah_ids PCI_AMD_17h_ids
+
/* Left as empty for initialization purpose. */
static char *Arch_Misc_Processor[] = ZLIST(NULL);
